JPH0533423B2 - - Google Patents

Info

Publication number
JPH0533423B2
JPH0533423B2 JP61023782A JP2378286A JPH0533423B2 JP H0533423 B2 JPH0533423 B2 JP H0533423B2 JP 61023782 A JP61023782 A JP 61023782A JP 2378286 A JP2378286 A JP 2378286A JP H0533423 B2 JPH0533423 B2 JP H0533423B2
Authority
JP
Japan
Prior art keywords
logic
model
function model
logic circuit
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61023782A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62182939A (ja
Inventor
Nobuhiko Onizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61023782A priority Critical patent/JPS62182939A/ja
Priority to US07/011,068 priority patent/US4918594A/en
Publication of JPS62182939A publication Critical patent/JPS62182939A/ja
Publication of JPH0533423B2 publication Critical patent/JPH0533423B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP61023782A 1986-02-07 1986-02-07 情報処理装置の論理シミユレ−シヨン方法 Granted JPS62182939A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61023782A JPS62182939A (ja) 1986-02-07 1986-02-07 情報処理装置の論理シミユレ−シヨン方法
US07/011,068 US4918594A (en) 1986-02-07 1987-02-04 Method and system for logical simulation of information processing system including logic circuit model and logic function model

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61023782A JPS62182939A (ja) 1986-02-07 1986-02-07 情報処理装置の論理シミユレ−シヨン方法

Publications (2)

Publication Number Publication Date
JPS62182939A JPS62182939A (ja) 1987-08-11
JPH0533423B2 true JPH0533423B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-05-19

Family

ID=12119893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61023782A Granted JPS62182939A (ja) 1986-02-07 1986-02-07 情報処理装置の論理シミユレ−シヨン方法

Country Status (2)

Country Link
US (1) US4918594A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS62182939A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01209542A (ja) * 1988-02-17 1989-08-23 Hitachi Ltd 論理検証装置
JPH01243136A (ja) * 1988-03-24 1989-09-27 Hitachi Ltd 論理シミュレーション方式
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5572708A (en) * 1989-02-28 1996-11-05 Nec Corporation Hardware simulator capable of dealing with a description of a functional level
US5561787A (en) * 1989-03-07 1996-10-01 Xerox Corporation User interface module
US5369593A (en) 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
US5353243A (en) 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
US5276811A (en) * 1989-06-30 1994-01-04 Icom, Inc. Method for emulating programmable logic controller by exchanging information between debug program which emulates I/O devices and ladder logic program
JPH0362202A (ja) * 1989-07-31 1991-03-18 Japan Electron Control Syst Co Ltd 制御プログラム開発装置
EP0416669B1 (en) * 1989-09-05 1998-09-09 Lsi Logic Corporation Logic compiler for design of circuit models
US5179672A (en) * 1990-06-19 1993-01-12 International Business Machines Corporation Apparatus and method for modeling parallel processing of instructions using sequential execution hardware
US5438673A (en) * 1990-08-17 1995-08-01 Cray Research, Inc. Automatic interface for CPU real machine and logic simulator diagnostics
GB9023633D0 (en) * 1990-10-31 1990-12-12 Int Computers Ltd Predicting the performance of a computer system
US5410678A (en) * 1991-01-11 1995-04-25 Nec Corporation Fault simulator comprising a signal generating circuit implemented by hardware
US5490266A (en) * 1991-03-01 1996-02-06 Altera Corporation Process oriented logic simulation having stability checking
US5652869A (en) * 1991-03-07 1997-07-29 Digital Equipment Corporation System for executing and debugging multiple codes in a multi-architecture environment using jacketing means for jacketing the cross-domain calls
EP0532744B1 (en) * 1991-03-07 1996-12-18 Digital Equipment Corporation Improved software debugging system and method especially adapted for code debugging within a multi-architecture environment
US5884065A (en) * 1992-01-10 1999-03-16 Nec Corporation Logic circuit apparatus and method for sequentially performing one of a fault-free simulation and a fault simulation through various levels of a logic circuit
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5493672A (en) * 1994-05-16 1996-02-20 Sun Microsystems, Inc. Concurrent simulation of host system at instruction level and input/output system at logic level with two-way communication deadlock resolution
GB9413127D0 (en) * 1994-06-30 1994-08-24 Philips Electronics Uk Ltd Data processing apparatus
US5857091A (en) * 1995-03-14 1999-01-05 Siemens Business Communication Systems, Inc. Machine and method for simulating a processor-based digital system
US6053948A (en) * 1995-06-07 2000-04-25 Synopsys, Inc. Method and apparatus using a memory model
GB2301911B (en) * 1995-06-08 2000-01-12 Advanced Risc Mach Ltd Simulation of digital circuits
US5809283A (en) * 1995-09-29 1998-09-15 Synopsys, Inc. Simulator for simulating systems including mixed triggers
US5784593A (en) * 1995-09-29 1998-07-21 Synopsys, Inc. Simulator including process levelization
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6421251B1 (en) 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6192290B1 (en) * 1998-05-21 2001-02-20 Lucent Technologies Inc. System and method of manufacturing semicustom integrated circuits using reticle primitives from a library and interconnect reticles
US6618698B1 (en) 1999-08-12 2003-09-09 Quickturn Design Systems, Inc. Clustered processors in an emulation engine
US6853968B2 (en) * 2000-01-20 2005-02-08 Arm Limited Simulation of data processing apparatus
US6980941B2 (en) * 2001-01-31 2005-12-27 Kabushiki Kaisha Toshiba Method and computer program product for realizing a system specification which is described in a system description language
JP3930255B2 (ja) * 2001-01-31 2007-06-13 株式会社東芝 システム仕様情報処理装置、システム仕様情報処理方法及びプログラム
CN115312110A (zh) * 2021-05-08 2022-11-08 瑞昱半导体股份有限公司 芯片验证系统及其验证方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55153054A (en) * 1979-05-15 1980-11-28 Hitachi Ltd Logic circuit simulation system
US4656580A (en) * 1982-06-11 1987-04-07 International Business Machines Corporation Logic simulation machine
EP0099114B1 (en) * 1982-07-13 1988-05-11 Nec Corporation Logic simulator operable on level basis and on logic block basis on each level
US4527249A (en) * 1982-10-22 1985-07-02 Control Data Corporation Simulator system for logic design validation
JPS59148971A (ja) * 1983-02-14 1984-08-25 Hitachi Ltd 論理回路シミュレ−ション方法
JPS59151247A (ja) * 1983-02-18 1984-08-29 Hitachi Ltd 情報処理装置の試験装置
JPS59195751A (ja) * 1983-04-22 1984-11-06 Hitachi Ltd 情報処理装置の診断方式
US4635218A (en) * 1983-05-09 1987-01-06 Valid Logic Systems Method for simulating system operation of static and dynamic circuit devices
JPS6091455A (ja) * 1983-10-24 1985-05-22 Fujitsu Ltd 論理回路のシミユレ−シヨン方式
US4628471A (en) * 1984-02-02 1986-12-09 Prime Computer, Inc. Digital system simulation method and apparatus having two signal-level modes of operation
JPS60237573A (ja) * 1984-05-11 1985-11-26 Hitachi Ltd システム機能シミユレ−シヨン方法
JPS60254351A (ja) * 1984-05-31 1985-12-16 Fujitsu Ltd サブセツトシミユレ−タ
FR2568015B1 (fr) * 1984-07-18 1986-08-08 Commissariat Energie Atomique Systeme de test de la defaillance ou du bon fonctionnement d'un circuit a composants logiques
JPS6142040A (ja) * 1984-08-03 1986-02-28 Nec Corp 論理シミユレ−タ
US4763289A (en) * 1985-12-31 1988-08-09 International Business Machines Corporation Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits

Also Published As

Publication number Publication date
US4918594A (en) 1990-04-17
JPS62182939A (ja) 1987-08-11

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Legal Events

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EXPY Cancellation because of completion of term