JPH05206373A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPH05206373A
JPH05206373A JP1266492A JP1266492A JPH05206373A JP H05206373 A JPH05206373 A JP H05206373A JP 1266492 A JP1266492 A JP 1266492A JP 1266492 A JP1266492 A JP 1266492A JP H05206373 A JPH05206373 A JP H05206373A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
capacitor
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1266492A
Other languages
English (en)
Inventor
Shinobu Himei
志乃夫 姫井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP1266492A priority Critical patent/JPH05206373A/ja
Publication of JPH05206373A publication Critical patent/JPH05206373A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

(57)【要約】 【目的】本発明はますます高性能化する集積回路におい
て、その動作時に発生するノイズを極力低減することを
目的とする。 【構成】リードフレーム上のできるだけ集積回路チップ
の近くいコンデンサを形成する。 【効果】集積回路チップのすぐ近くにコンデンサを形成
することにより高速動作時のノイズ発生をパッケージ外
にノイズ防止コンデンサをとりつける場合よりも、更に
効果的に低減することができる。また実装時にコンデン
サの取付が必要なくなり高密度実装が可能になる。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体集積回路に関す
る。
【０００２】
【従来の技術】従来の技術としては、図３に示すよう
に、セラミックＰＧＡケース５に半導体集積回路チップ
１を搭載し、ケース上にコンデンサ４を搭載した適用例
があるが、樹脂封止品においてはリードフレームにコン
デンサを形成することはなかった。
【０００３】
【発明が解決しようとする課題】上述した従来の技術で
は、ますます高速動作高精度化する集積回路装置にノイ
ズの発生で悪影響を与える危険があるという欠点があ
る。
【０００４】高速動作の為に電流電圧変動が激しくな
り、集積回路装置の電源変動が大きくなってスレッシュ
ホールド電圧の変動信号伝播の遅れをひきおこし、また
動作マージンの低下をひきおこす危険がある。
【０００５】
【課題を解決するための手段】上述した従来の技術に対
し、本発明はリードフレーム上にコンデンサを形成しこ
のコンデンサにより集積回路装置が動作する際に発生す
るノイズを効果的に低減する。
【０００６】
【実施例】次に本発明について図面を参照して説明す
る。図１（Ａ），（Ｂ）および図２は本発明の一実施例
である。図１（Ａ）は断面図、図１（Ｂ）、図２平面図
である。
【０００７】図１に示すように、バウンダリレイヤーコ
ンデンサ４をリードフレームのアイランド部６上に半田
付けし、このバウンダリレイヤーコンデンサ４上に半導
体集積回路チップ１をマウントしている。半導体集積回
路チップはボンディングワイヤー２によりリード３と電
気的に接続している。半導体集積回路チップ１、アイラ
ンド部６、ボンディングワイヤー２等は樹脂（図示省
略）により封止される。
【０００８】図２は第２の実施例で、チップコンデンサ
４をリード間にまたがって搭載しており、半導体集積回
路チップ１は直にアイランド部３にマウンされている。
この他の部分は先の実施例と同じである。
【０００９】
【発明の効果】以上説明したように本発明はリードフレ
ーム上にコンデンサを形成することにより集積回路装置
の動作時に発生するノイズを効果的に低減できるという
効果を有する。
【００１０】また、従来集積回路装置のプリント板等へ
の実装時に必要としていたノイズ防止用のコンデンサの
とりつけが必要なくなるという効果を有する。
【図面の簡単な説明】
【図１】（Ａ）は本発明の一実施例の断面図、（Ｂ）は
（Ａ）の平面図。
【図２】コンデンサの位置を変更第２実施例の平面図。
【図３】従来技術例（ＰＧＡケース）の概略図。
【符号の説明】
１ 半導体集積回路チップ ２ ボンディングワイヤー ３ リード ４ コンデンサ ５ ＰＧＡケース ６ アイランド部

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 リードフレームのアイランド部に半導体
    集積回路チップを搭載し、樹脂封止して成る半導体集積
    回路装置において、リードフレームのリード間あるいは
    前記アイランド部上にあらかじめコンデンサーを形成し
    たことを特徴とする半導体集積回路装置。
JP1266492A 1992-01-28 1992-01-28 半導体集積回路装置 Pending JPH05206373A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1266492A JPH05206373A (ja) 1992-01-28 1992-01-28 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1266492A JPH05206373A (ja) 1992-01-28 1992-01-28 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPH05206373A true JPH05206373A (ja) 1993-08-13

Family

ID=11811637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1266492A Pending JPH05206373A (ja) 1992-01-28 1992-01-28 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPH05206373A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246536A (ja) * 2001-02-14 2002-08-30 Ibiden Co Ltd 三次元実装パッケージの製造方法、及びその製造用のパッケージモジュール

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58191460A (ja) * 1982-04-30 1983-11-08 Matsushita Electric Works Ltd 電子部品
JPS5948949A (ja) * 1982-09-13 1984-03-21 Matsushita Electric Ind Co Ltd 混成集積回路部品
JPS5972757A (ja) * 1982-10-20 1984-04-24 Fujitsu Ltd 半導体装置
JPS63132459A (ja) * 1986-11-25 1988-06-04 Hitachi Ltd 容量内蔵半導体パツケ−ジ
JPH02296360A (ja) * 1989-05-10 1990-12-06 Ricoh Co Ltd 裏面にコンデンサをもつ半導体装置
JPH04162657A (ja) * 1990-10-26 1992-06-08 Hitachi Ltd 半導体装置用リードフレーム
JPH04188759A (ja) * 1990-11-21 1992-07-07 Mitsubishi Electric Corp 半導体集積回路装置
JPH0582697A (ja) * 1991-09-20 1993-04-02 Nippondenso Co Ltd 半導体装置のリードフレーム

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58191460A (ja) * 1982-04-30 1983-11-08 Matsushita Electric Works Ltd 電子部品
JPS5948949A (ja) * 1982-09-13 1984-03-21 Matsushita Electric Ind Co Ltd 混成集積回路部品
JPS5972757A (ja) * 1982-10-20 1984-04-24 Fujitsu Ltd 半導体装置
JPS63132459A (ja) * 1986-11-25 1988-06-04 Hitachi Ltd 容量内蔵半導体パツケ−ジ
JPH02296360A (ja) * 1989-05-10 1990-12-06 Ricoh Co Ltd 裏面にコンデンサをもつ半導体装置
JPH04162657A (ja) * 1990-10-26 1992-06-08 Hitachi Ltd 半導体装置用リードフレーム
JPH04188759A (ja) * 1990-11-21 1992-07-07 Mitsubishi Electric Corp 半導体集積回路装置
JPH0582697A (ja) * 1991-09-20 1993-04-02 Nippondenso Co Ltd 半導体装置のリードフレーム

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246536A (ja) * 2001-02-14 2002-08-30 Ibiden Co Ltd 三次元実装パッケージの製造方法、及びその製造用のパッケージモジュール
JP4694007B2 (ja) * 2001-02-14 2011-06-01 イビデン株式会社 三次元実装パッケージの製造方法

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