JPH05160292A - 多層パッケージ - Google Patents

多層パッケージ

Info

Publication number
JPH05160292A
JPH05160292A JP4139006A JP13900692A JPH05160292A JP H05160292 A JPH05160292 A JP H05160292A JP 4139006 A JP4139006 A JP 4139006A JP 13900692 A JP13900692 A JP 13900692A JP H05160292 A JPH05160292 A JP H05160292A
Authority
JP
Japan
Prior art keywords
conductor layer
layer
conductor
connection point
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4139006A
Other languages
English (en)
Japanese (ja)
Inventor
Naohiko Hirano
尚彦 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4139006A priority Critical patent/JPH05160292A/ja
Priority to US07/893,807 priority patent/US5309024A/en
Priority to EP92109550A priority patent/EP0517247B1/en
Priority to DE69232012T priority patent/DE69232012T2/de
Publication of JPH05160292A publication Critical patent/JPH05160292A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/451—Multilayered leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/464—Additional interconnections in combination with leadframes
    • H10W70/467—Multilayered additional interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP4139006A 1991-06-06 1992-05-29 多層パッケージ Pending JPH05160292A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP4139006A JPH05160292A (ja) 1991-06-06 1992-05-29 多層パッケージ
US07/893,807 US5309024A (en) 1991-06-06 1992-06-04 Multilayer package
EP92109550A EP0517247B1 (en) 1991-06-06 1992-06-05 Multilayer package
DE69232012T DE69232012T2 (de) 1991-06-06 1992-06-05 Mehrschichtpackung

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3-134613 1991-06-06
JP13461391 1991-06-06
JP4139006A JPH05160292A (ja) 1991-06-06 1992-05-29 多層パッケージ

Publications (1)

Publication Number Publication Date
JPH05160292A true JPH05160292A (ja) 1993-06-25

Family

ID=26468670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4139006A Pending JPH05160292A (ja) 1991-06-06 1992-05-29 多層パッケージ

Country Status (4)

Country Link
US (1) US5309024A (https=)
EP (1) EP0517247B1 (https=)
JP (1) JPH05160292A (https=)
DE (1) DE69232012T2 (https=)

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US5634821A (en) * 1992-12-01 1997-06-03 Crane, Jr.; Stanford W. High-density electrical interconnect system
TW238431B (https=) * 1992-12-01 1995-01-11 Stanford W Crane Jr
US5338970A (en) * 1993-03-24 1994-08-16 Intergraph Corporation Multi-layered integrated circuit package with improved high frequency performance
JP3287673B2 (ja) * 1993-11-30 2002-06-04 富士通株式会社 半導体装置
US5679978A (en) * 1993-12-06 1997-10-21 Fujitsu Limited Semiconductor device having resin gate hole through substrate for resin encapsulation
US6111306A (en) 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
EP0977127A2 (en) 1994-03-11 2000-02-02 The Panda Project Method for configuring a computer system
US5824950A (en) * 1994-03-11 1998-10-20 The Panda Project Low profile semiconductor die carrier
US5543586A (en) * 1994-03-11 1996-08-06 The Panda Project Apparatus having inner layers supporting surface-mount components
US5821457A (en) * 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
US6339191B1 (en) * 1994-03-11 2002-01-15 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier
US5541449A (en) * 1994-03-11 1996-07-30 The Panda Project Semiconductor chip carrier affording a high-density external interface
GB2288286A (en) * 1994-03-30 1995-10-11 Plessey Semiconductors Ltd Ball grid array arrangement
US5576931A (en) * 1994-05-03 1996-11-19 The Panda Project Computer with two fans and two air circulation areas
TW276356B (https=) * 1994-06-24 1996-05-21 Ibm
US5654204A (en) * 1994-07-20 1997-08-05 Anderson; James C. Die sorter
US5461260A (en) * 1994-08-01 1995-10-24 Motorola Inc. Semiconductor device interconnect layout structure for reducing premature electromigration failure due to high localized current density
US6031723A (en) * 1994-08-18 2000-02-29 Allen-Bradley Company, Llc Insulated surface mount circuit board construction
US5483099A (en) * 1994-08-31 1996-01-09 Intel Corporation Standardized power and ground design for pin grid array packages
EP0706208B1 (en) * 1994-10-03 2002-06-12 Kabushiki Kaisha Toshiba Method of manufacturing of a semiconductor package integral with semiconductor chip.
US5714801A (en) * 1995-03-31 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor package
JP3432963B2 (ja) * 1995-06-15 2003-08-04 沖電気工業株式会社 半導体集積回路
JP2716005B2 (ja) * 1995-07-04 1998-02-18 日本電気株式会社 ワイヤボンド型半導体装置
US5629241A (en) * 1995-07-07 1997-05-13 Hughes Aircraft Company Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same
US5623160A (en) * 1995-09-14 1997-04-22 Liberkowski; Janusz B. Signal-routing or interconnect substrate, structure and apparatus
MY123146A (en) * 1996-03-28 2006-05-31 Intel Corp Perimeter matrix ball grid array circuit package with a populated center
US5895977A (en) 1996-08-08 1999-04-20 Intel Corporation Bond pad functional layout on die to improve package manufacturability and assembly
US5990545A (en) * 1996-12-02 1999-11-23 3M Innovative Properties Company Chip scale ball grid array for integrated circuit package
US5866949A (en) * 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
KR100237328B1 (ko) * 1997-02-26 2000-01-15 김규현 반도체 패키지의 구조 및 제조방법
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
US7336468B2 (en) 1997-04-08 2008-02-26 X2Y Attenuators, Llc Arrangement for energy conditioning
US7321485B2 (en) 1997-04-08 2008-01-22 X2Y Attenuators, Llc Arrangement for energy conditioning
JPH10303562A (ja) * 1997-04-30 1998-11-13 Toshiba Corp プリント配線板
US6100853A (en) * 1997-09-10 2000-08-08 Hughes Electronics Corporation Receiver/transmitter system including a planar waveguide-to-stripline adapter
US6028354A (en) 1997-10-14 2000-02-22 Amkor Technology, Inc. Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package
US6133628A (en) * 1997-12-18 2000-10-17 Advanced Micro Devices, Inc. Metal layer interconnects with improved performance characteristics
US6169664B1 (en) * 1998-01-05 2001-01-02 Texas Instruments Incorporated Selective performance enhancements for interconnect conducting paths
JP3610221B2 (ja) * 1998-01-27 2005-01-12 キヤノン株式会社 多層プリント配線基板
US6078102A (en) * 1998-03-03 2000-06-20 Silicon Bandwidth, Inc. Semiconductor die package for mounting in horizontal and upright configurations
US6141869A (en) 1998-10-26 2000-11-07 Silicon Bandwidth, Inc. Apparatus for and method of manufacturing a semiconductor die carrier
US6664620B2 (en) 1999-06-29 2003-12-16 Intel Corporation Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
GB2377080B (en) 2001-09-11 2003-05-07 Sendo Int Ltd Integrated circuit package and printed circuit board arrangement
EP1376698A1 (en) * 2002-06-25 2004-01-02 STMicroelectronics S.r.l. Electrically erasable and programable non-volatile memory cell
JP4206885B2 (ja) * 2003-09-26 2009-01-14 ソニー株式会社 半導体装置の製造方法
JP2008537843A (ja) 2005-03-01 2008-09-25 エックストゥーワイ アテニュエイターズ，エルエルシー 内部で重なり合った調整器
US8057240B2 (en) * 2010-03-23 2011-11-15 Tyco Electronics Corporation Circuit board for an electrical connector assembly

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161843A (ja) * 1983-03-07 1984-09-12 Hitachi Ltd 半導体装置
US4705917A (en) * 1985-08-27 1987-11-10 Hughes Aircraft Company Microelectronic package
JPS62216240A (ja) * 1986-03-17 1987-09-22 Nec Ic Microcomput Syst Ltd 集積回路パツケ−ジ
JPH0777247B2 (ja) * 1986-09-17 1995-08-16 富士通株式会社 半導体装置の製造方法
JPH088321B2 (ja) * 1987-01-19 1996-01-29 住友電気工業株式会社 集積回路パツケ−ジ
US5066831A (en) * 1987-10-23 1991-11-19 Honeywell Inc. Universal semiconductor chip package
US4972253A (en) * 1988-06-27 1990-11-20 Digital Equipment Corporation Programmable ceramic high performance custom package
US4943845A (en) * 1988-08-02 1990-07-24 Northern Telecom Limited Thick film packages with common wafer aperture placement
JPH02239649A (ja) * 1989-03-14 1990-09-21 Fujitsu Ltd ピン・グリッド・アレイディバイスとその搭載用基板
JPH02267947A (ja) * 1989-04-07 1990-11-01 Mitsubishi Electric Corp 半導体装置
US4949453A (en) * 1989-06-15 1990-08-21 Cray Research, Inc. Method of making a chip carrier with terminating resistive elements
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package

Also Published As

Publication number Publication date
EP0517247B1 (en) 2001-08-22
DE69232012D1 (de) 2001-09-27
EP0517247A2 (en) 1992-12-09
EP0517247A3 (https=) 1994-02-16
US5309024A (en) 1994-05-03
DE69232012T2 (de) 2002-03-14

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