JPH0496354A - 半導体集積回路チップとこれの実装方法 - Google Patents

半導体集積回路チップとこれの実装方法

Info

Publication number
JPH0496354A
JPH0496354A JP21390190A JP21390190A JPH0496354A JP H0496354 A JPH0496354 A JP H0496354A JP 21390190 A JP21390190 A JP 21390190A JP 21390190 A JP21390190 A JP 21390190A JP H0496354 A JPH0496354 A JP H0496354A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
circuit chip
power supply
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21390190A
Other languages
English (en)
Inventor
Hiroshi Nishida
宏 西田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21390190A priority Critical patent/JPH0496354A/ja
Publication of JPH0496354A publication Critical patent/JPH0496354A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路チップとこれの実装方法に関し
、特に電源供給もしくは接地方法を改善した半導体集積
回路チップとこれの実装方法に関する。
〔従来の技術〕
従来の半導体集積回路チップとこれの実装方法は、第４
図の側面図に示すように、半導体集積回路チップ３０上
に金属膜で電源パッド３１および地気パッド３２を設け
、ボンディング線３３を介して電源供給及び接地を行っ
ている。
〔発明が解決しようとする課題〕
この従来の半導体集積回路チップに対する電源供給及び
接地には、半導体集積回路チップ上に電源パッドおよび
地気バッドを設けているため、入出力信号パッドを多数
必要とする場合、全パッド数に制限があり、電源パッド
又は地気バッド数を余儀なく制限せざるをえない場合が
ある。この結果電源ライン又は地気ラインが弱くなり、
ノイズに対して誤動作しやすくなるという問題点があっ
た。
〔課題を解決するための手段〕
本発明の半導体集積回路チップは、電源！（又は地気線
）を上面の周辺部に有する半導体集積回路チップにおい
て、前記電源線（又は地気線）と前記半導体集積回路チ
ップの側面部とを導体の薄膜から成る導電膜によって覆
う構成である。
本発明の半導体集積回路チップの実装方法は、側面部を
導体の薄膜から成る導電膜で覆った半導体集積回路チッ
プを絶縁体の表面に設けた導体上に載せ電気的に接続す
る構成である。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図は本発明の一実施例の半導体集積回路チップの断
面斜視図である。
半導体集積回路チップ１上面の周辺部には、電源線又は
地気線３を設けて有る。この半導体集積回路チップ１の
側面４と周辺部に設けた電源線又は地気線３とを、金あ
るいはアルミニウム等の導体薄膜から成る導電膜５で覆
う０図では、導電膜５で側面４と電源線又はＧＮＤ線の
一部を覆っているが、もちろん全面を覆っていてもかま
わない。
第２図は半導体集積回路チップを半導体パッケージに搭
載した一実施例の側面図である。
導電膜７が印刷された半導体パッケージの素子取付板８
上に導電性のマウント材６を用いて、第１図で説明した
半導体集積回路チップ１を固定させる。このときの接触
面積は非常に大きいのでこれによって半導体集積回路チ
ップ１にボンディング線を介さないでパッケージ端子９
がらの電源の供給又は接地が低抵抗でできることになる
にこで、ボンディング線を介して電源の供給線は接地を
をすればさらに電源又は接地ラインが強化されノイズに
対して一層強くなる。
第３図は半導体集積回路チップをプリント基板に搭載し
た他の実施例の側面図である。
この場合は絶縁体の上に電源又は地気の回路バタン１０
を印刷したプリント基板１１上に、導電性マウント材１
２を用いて半導体集積回路チップ１を固定し、電源の供
給又は接地を、電源又は地気の回路パターン１０を介し
て行っている。
〔発明の効果〕
以上説明したように本発明は、電源線又は地気を上面の
周辺部に有する半導体集積回路チップ３において電源線
又は地気線と半導体集積回路チップの側面部とを導電膜
で覆うことにより、電源パッド又は地気パッドを介して
電源の供給又は接地をする必要がなくなり、入出力信号
パッド数の制限の緩和ができる。またボンディング線を
介さないで直接、電源の供給又は接地を低抵抗で行える
ので、ノイズに対して強く誤動作しにくくなるという効
果がある。
は地気パッド、３・・・電源線又は地気線、４・・・側
面、５．７・・・導電膜、６．１２・・・導電性マウン
ト材、８・・・素子取付板、９・・・パッケージ端子、
１０・・・電源又は地気の回路パターン、１１・・・プ
リント基板。

Claims (1)

  1. 【特許請求の範囲】 １、電源線（又は地気線）を上面の周辺部に有する半導
    体集積回路チップにおいて、前記電源線（又は地気線）
    と前記半導体集積回路チップの側面部とを導体の薄膜か
    ら成る導電膜によって覆うことを特徴とする半導体集積
    回路チップ。 ２、側面部を導体の薄膜から成る導電膜で覆った半導体
    集積回路チップを絶縁体の表面に設けた導体上に載せ電
    気的に接続することを特徴とする半導体集積回路チップ
    実装方法。
JP21390190A 1990-08-13 1990-08-13 半導体集積回路チップとこれの実装方法 Pending JPH0496354A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21390190A JPH0496354A (ja) 1990-08-13 1990-08-13 半導体集積回路チップとこれの実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21390190A JPH0496354A (ja) 1990-08-13 1990-08-13 半導体集積回路チップとこれの実装方法

Publications (1)

Publication Number Publication Date
JPH0496354A true JPH0496354A (ja) 1992-03-27

Family

ID=16646899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21390190A Pending JPH0496354A (ja) 1990-08-13 1990-08-13 半導体集積回路チップとこれの実装方法

Country Status (1)

Country Link
JP (1) JPH0496354A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173214A (ja) * 2004-12-14 2006-06-29 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173214A (ja) * 2004-12-14 2006-06-29 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP4619104B2 (ja) * 2004-12-14 2011-01-26 パナソニック株式会社 半導体装置

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