JPH0482881U - - Google Patents
Info
- Publication number
- JPH0482881U JPH0482881U JP1990126183U JP12618390U JPH0482881U JP H0482881 U JPH0482881 U JP H0482881U JP 1990126183 U JP1990126183 U JP 1990126183U JP 12618390 U JP12618390 U JP 12618390U JP H0482881 U JPH0482881 U JP H0482881U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- forming
- forming surface
- insulating film
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011229 interlayer Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims 3
- 239000010410 layer Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
Description
第１図はこの考案の実施例の要部構成を概略的
に示す断面図、第２図は実施例装置及び従来装置
におけるインピーダンスの変化の様子の説明に供
する図、第３図は従来の配線装置の要部構成を概
略的に示す断面図である。
３４……下地、３６，３８……回路形成面、４
０……層間絶縁膜、４２……バイアホール、４４
……層間配線、４６，４８，５０，５２……回路
構成部品。
Fig. 1 is a cross-sectional view schematically showing the main structure of an embodiment of this invention, Fig. 2 is a diagram illustrating how impedance changes in the embodiment device and the conventional device, and Fig. 3 is a diagram showing conventional wiring. FIG. 2 is a cross-sectional view schematically showing the configuration of main parts of the device. 34... Base, 36, 38... Circuit forming surface, 4
0... Interlayer insulating film, 42... Via hole, 44
...Interlayer wiring, 46, 48, 50, 52...Circuit component.
Claims (1)
、隣接する回路形成面の間に設けた層間絶縁膜と
、一方の回路形成面から当該回路形成面とは異な
る層の他方の回路形成面まで層間絶縁膜に形成し
たバイアホールと、該バイアホールに設けられ前
記一方の回路形成面の回路構成部品及び他方の回
路形成面の回路構成部品の間を電気的に接続する
層間配線とを備えて成る配線装置において、 前記バイアホールを一方及び他方の回路形成面
の双方に対して斜めに設けることを特徴とする配
線装置。[Claims for Utility Model Registration] A base, a circuit-forming surface provided in multiple layers on the base, an interlayer insulating film provided between adjacent circuit-forming surfaces, and a circuit-forming surface from one circuit-forming surface to the circuit-forming surface. A via hole is formed in the interlayer insulating film up to the other circuit formation surface of a different layer, and an electrical connection between the circuit component on the one circuit formation surface and the circuit component on the other circuit formation surface provided in the via hole is provided. What is claimed is: 1. A wiring device comprising: an interlayer wiring that connects the via holes diagonally with respect to both one and the other circuit forming surfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990126183U JPH0482881U (en) | 1990-11-28 | 1990-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990126183U JPH0482881U (en) | 1990-11-28 | 1990-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0482881U true JPH0482881U (en) | 1992-07-20 |
Family
ID=31873749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990126183U Pending JPH0482881U (en) | 1990-11-28 | 1990-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0482881U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003008224A (en) * | 2001-06-25 | 2003-01-10 | Kyocera Corp | Multilayer substrate |
-
1990
- 1990-11-28 JP JP1990126183U patent/JPH0482881U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003008224A (en) * | 2001-06-25 | 2003-01-10 | Kyocera Corp | Multilayer substrate |