JPH0446548U - - Google Patents
Info
- Publication number
- JPH0446548U JPH0446548U JP8821290U JP8821290U JPH0446548U JP H0446548 U JPH0446548 U JP H0446548U JP 8821290 U JP8821290 U JP 8821290U JP 8821290 U JP8821290 U JP 8821290U JP H0446548 U JPH0446548 U JP H0446548U
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- interlayer insulating
- insulating film
- hole portion
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は一実施例を示す断面図、第２図は同実
施例の製造方法を示す工程断面図、第３図は従来
の多層配線を示す断面図、第４図及び第５図はそ
れぞれ従来の改善されたスルーホール部分を示す
断面図である。
２……下地、４……下層メタル配線、６……段
差、８……メタルパターン、１０……層間絶縁膜
、１２……スルーホール、１４……上層メタル配
線。
Fig. 1 is a sectional view showing one embodiment, Fig. 2 is a process sectional view showing the manufacturing method of the same embodiment, Fig. 3 is a sectional view showing a conventional multilayer wiring, and Figs. 4 and 5 are respectively FIG. 2 is a sectional view showing a conventional improved through-hole portion. 2... Base layer, 4... Lower layer metal wiring, 6... Step, 8... Metal pattern, 10... Interlayer insulating film, 12... Through hole, 14... Upper layer metal wiring.
Claims (1)
配線と上層メタル配線が接続している多層配線に
おいて、前記下層メタル配線にはスルーホール部
分が盛り上がるように段差が設けられており、か
つ前記層間絶縁膜は平坦化処理がなされてスルー
ホール部分の膜厚が薄くなつていることを特徴と
する半導体装置の多層配線。 In a multilayer wiring in which a lower metal wiring and an upper metal wiring are connected via a through hole in an interlayer insulating film, the lower metal wiring is provided with a step so that the through hole portion is raised, and the interlayer insulating film is a multilayer wiring for a semiconductor device, which is characterized by a planarization process that reduces the thickness of the film in the through-hole portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8821290U JPH0446548U (en) | 1990-08-22 | 1990-08-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8821290U JPH0446548U (en) | 1990-08-22 | 1990-08-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0446548U true JPH0446548U (en) | 1992-04-21 |
Family
ID=31821246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8821290U Pending JPH0446548U (en) | 1990-08-22 | 1990-08-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0446548U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011507253A (en) * | 2007-12-17 | 2011-03-03 | コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ | Method for making an electrical interconnection between two conductive layers |
-
1990
- 1990-08-22 JP JP8821290U patent/JPH0446548U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011507253A (en) * | 2007-12-17 | 2011-03-03 | コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ | Method for making an electrical interconnection between two conductive layers |