JPH0183366U - - Google Patents
Info
- Publication number
- JPH0183366U JPH0183366U JP1987178129U JP17812987U JPH0183366U JP H0183366 U JPH0183366 U JP H0183366U JP 1987178129 U JP1987178129 U JP 1987178129U JP 17812987 U JP17812987 U JP 17812987U JP H0183366 U JPH0183366 U JP H0183366U
- Authority
- JP
- Japan
- Prior art keywords
- conductor patterns
- substrate material
- diagram showing
- wiring board
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 2
Description
第１図は本考案実施例の断面構造を示す図、第
２図は本考案実施例の製造前の状態を示す図、第
３図は本考案実施例の基板の平面構造を示す図、
第４図は従来例の断面構造を示す図、第５図は従
来例の製造前の状態を示す図、第６図は従来例の
基板材料の平面構造を示す図、第７図は従来例の
多層配線基板に回路素子を実装するときの状態を
説明する図である。
１……基板材料、１ａ……表面、１ｂ……裏面
、２……導体、３，４，５……基板材料、６……
導体。
FIG. 1 is a diagram showing the cross-sectional structure of the embodiment of the present invention, FIG. 2 is a diagram showing the state of the embodiment of the present invention before manufacturing, and FIG. 3 is a diagram showing the planar structure of the substrate of the embodiment of the present invention.
Figure 4 is a diagram showing the cross-sectional structure of the conventional example, Figure 5 is a diagram showing the state before manufacturing of the conventional example, Figure 6 is a diagram showing the planar structure of the substrate material of the conventional example, and Figure 7 is the conventional example. FIG. 3 is a diagram illustrating a state when circuit elements are mounted on the multilayer wiring board of FIG. 1...Substrate material, 1a...Front surface, 1b...Back surface, 2...Conductor, 3, 4, 5...Substrate material, 6...
conductor.
Claims (1)
において、片面がスルーホール及び導体パターン
を有しない基板材料により形成されてなる多層配
線基板。 A multilayer wiring board in which conductor patterns are formed in multiple layers, one side of which is formed of a substrate material that does not have through holes or conductor patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178129U JPH0183366U (en) | 1987-11-20 | 1987-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178129U JPH0183366U (en) | 1987-11-20 | 1987-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0183366U true JPH0183366U (en) | 1989-06-02 |
Family
ID=31469761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987178129U Pending JPH0183366U (en) | 1987-11-20 | 1987-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0183366U (en) |
-
1987
- 1987-11-20 JP JP1987178129U patent/JPH0183366U/ja active Pending