JPH0233438U - - Google Patents

Info

Publication number
JPH0233438U
JPH0233438U JP10998388U JP10998388U JPH0233438U JP H0233438 U JPH0233438 U JP H0233438U JP 10998388 U JP10998388 U JP 10998388U JP 10998388 U JP10998388 U JP 10998388U JP H0233438 U JPH0233438 U JP H0233438U
Authority
JP
Japan
Prior art keywords
conductor pattern
multilayer wiring
wiring structure
wiring conductor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10998388U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10998388U priority Critical patent/JPH0233438U/ja
Publication of JPH0233438U publication Critical patent/JPH0233438U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは本考案の一実施例を示す断面図
、平面図、第2図、第3図は本考案の他の実施例
を示す断面図、第4図a,bは従来の膜集積回路
における多層配線構造の一例を示す断面図、平面
図である。 1……セラミツク基板、11……凹み、2,4
,6……導体パターン、3,5……絶縁層。なお
図中同一符号は同一または相当する部分を示す。
Figures 1a and b are cross-sectional views and plan views showing one embodiment of the present invention, Figures 2 and 3 are cross-sectional views showing other embodiments of the present invention, and Figures 4a and b are sectional views of conventional FIG. 1 is a cross-sectional view and a plan view showing an example of a multilayer wiring structure in a film integrated circuit. 1... Ceramic substrate, 11... Recess, 2, 4
, 6... conductor pattern, 3, 5... insulating layer. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 多層配線構造の膜集積回路において、多層配線
構造部分の最下部の配線導体パターンと該配線導
体パターン上の絶縁層部分を基板に設けた凹み内
に納めたことを特徴とする膜集積回路。
A film integrated circuit having a multilayer wiring structure, characterized in that a lowermost wiring conductor pattern of a multilayer wiring structure part and an insulating layer part on the wiring conductor pattern are housed in a recess provided in a substrate.
JP10998388U 1988-08-24 1988-08-24 Pending JPH0233438U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10998388U JPH0233438U (en) 1988-08-24 1988-08-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10998388U JPH0233438U (en) 1988-08-24 1988-08-24

Publications (1)

Publication Number Publication Date
JPH0233438U true JPH0233438U (en) 1990-03-02

Family

ID=31346727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10998388U Pending JPH0233438U (en) 1988-08-24 1988-08-24

Country Status (1)

Country Link
JP (1) JPH0233438U (en)

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