JPH0397975U - - Google Patents
Info
- Publication number
- JPH0397975U JPH0397975U JP592090U JP592090U JPH0397975U JP H0397975 U JPH0397975 U JP H0397975U JP 592090 U JP592090 U JP 592090U JP 592090 U JP592090 U JP 592090U JP H0397975 U JPH0397975 U JP H0397975U
- Authority
- JP
- Japan
- Prior art keywords
- wirings
- insulating layer
- land
- layers
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Alarm Systems (AREA)
Description
第１図はこの考案の実施例の一部を示す断面図
、第２図はその第１配線１２上から見た平面図、
第３図は従来の多層配線基板の一部を示す断面図
、第４図はその第１配線１２上から見た平面図で
ある。
FIG. 1 is a sectional view showing a part of an embodiment of this invention, FIG. 2 is a plan view seen from above the first wiring 12,
FIG. 3 is a sectional view showing a part of a conventional multilayer wiring board, and FIG. 4 is a plan view of the first wiring 12 viewed from above.
Claims (1)
２配線が形成され、これら第１、第２配線がスル
ーホールで互いに接続され、そのスルーホール部
分で、上記第１、第２配線にそれぞれ第１、第２
ランドが形成され、上記第１絶縁層の両側に第２
、第３絶縁層がそれぞれ形成されて上記第１絶縁
層と上記第２、第３絶縁層とにより上記第１、第
２配線がそれぞれ挟まれ、上記第２、第３絶縁層
の上記第１絶縁層と各反対の面に第１、第２グラ
ンド・電源層がそれぞれ形成された多層配線基板
において、 上記第１、第２グランド・電源層の上記第１、
第２ランドと対向する部分に第１、第２の孔がそ
れぞれ形成されて、上記第１、第２ランド部分の
インピーダンスが、それぞれ上記第１、第２配線
のインピーダンスとほぼ等しくされていることを
特徴とする多層配線基板。[Claims for Utility Model Registration] First and second wirings are formed on one side and the other side of the first insulating layer, respectively, and these first and second wirings are connected to each other through a through hole, and the through hole portion , the first and second wirings are connected to the first and second wirings, respectively.
A land is formed, and a second land is formed on both sides of the first insulating layer.
, a third insulating layer is formed, and the first and second wirings are sandwiched between the first insulating layer and the second and third insulating layers, respectively, and the first and second wirings are sandwiched between the first insulating layer and the second and third insulating layers, respectively. In a multilayer wiring board in which first and second ground/power layers are respectively formed on opposite sides of the insulating layer, the first and second ground/power layers of the first and second ground/power layers are provided.
First and second holes are formed in portions facing the second land, respectively, so that the impedance of the first and second land portions is approximately equal to the impedance of the first and second wiring, respectively. A multilayer wiring board featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP592090U JPH0397975U (en) | 1990-01-24 | 1990-01-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP592090U JPH0397975U (en) | 1990-01-24 | 1990-01-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0397975U true JPH0397975U (en) | 1991-10-09 |
Family
ID=31509607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP592090U Pending JPH0397975U (en) | 1990-01-24 | 1990-01-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0397975U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0946015A (en) * | 1995-07-28 | 1997-02-14 | Hewlett Packard Co <Hp> | Printed circuit board |
| JP2005244010A (en) * | 2004-02-27 | 2005-09-08 | Toppan Printing Co Ltd | Packaging structure of circuit board |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5392470A (en) * | 1977-01-24 | 1978-08-14 | Hitachi Ltd | Method of producing printed circuit board |
| JPS5878498A (en) * | 1981-11-04 | 1983-05-12 | 日本電気株式会社 | Multilayer printed circuit board |
| JPS61290794A (en) * | 1985-06-19 | 1986-12-20 | 株式会社日立製作所 | Wiring board |
| JPS6214806B2 (en) * | 1978-12-01 | 1987-04-03 | Sony Corp |
-
1990
- 1990-01-24 JP JP592090U patent/JPH0397975U/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5392470A (en) * | 1977-01-24 | 1978-08-14 | Hitachi Ltd | Method of producing printed circuit board |
| JPS6214806B2 (en) * | 1978-12-01 | 1987-04-03 | Sony Corp | |
| JPS5878498A (en) * | 1981-11-04 | 1983-05-12 | 日本電気株式会社 | Multilayer printed circuit board |
| JPS61290794A (en) * | 1985-06-19 | 1986-12-20 | 株式会社日立製作所 | Wiring board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0946015A (en) * | 1995-07-28 | 1997-02-14 | Hewlett Packard Co <Hp> | Printed circuit board |
| JP2005244010A (en) * | 2004-02-27 | 2005-09-08 | Toppan Printing Co Ltd | Packaging structure of circuit board |
| JP4543699B2 (en) * | 2004-02-27 | 2010-09-15 | 凸版印刷株式会社 | Circuit board mounting structure |