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Priority to JP3631988UpriorityCriticalpatent/JPH0449723Y2/ja
Publication of JPH01142061UpublicationCriticalpatent/JPH01142061U/ja
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Publication of JPH0449723Y2publicationCriticalpatent/JPH0449723Y2/ja
Computer system having direct bus attachment between processor and dynamic main memory, and having in-processor DMA control with respect to a plurality of data exchange means also connected to said bus, and central processor for use in such computer system
System for checking the acceptance of I/O request to an interface using software visible instruction which provides a status signal and performs operations in response thereto