JPH0449196B2 - - Google Patents

Info

Publication number
JPH0449196B2
JPH0449196B2 JP56149466A JP14946681A JPH0449196B2 JP H0449196 B2 JPH0449196 B2 JP H0449196B2 JP 56149466 A JP56149466 A JP 56149466A JP 14946681 A JP14946681 A JP 14946681A JP H0449196 B2 JPH0449196 B2 JP H0449196B2
Authority
JP
Japan
Prior art keywords
signal
circuit
control signal
external terminal
data line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56149466A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5853082A (ja
Inventor
Noburo Tanimura
Hiroshi Fukuda
Kyobumi Uchibori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Microcomputer System Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Microcomputer System Ltd, Hitachi Ltd filed Critical Hitachi Microcomputer System Ltd
Priority to JP56149466A priority Critical patent/JPS5853082A/ja
Publication of JPS5853082A publication Critical patent/JPS5853082A/ja
Publication of JPH0449196B2 publication Critical patent/JPH0449196B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals

Landscapes

  • Static Random-Access Memory (AREA)
JP56149466A 1981-09-24 1981-09-24 スタテイツク型ｒａｍ Granted JPS5853082A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56149466A JPS5853082A (ja) 1981-09-24 1981-09-24 スタテイツク型ｒａｍ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56149466A JPS5853082A (ja) 1981-09-24 1981-09-24 スタテイツク型ｒａｍ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2126726A Division JPH03201296A (ja) 1990-05-18 1990-05-18 Ｒａｍの制御方式

Publications (2)

Publication Number Publication Date
JPS5853082A JPS5853082A (ja) 1983-03-29
JPH0449196B2 true JPH0449196B2 (enrdf_load_html_response) 1992-08-10

Family

ID=15475747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56149466A Granted JPS5853082A (ja) 1981-09-24 1981-09-24 スタテイツク型ｒａｍ

Country Status (1)

Country Link
JP (1) JPS5853082A (enrdf_load_html_response)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110090A (ja) * 1982-12-14 1984-06-25 Nec Corp メモリ回路
JPH0641648B2 (ja) * 1984-02-29 1994-06-01 帝人株式会社 潜在嵩高性マルチフイラメントの製造法及びその紡糸口金
JPH0831275B2 (ja) * 1986-09-09 1996-03-27 日本電気株式会社 メモリ回路
JPH03201296A (ja) * 1990-05-18 1991-09-03 Hitachi Ltd Ｒａｍの制御方式
US5511024A (en) * 1993-06-02 1996-04-23 Rambus, Inc. Dynamic random access memory system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5931154B2 (ja) * 1977-03-15 1984-07-31 富士通株式会社 半導体記憶装置
JPS542029A (en) * 1977-06-07 1979-01-09 Fujitsu Ltd Ic memory having address data common terminal
JPS54128226A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Random access memory

Also Published As

Publication number Publication date
JPS5853082A (ja) 1983-03-29

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