JPH0441502B2 - - Google Patents

Info

Publication number
JPH0441502B2
JPH0441502B2 JP58146325A JP14632583A JPH0441502B2 JP H0441502 B2 JPH0441502 B2 JP H0441502B2 JP 58146325 A JP58146325 A JP 58146325A JP 14632583 A JP14632583 A JP 14632583A JP H0441502 B2 JPH0441502 B2 JP H0441502B2
Authority
JP
Japan
Prior art keywords
region
forming
emitter
layer
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58146325A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6038856A (ja
Inventor
Masanori Odaka
Katsumi Ogiue
Takahide Ikeda
Shuichi Myaoka
Nobuo Tanba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58146325A priority Critical patent/JPS6038856A/ja
Publication of JPS6038856A publication Critical patent/JPS6038856A/ja
Publication of JPH0441502B2 publication Critical patent/JPH0441502B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP58146325A 1983-08-12 1983-08-12 半導体装置及びその製造方法 Granted JPS6038856A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58146325A JPS6038856A (ja) 1983-08-12 1983-08-12 半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58146325A JPS6038856A (ja) 1983-08-12 1983-08-12 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JPS6038856A JPS6038856A (ja) 1985-02-28
JPH0441502B2 true JPH0441502B2 (fr) 1992-07-08

Family

ID=15405117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58146325A Granted JPS6038856A (ja) 1983-08-12 1983-08-12 半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JPS6038856A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6337642A (ja) * 1986-07-31 1988-02-18 Mitsubishi Electric Corp 半導体集積回路装置
JPH0734453B2 (ja) * 1986-09-12 1995-04-12 三菱電機株式会社 半導体集積回路装置の製造方法
JPS63131563A (ja) * 1986-11-20 1988-06-03 Mitsubishi Electric Corp 半導体集積回路装置
JPS63164458A (ja) * 1986-12-26 1988-07-07 Fujitsu Ltd Bi−CMOS素子の製造方法
JPS63205966A (ja) * 1987-02-23 1988-08-25 Matsushita Electronics Corp 半導体集積回路の製造方法
US6875648B1 (en) * 2004-07-09 2005-04-05 Atmel Corporation Fabrication of an EEPROM cell with emitter-polysilicon source/drain regions

Also Published As

Publication number Publication date
JPS6038856A (ja) 1985-02-28

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