JPH04107832U - 半導体装置 - Google Patents

半導体装置

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Publication number
JPH04107832U
JPH04107832U JP1991009777U JP977791U JPH04107832U JP H04107832 U JPH04107832 U JP H04107832U JP 1991009777 U JP1991009777 U JP 1991009777U JP 977791 U JP977791 U JP 977791U JP H04107832 U JPH04107832 U JP H04107832U
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Japan
Prior art keywords
external connection
lead
semiconductor chip
connection lead
island
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Granted
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JP1991009777U
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JP2513044Y2 (ja
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守 安藤
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三洋電機株式会社
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 （修正有） 【目的】外形寸法を小さくできる表面実装型のミニモー
ルドパッケージを提供する。 【構成】接続パッド（１５）と外部接続リード（１６）
とを異方性導電接着剤（１７）にて固着することによ
り、外形寸法を一層小型化した。

Description

【考案の詳細な説明】
【０００１】
【産業上の利用分野】
本考案は外形寸法を小さくできる表面実装型の半導体装置に関する。
【０００２】
【従来の技術】
従来より軽薄短小化を実現する１つの手段として、プリント基板の導電パター ン上にリードを対向接着する所謂ＣＰ、ＭＣＰと称される表面実装型のミニモー ルドパッケージがある（例えば、特開平０２−１８４０５９号）。 図５にその例を示す。同図において、（１）は半導体チップ、（２）はチップ （１）を搭載するアイランド、（３）はチップ（１）上の電極パッドにワイヤ（ ４）で接続された外部接続リード、（５）は主要部を封止する樹脂である。
【０００３】 上記ミニモールドパッケージは、微細化が押し進められた結果、外形寸法が１ ．６×０．８mm程度まで小型化されている。
【０００４】
【考案が解決しようとする課題】
しかしながら、従来の半導体装置はワイヤ（４）の位置精度を保つため、リー ドフレームの打ち抜き加工に要する抜きしろ寸法（ａ）、ワイヤ（４）のセカン ドボンドエリアに要する外部接続リード（３）の寸法（ｂ）、ワイヤ（４）のル ープ高さに要する寸法（ｃ）、およびワイヤ（４）ループ高さからの樹脂（５） の余裕に要する寸法（ｄ）が必要になる。そのため外形寸法の更なる縮小が困難 である欠点があった。
【０００５】
【課題を解決するための手段】
本考案は上記従来の欠点に鑑み成されたもので、半導体チップ（１１）を搭載 するアイランド（１２）と、アイランド（１２）に一体化した外部接続リード（ １４）と、チップ（１１）の表面に形成した電極パッド（１５）と、電極パッド （１５）に異方性導電接着剤（１７）にて対向接着された外部接続リード（１６ ）と、主要部を封止する樹脂（１８）とを具備することにより、外形寸法を縮小 できるミニモールド型の半導体装置を提供するものである。
【０００６】
【作用】
本考案によれば、ワイヤ（４）を使用せず外部接続リード（１６）を電極パッ ド（１５）に直付けするので、ワイヤボンドに要する寸法を無くすことができる 。そのため、樹脂（１８）の外形寸法を縮小できる。
【０００７】
【実施例】
以下に本考案の一実施例を図面を参照しながら詳細に説明する。 図１と図２は夫々本考案の半導体装置を示す断面図と平面図である。同図にお いて、（１１）は表面に通常のプレーナ技術によってトランジスタ等の回路素子 を形成した半導体チップ、（１２）は半導体チップ（１１）を共晶半田（１３） 等で固着するアイランド、（１４）はアイランド（１２）と一体化されて外部に 延在し、前記トランジスタのコレクタ取出しとなる外部接続リード、（１５）は 半導体チップ（１１）の表面にＡｌのホトエッチで形成された電極取出し用の接 続パッド、（１６）は接続パッド（１５）に対向接着されて外部に延在し、前記 トランジスタのベースおよびエミッタの取出しとなる外部接続リード、（１７） は接続パッド（１５）と外部接続リード（１６）とを電気的機械的に接続するた めの異方性導電接着剤、（１８）は主要部を封止するエポキシ系熱硬化性樹脂で ある。
【０００８】 アイランド（１２）と外部接続リード（１４）（１６）とは、肉厚０．１〜０ ．３mmの銅系板状素材から打ち抜き加工したリードフレームにより形成され、そ の表面にはＡｇ、Ｎｉ等の金属メッキが処される。アイランド（１２）上への半 導体チップ（１１）の固着は、Ａｕ−Ｓｉ共晶等で行われている。 異方性導電接着剤（１７）は、母材としての絶縁材である厚さ０．３mmのシリ コーンゴムに導電繊維を縦に配向して埋め込んだものか、又は厚さ２０〜３０μ ｍの絶縁性接着剤中に直径７μｍ、長さ５０〜１００μｍのカーボン繊維を並列 配列したものである。カーボン繊維の代わりにハンダ粒子やＮｉ粒子等の導電粒 子を用いたものもある。両者共、接続パッド（１５）と外部接続リード（１６） との間に挟み込み、加圧又は加圧加熱することにより、接続パッド（１５）と外 部接続リード（１６）との電気的機械的な接続を果たす 外部接続リード（１６）の接着部付近には、リードフレームのコイニング加工 によって段差（１９）が付けられている。この段差（１９）は、異方性導電接着 剤（１７）が流出するのを防止する役割を果たす段差（１９）以降はやや上方に 折り曲げられ、樹脂（１８）外部に露出してから表面実装用にリードフォーミン グされる。尚、アイランド（１２）に一体化した外部接続リード（１４）も同様 にリードフォーミングされる。
【０００９】 上記半導体装置は、図３に示すリードフレームＡ（２０）と、図４に示すリー ドフレームＢ（２１）とに分離されたリードフレームで製造される。先ずアイラ ンド（１２）を形成したリードフレームＡ（２０）に半導体チップ（１１）をダ イボンドし、外部接続リード（１６）を形成したリードフレームＢ（２１）の接 続部にあらかじめ異方性導電接着剤（１７）を塗布し、そしてリードフレームＡ （２０）とリードフレームＢ（２１）とを重ね合わせるようにして接続パッド（ １５）と外部接続リード（１６）を接続し、樹脂モールド、リードフォーミング という工程で完成する。
【００１０】 斯る本願の半導体装置は、従来のＡｕワイヤを使用しないので、セカンドボン ドエリアに要する寸法ｂとループ高さに要する寸法ｃが不要となる。さらに、リ ードフレームを２体に分離するので、抜きしろａも不要となる。従って従来の半 導体装置に比べて大幅に小型化できる。
【００１１】
【考案の効果】
このように、本発明によれば、ワイヤを用いたことによる寸法の制限が無いの で、従来の半導体装置より一層小型化を押し進めることができる利点を有する。 さらに、外部接続リード（１６）に段差（１９）を設けておけば、接着剤（１７ ）の流出による短絡事故を未然に防止できる利点をも有する。さらに、Ａｕバン プ技術と比較して、チップ（１１）の設計変更が不要であり、且つ製造が容易で ある利点をも有する。
【図面の簡単な説明】
【図１】本考案を説明するための断面図である。
【図２】本考案を説明するための断面図である。
【図３】リードフレームＡ（２０）を示す平面図であ
る。
【図４】リードフレームＢ（２１）を示す平面図であ
る。
【図５】従来例を説明する断面図である。

Claims (2)

    【実用新案登録請求の範囲】
  1. 【請求項１】 回路素子を形成した半導体チップと、前
    記半導体チップを固着するアイランドと、前記アイラン
    ドに連続して延在する外部接続リードと、前記半導体チ
    ップの表面に形成した電極取出し用の電極パッドと、前
    記電極パッドに先端が異方性導電接着剤にて固着され延
    在する外部接続リードと、前記半導体チップを含む主要
    部をモールドする樹脂とを具備することを特徴とする半
    導体装置。
  2. 【請求項２】 前記外部接続リードの表面に前記異方性
    導電接着剤の流動を停止するためのコイニング加工を処
    したことを特徴とする請求項１記載の半導体装置。
JP1991009777U 1991-02-27 1991-02-27 半導体装置 Expired - Lifetime JP2513044Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991009777U JP2513044Y2 (ja) 1991-02-27 1991-02-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991009777U JP2513044Y2 (ja) 1991-02-27 1991-02-27 半導体装置

Publications (2)

Publication Number Publication Date
JPH04107832U true JPH04107832U (ja) 1992-09-17
JP2513044Y2 JP2513044Y2 (ja) 1996-10-02

Family

ID=31899996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991009777U Expired - Lifetime JP2513044Y2 (ja) 1991-02-27 1991-02-27 半導体装置

Country Status (1)

Country Link
JP (1) JP2513044Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511188A (zh) * 2018-05-15 2018-09-07 山东晶导微电子股份有限公司 一种贴片电容封装结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5271177A (en) * 1975-12-10 1977-06-14 Seiko Epson Corp Semiconductor device
JPS59128934A (ja) * 1983-01-13 1984-07-25 Diesel Kiki Co Ltd 燃料制御方法
JPS63152160A (ja) * 1986-12-17 1988-06-24 Sumitomo Electric Ind Ltd 半導体装置用リ−ドフレ−ム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5271177A (en) * 1975-12-10 1977-06-14 Seiko Epson Corp Semiconductor device
JPS59128934A (ja) * 1983-01-13 1984-07-25 Diesel Kiki Co Ltd 燃料制御方法
JPS63152160A (ja) * 1986-12-17 1988-06-24 Sumitomo Electric Ind Ltd 半導体装置用リ−ドフレ−ム

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511188A (zh) * 2018-05-15 2018-09-07 山东晶导微电子股份有限公司 一种贴片电容封装结构
CN108511188B (zh) * 2018-05-15 2024-02-27 山东晶导微电子股份有限公司 一种贴片电容封装结构

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