JPH0371768B2 - - Google Patents
Info
- Publication number
- JPH0371768B2 JPH0371768B2 JP57085937A JP8593782A JPH0371768B2 JP H0371768 B2 JPH0371768 B2 JP H0371768B2 JP 57085937 A JP57085937 A JP 57085937A JP 8593782 A JP8593782 A JP 8593782A JP H0371768 B2 JPH0371768 B2 JP H0371768B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- fet
- insulating film
- metal silicide
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H10D64/0112—
-
- H10D64/011—
-
- H10D64/0111—
-
- H10P32/1414—
-
- H10P32/171—
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/923—Diffusion through a layer
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57085937A JPS58202525A (ja) | 1982-05-21 | 1982-05-21 | 半導体装置の製造方法 |
| EP83105022A EP0098941B1 (en) | 1982-05-21 | 1983-05-20 | Method of making ohmic contacts regions and device manufactured by the method |
| US06/496,581 US4536943A (en) | 1982-05-21 | 1983-05-20 | Method of manufacturing a FET |
| DE8383105022T DE3374102D1 (en) | 1982-05-21 | 1983-05-20 | Method of making ohmic contacts regions and device manufactured by the method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57085937A JPS58202525A (ja) | 1982-05-21 | 1982-05-21 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58202525A JPS58202525A (ja) | 1983-11-25 |
| JPH0371768B2 true JPH0371768B2 (enExample) | 1991-11-14 |
Family
ID=13872669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57085937A Granted JPS58202525A (ja) | 1982-05-21 | 1982-05-21 | 半導体装置の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4536943A (enExample) |
| EP (1) | EP0098941B1 (enExample) |
| JP (1) | JPS58202525A (enExample) |
| DE (1) | DE3374102D1 (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4702000A (en) * | 1986-03-19 | 1987-10-27 | Harris Corporation | Technique for elimination of polysilicon stringers in direct moat field oxide structure |
| US4818725A (en) * | 1986-09-15 | 1989-04-04 | Harris Corp. | Technique for forming planarized gate structure |
| US4871688A (en) * | 1988-05-02 | 1989-10-03 | Micron Technology, Inc. | Sequence of etching polysilicon in semiconductor memory devices |
| US4957878A (en) * | 1988-05-02 | 1990-09-18 | Micron Technology, Inc. | Reduced mask manufacture of semiconductor memory devices |
| JP3285934B2 (ja) * | 1991-07-16 | 2002-05-27 | 株式会社東芝 | 半導体装置の製造方法 |
| KR960008558B1 (en) * | 1993-03-02 | 1996-06-28 | Samsung Electronics Co Ltd | Low resistance contact structure and manufacturing method of high integrated semiconductor device |
| US5342798A (en) * | 1993-11-23 | 1994-08-30 | Vlsi Technology, Inc. | Method for selective salicidation of source/drain regions of a transistor |
| JPH08255907A (ja) * | 1995-01-18 | 1996-10-01 | Canon Inc | 絶縁ゲート型トランジスタ及びその製造方法 |
| JP3525316B2 (ja) * | 1996-11-12 | 2004-05-10 | 株式会社半導体エネルギー研究所 | アクティブマトリクス型表示装置 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3967981A (en) * | 1971-01-14 | 1976-07-06 | Shumpei Yamazaki | Method for manufacturing a semiconductor field effort transistor |
| JPS49131585A (enExample) * | 1973-04-20 | 1974-12-17 | ||
| US4127931A (en) * | 1974-10-04 | 1978-12-05 | Nippon Electric Co., Ltd. | Semiconductor device |
| US4282647A (en) * | 1978-04-04 | 1981-08-11 | Standard Microsystems Corporation | Method of fabricating high density refractory metal gate MOS integrated circuits utilizing the gate as a selective diffusion and oxidation mask |
| JPS5561037A (en) * | 1978-10-31 | 1980-05-08 | Toshiba Corp | Preparation of semiconductor device |
| NL7900280A (nl) * | 1979-01-15 | 1980-07-17 | Philips Nv | Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan. |
| US4319395A (en) * | 1979-06-28 | 1982-03-16 | Motorola, Inc. | Method of making self-aligned device |
| US4431460A (en) * | 1982-03-08 | 1984-02-14 | International Business Machines Corporation | Method of producing shallow, narrow base bipolar transistor structures via dual implantations of selected polycrystalline layer |
-
1982
- 1982-05-21 JP JP57085937A patent/JPS58202525A/ja active Granted
-
1983
- 1983-05-20 EP EP83105022A patent/EP0098941B1/en not_active Expired
- 1983-05-20 US US06/496,581 patent/US4536943A/en not_active Expired - Lifetime
- 1983-05-20 DE DE8383105022T patent/DE3374102D1/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4536943A (en) | 1985-08-27 |
| DE3374102D1 (en) | 1987-11-19 |
| EP0098941B1 (en) | 1987-10-14 |
| EP0098941A1 (en) | 1984-01-25 |
| JPS58202525A (ja) | 1983-11-25 |
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