JPH0336302B2 - - Google Patents
Info
- Publication number
- JPH0336302B2 JPH0336302B2 JP56198934A JP19893481A JPH0336302B2 JP H0336302 B2 JPH0336302 B2 JP H0336302B2 JP 56198934 A JP56198934 A JP 56198934A JP 19893481 A JP19893481 A JP 19893481A JP H0336302 B2 JPH0336302 B2 JP H0336302B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon nitride
- silicon
- nitride film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19893481A JPS5898944A (ja) | 1981-12-08 | 1981-12-08 | 半導体装置の製造方法 |
US06/660,255 US4563227A (en) | 1981-12-08 | 1984-10-12 | Method for manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19893481A JPS5898944A (ja) | 1981-12-08 | 1981-12-08 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5898944A JPS5898944A (ja) | 1983-06-13 |
JPH0336302B2 true JPH0336302B2 (enrdf_load_stackoverflow) | 1991-05-31 |
Family
ID=16399393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19893481A Granted JPS5898944A (ja) | 1981-12-08 | 1981-12-08 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5898944A (enrdf_load_stackoverflow) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4538343A (en) * | 1984-06-15 | 1985-09-03 | Texas Instruments Incorporated | Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking |
US4561172A (en) * | 1984-06-15 | 1985-12-31 | Texas Instruments Incorporated | Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions |
US4580330A (en) * | 1984-06-15 | 1986-04-08 | Texas Instruments Incorporated | Integrated circuit isolation |
JPS6148934A (ja) * | 1984-08-16 | 1986-03-10 | Matsushita Electronics Corp | 半導体装置の製造方法 |
US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
BE1007588A3 (nl) * | 1993-09-23 | 1995-08-16 | Philips Electronics Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam met veldisolatiegebieden gevormd door met isolerend materiaal gevulde groeven. |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53120289A (en) * | 1977-03-30 | 1978-10-20 | Toshiba Corp | Manufacture of semiconductor device |
-
1981
- 1981-12-08 JP JP19893481A patent/JPS5898944A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5898944A (ja) | 1983-06-13 |
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