JPS5898944A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法Info
- Publication number
- JPS5898944A JPS5898944A JP19893481A JP19893481A JPS5898944A JP S5898944 A JPS5898944 A JP S5898944A JP 19893481 A JP19893481 A JP 19893481A JP 19893481 A JP19893481 A JP 19893481A JP S5898944 A JPS5898944 A JP S5898944A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon
- silicon nitride
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title description 5
- 230000003647 oxidation Effects 0.000 claims abstract description 28
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 48
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 42
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 40
- 238000002955 isolation Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 2
- KYARBIJYVGJZLB-UHFFFAOYSA-N 7-amino-4-hydroxy-2-naphthalenesulfonic acid Chemical compound OC1=CC(S(O)(=O)=O)=CC2=CC(N)=CC=C21 KYARBIJYVGJZLB-UHFFFAOYSA-N 0.000 claims 1
- 238000010276 construction Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- STRAHSCTRLRZNU-UHFFFAOYSA-N 4-(9h-carbazol-3-ylamino)phenol Chemical compound C1=CC(O)=CC=C1NC1=CC=C(NC=2C3=CC=CC=2)C3=C1 STRAHSCTRLRZNU-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 208000014380 ornithine aminotransferase deficiency Diseases 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19893481A JPS5898944A (ja) | 1981-12-08 | 1981-12-08 | 半導体装置の製造方法 |
| US06/660,255 US4563227A (en) | 1981-12-08 | 1984-10-12 | Method for manufacturing a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19893481A JPS5898944A (ja) | 1981-12-08 | 1981-12-08 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5898944A true JPS5898944A (ja) | 1983-06-13 |
| JPH0336302B2 JPH0336302B2 (enrdf_load_stackoverflow) | 1991-05-31 |
Family
ID=16399393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19893481A Granted JPS5898944A (ja) | 1981-12-08 | 1981-12-08 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5898944A (enrdf_load_stackoverflow) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4538343A (en) * | 1984-06-15 | 1985-09-03 | Texas Instruments Incorporated | Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking |
| US4561172A (en) * | 1984-06-15 | 1985-12-31 | Texas Instruments Incorporated | Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions |
| JPS6148934A (ja) * | 1984-08-16 | 1986-03-10 | Matsushita Electronics Corp | 半導体装置の製造方法 |
| JPS6175539A (ja) * | 1984-06-15 | 1986-04-17 | テキサス インスツルメンツ インコ−ポレイテツド | 集積回路の製造方法 |
| US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| KR100336543B1 (ko) * | 1993-09-23 | 2002-11-29 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 반도체장치제조방법 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53120289A (en) * | 1977-03-30 | 1978-10-20 | Toshiba Corp | Manufacture of semiconductor device |
-
1981
- 1981-12-08 JP JP19893481A patent/JPS5898944A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53120289A (en) * | 1977-03-30 | 1978-10-20 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4538343A (en) * | 1984-06-15 | 1985-09-03 | Texas Instruments Incorporated | Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking |
| US4561172A (en) * | 1984-06-15 | 1985-12-31 | Texas Instruments Incorporated | Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions |
| JPS6175539A (ja) * | 1984-06-15 | 1986-04-17 | テキサス インスツルメンツ インコ−ポレイテツド | 集積回路の製造方法 |
| JPS6175540A (ja) * | 1984-06-15 | 1986-04-17 | テキサス インスツルメンツ インコ−ポレイテツド | 集積回路の製法 |
| JPS6148934A (ja) * | 1984-08-16 | 1986-03-10 | Matsushita Electronics Corp | 半導体装置の製造方法 |
| US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| KR100336543B1 (ko) * | 1993-09-23 | 2002-11-29 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 반도체장치제조방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0336302B2 (enrdf_load_stackoverflow) | 1991-05-31 |
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