JPH031828B2 - - Google Patents

Info

Publication number
JPH031828B2
JPH031828B2 JP58224744A JP22474483A JPH031828B2 JP H031828 B2 JPH031828 B2 JP H031828B2 JP 58224744 A JP58224744 A JP 58224744A JP 22474483 A JP22474483 A JP 22474483A JP H031828 B2 JPH031828 B2 JP H031828B2
Authority
JP
Japan
Prior art keywords
conductive layer
semiconductor
circuit board
semiconductor element
element chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58224744A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60116157A (ja
Inventor
Kazuyuki Shimada
Takafumi Kashiwagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58224744A priority Critical patent/JPS60116157A/ja
Publication of JPS60116157A publication Critical patent/JPS60116157A/ja
Publication of JPH031828B2 publication Critical patent/JPH031828B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4827—Materials
    • H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP58224744A 1983-11-29 1983-11-29 半導体装置 Granted JPS60116157A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58224744A JPS60116157A (ja) 1983-11-29 1983-11-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58224744A JPS60116157A (ja) 1983-11-29 1983-11-29 半導体装置

Publications (2)

Publication Number Publication Date
JPS60116157A JPS60116157A (ja) 1985-06-22
JPH031828B2 true JPH031828B2 (enExample) 1991-01-11

Family

ID=16818554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58224744A Granted JPS60116157A (ja) 1983-11-29 1983-11-29 半導体装置

Country Status (1)

Country Link
JP (1) JPS60116157A (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6243138A (ja) * 1985-08-21 1987-02-25 Seiko Instr & Electronics Ltd 液晶表示装置のｉｃ実装構造
JPS6347942A (ja) * 1986-08-18 1988-02-29 Fuji Xerox Co Ltd 半導体装置
EP0265077A3 (en) * 1986-09-25 1989-03-08 Sheldahl, Inc. An anisotropic adhesive for bonding electrical components
FR2618254B1 (fr) * 1987-07-16 1990-01-05 Thomson Semiconducteurs Procede et structure de prise de contact sur des plots de circuit integre.
JPH01132138A (ja) * 1987-08-13 1989-05-24 Shin Etsu Polymer Co Ltd Ｉｃチップの電気的接続方法、樹脂バンプ形成材料および液晶表示器
JP2666299B2 (ja) * 1987-10-08 1997-10-22 ソニー株式会社 固体撮像装置
JPH0234951A (ja) * 1988-04-20 1990-02-05 Seiko Epson Corp 半導体装置の実装構造
JPH02199847A (ja) * 1989-01-27 1990-08-08 Shin Etsu Polymer Co Ltd Ｉｃチップの実装方法
US5136365A (en) * 1990-09-27 1992-08-04 Motorola, Inc. Anisotropic conductive adhesive and encapsulant material
KR100218996B1 (ko) * 1995-03-24 1999-09-01 모기 쥰이찌 반도체장치
CA2156941A1 (en) * 1995-08-21 1997-02-22 Jonathan H. Orchard-Webb Method of making electrical connections to integrated circuit
JPH09199506A (ja) * 1995-11-15 1997-07-31 Citizen Watch Co Ltd 半導体素子のバンプ形成方法
US6396712B1 (en) * 1998-02-12 2002-05-28 Rose Research, L.L.C. Method and apparatus for coupling circuit components
JP4761164B2 (ja) * 2006-03-31 2011-08-31 ブラザー工業株式会社 接続構造、および部品搭載基板

Also Published As

Publication number Publication date
JPS60116157A (ja) 1985-06-22

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