JPH033384B2 - - Google Patents

Info

Publication number
JPH033384B2
JPH033384B2 JP59275493A JP27549384A JPH033384B2 JP H033384 B2 JPH033384 B2 JP H033384B2 JP 59275493 A JP59275493 A JP 59275493A JP 27549384 A JP27549384 A JP 27549384A JP H033384 B2 JPH033384 B2 JP H033384B2
Authority
JP
Japan
Prior art keywords
chip
conductive powder
paint
conductive
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59275493A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61158163A (ja
Inventor
Kazuyuki Shimada
Hiroshi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59275493A priority Critical patent/JPS61158163A/ja
Publication of JPS61158163A publication Critical patent/JPS61158163A/ja
Publication of JPH033384B2 publication Critical patent/JPH033384B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP59275493A 1984-12-29 1984-12-29 バンプの形成方法 Granted JPS61158163A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59275493A JPS61158163A (ja) 1984-12-29 1984-12-29 バンプの形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59275493A JPS61158163A (ja) 1984-12-29 1984-12-29 バンプの形成方法

Publications (2)

Publication Number Publication Date
JPS61158163A JPS61158163A (ja) 1986-07-17
JPH033384B2 true JPH033384B2 (enExample) 1991-01-18

Family

ID=17556274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59275493A Granted JPS61158163A (ja) 1984-12-29 1984-12-29 バンプの形成方法

Country Status (1)

Country Link
JP (1) JPS61158163A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63181450A (ja) * 1987-01-23 1988-07-26 Matsushita Electric Ind Co Ltd 半導体素子用バンプ及びその製造方法
JP2681931B2 (ja) * 1987-07-03 1997-11-26 松下電器産業株式会社 半導体素子
JP2001237268A (ja) * 2000-02-22 2001-08-31 Nec Corp 半導体素子の実装方法及び製造装置

Also Published As

Publication number Publication date
JPS61158163A (ja) 1986-07-17

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term