JPH0315764B2 - - Google Patents

Info

Publication number
JPH0315764B2
JPH0315764B2 JP58177262A JP17726283A JPH0315764B2 JP H0315764 B2 JPH0315764 B2 JP H0315764B2 JP 58177262 A JP58177262 A JP 58177262A JP 17726283 A JP17726283 A JP 17726283A JP H0315764 B2 JPH0315764 B2 JP H0315764B2
Authority
JP
Japan
Prior art keywords
circuit
semiconductor memory
delay
delay circuits
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58177262A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6069722A (ja
Inventor
Yoshiaki Narita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58177262A priority Critical patent/JPS6069722A/ja
Publication of JPS6069722A publication Critical patent/JPS6069722A/ja
Publication of JPH0315764B2 publication Critical patent/JPH0315764B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58177262A 1983-09-26 1983-09-26 タイミング調整方法 Granted JPS6069722A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58177262A JPS6069722A (ja) 1983-09-26 1983-09-26 タイミング調整方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58177262A JPS6069722A (ja) 1983-09-26 1983-09-26 タイミング調整方法

Publications (2)

Publication Number Publication Date
JPS6069722A JPS6069722A (ja) 1985-04-20
JPH0315764B2 true JPH0315764B2 (enrdf_load_html_response) 1991-03-01

Family

ID=16027986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58177262A Granted JPS6069722A (ja) 1983-09-26 1983-09-26 タイミング調整方法

Country Status (1)

Country Link
JP (1) JPS6069722A (enrdf_load_html_response)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01175408A (ja) * 1987-12-29 1989-07-11 Matsushita Electric Ind Co Ltd 信号遅延装置
JP2741704B2 (ja) * 1990-08-01 1998-04-22 三田工業 株式会社 パルス発生器用データ生成装置
JPH04331507A (ja) * 1991-05-07 1992-11-19 Nec Eng Ltd 遅延回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5390834A (en) * 1977-01-21 1978-08-10 Hitachi Ltd Lsi logic circuit containig timing pulse switching circuit
JPS55960A (en) * 1978-06-20 1980-01-07 Fujitsu Ltd Clock distributor

Also Published As

Publication number Publication date
JPS6069722A (ja) 1985-04-20

Similar Documents

Publication Publication Date Title
US3633174A (en) Memory system having self-adjusting strobe timing
US6795906B2 (en) Memory controller, interface device and method using a mode selection signal to support different types of memories
JPS625406A (ja) 状態装置
JPH1056361A (ja) 疑似雑音系列発生器
US3675133A (en) Apparatus and method independently varying the widths of a plurality of pulses
US6320818B1 (en) Semiconductor storage device, and method for generating timing of signal for activating internal circuit thereof
WO1988000733A1 (en) Data input circuit with digital phase locked loop
JPS61170150A (ja) 時分割多元接続方式における基準局の従局制御装置
JPS60120421A (ja) デイジタル・コンピユ−タのクロツク信号を最適に調節する方法
JPH0315764B2 (enrdf_load_html_response)
KR950003994B1 (ko) 디스크 동기 제어 장치 및 동기 제어 방법
JPH03191409A (ja) 出力制御回路
JPS63224514A (ja) デユ−テイ制御回路
JP2000187612A (ja) データフェッチタイミング切り替え回路
JP2867480B2 (ja) メモリ切替回路
EP1122733A1 (en) Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit
JP3348247B2 (ja) データ遅延制御方式
JPS61270999A (ja) フレ−ム同期回路
JPH1125030A (ja) バス拡張制御回路
KR100334533B1 (ko) 커맨드 어드레스와 라이트 데이터 동기장치
JP2617575B2 (ja) データ速度変換回路
JPS61243527A (ja) ビツトバツフア回路
JPH05102882A (ja) 冗長系選択回路
JP2679471B2 (ja) クロック切替回路
JPH04288736A (ja) データ書込み、読出し装置