JPH0315764B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a timing adjustment method for a timing generation circuit having a plurality of delay circuits in a synchronous digital device.

(b) Background of technology With recent advances in digital technology and semiconductor integrated circuit technology, methods for transmitting and processing digital information will become the core of advanced information communication systems using digital communication and various digital information processing systems. Furthermore, it is developing by adopting the latest technologies such as digital signal processing technology and large-scale semiconductor integrated circuit technology.

These synchronous digital devices that use digital signal processing technology are equipped with a timing generation circuit, which is the basis of a digital information processing system, and the synchronization signal ( clock, etc.) to operate synchronous digital equipment. Therefore, the timing generation circuit provided in each synchronous digital device adjusts the phase timing of the delay circuit in the timing generation circuit to incorporate phase timing suitable for each device, and adjusts the timing to obtain multiple phase timings. Work is done. These timing adjustments require high precision as electronic equipment becomes more sophisticated and faster, and it becomes necessary to make adjustments that also take into account variations in delay circuits.

(c) Prior Art and Problems Conventional timing adjustment work of this type will be explained below. FIG. 1 shows a circuit configuration block diagram of a conventional timing adjustment method. Reference numeral 1 denotes a circuit to be adjusted, and a plurality of delay circuits 21...2n are connected in series to the adjustment points of the circuit to be adjusted 1 by an amount that takes into account variations, and each connection point of the delay circuits 21...2n is connected to a short circuit. 3 selection terminals 41...4n. The output signal from the shot circuit 3 and the input signal input to the circuit to be adjusted 1 are sent to the oscilloscope 5.
Connect to. Timing adjustment work for many types of phases required for synchronous digital equipment is performed by adjusting the selection terminals 41...4n in the short circuit 3, which are input from the respective connection points of the delay circuits 21...2n, for the timing of one phase. Select and output as appropriate, compare the phase difference between the input signal of the circuit to be adjusted 1 and the output signal from the short circuit 3 using the oscilloscope 4, and if the target value is obtained, move on to timing adjustment of the next phase.
This selection adjustment is sequentially repeated for the required number of timings. Therefore, if many types of timing are required, the number of circuits to be adjusted 1 will be multiple, and each time one timing is adjusted, opening/shorting of the selection terminals 41...4n of the short circuit 3 will be repeated. This has the drawback of requiring a lot of work and a lot of man-hours for timing adjustment work.

(d) Object of the invention The present invention aims to solve this conventional drawback.

(e) Structure of the Invention The above object is to provide a plurality of series-connected delay circuits that create timings of synchronization signals of a plurality of phases and pulse widths, and to store delay phase data for selecting the plurality of delay circuits. a write circuit for writing delay phase data of the delay circuit into the semiconductor memory; and a data selector for selectively controlling the plurality of delay circuits based on the delay phase data in the semiconductor memory or an output from a counter. and a phase comparison circuit compares a phase difference between an output signal output from the timing generation circuit and an input signal input to the timing generation circuit, and updates the output of the counter in the plurality of delay circuits. When the phase difference reaches a predetermined value when the phase difference reaches a predetermined value,
This is achieved by the present invention, which is configured to stop updating the counter and write the counter value at this time into the semiconductor memory as the delayed phase data.

That is, a semiconductor memory in which delay phase data of each of a plurality of delay circuits is stored is prepared in advance by means for storing delay phase data of each of a plurality of delay circuits, and in order to obtain a predetermined timing, the delay phase data in the semiconductor memory is read out by a data selector. This method selects and connects delay circuits that can obtain a predetermined timing under the control of The present invention provides a method that can significantly reduce the number of man-hours for timing adjustment, since the only work required is to store the delay phase data of each delay circuit in the semiconductor memory.

(f) Embodiment of the Invention An embodiment of the present invention will be described below. Second
The figure shows a block diagram of a storage circuit for delayed phase data according to the present invention, and the same objects are designated by the same reference numerals throughout the figures. 6 is a circuit to be adjusted, 7 is a data selector, 8 is an up/down counter, 9 is a phase comparison circuit, 10 is a ROM writer, 11 is a semiconductor memory, 12 is a semiconductor memory circuit, and the data selector in the circuit to be adjusted 6 7 is controlled by the control signal of the up/down counter 8, and the phase comparison circuit 9 receives the input signal of the circuit to be adjusted 6 and the output signal from the data selector 7, and controls the up/down of the up/down counter 8. It is configured to send out a counter control signal to control and also send out a write signal to write the count value of the up/down counter 8 to the semiconductor memory 11 of the ROM writer 10. Note that the semiconductor memory circuit 12 is inserted with the semiconductor memory 11 that stores delayed phase data. It does not operate when writing in a circuit that stores delayed phase data.

In FIG. 2, the data selector 7 is controlled by the control signal of the up/down counter 8, sends its output signal to the phase comparator circuit 9, and the phase comparator circuit 9 calculates the phase difference with the input signal of the circuit to be adjusted 6. The up/down counter 8 is detected, the up/down counter 8 is operated until the target value is reached, the up/down count is repeated, and when the target value is reached, the up/down counter 8 is stopped and the phase comparator circuit 9 writes the up/down counter 8 to the ROM writer 10. A signal is sent to write the count value of the up/down counter 8 to the semiconductor memory 11 of the ROM writer 10. This detection write operation is repeated for the number of circuits to be adjusted 6, and each delay phase data of the circuits to be adjusted 6 is stored in the semiconductor memory 11.

FIG. 3 shows a circuit configuration block diagram of the circuit to be adjusted after timing adjustment according to the present invention, and 12 is the second circuit.
Delay circuits 21...2 of the circuit to be adjusted 6 by the method shown in the figure.
Semiconductor memory 1 storing n delay phase data
1 shows a semiconductor memory circuit in which 1 is inserted. To obtain a predetermined timing, the data selector 7 reads the delay phase data of the semiconductor memory circuit 12, selects and connects the delay circuits 21...2n in the circuit to be adjusted 6, and outputs a timing signal of a predetermined phase. . Therefore, by adopting the circuit configuration of the present invention, the timing adjustment method can easily obtain the required phase timing at the same time as the power is turned on.

(g) Effects of the Invention As explained above, the timing adjustment of the phase of a timing generation circuit having a plurality of delay circuits in a synchronous digital device is performed using means for storing delay phase data of each of a plurality of delay circuits according to the present invention. By providing a data selector that reads out the semiconductor memory stored in the semiconductor memory and the delay phase data in the semiconductor memory, and selects and connects the delay circuit that provides the predetermined timing, complicated manual timing adjustment work is no longer required. This has the effect of significantly reducing timing adjustment man-hours.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration block diagram of a conventional timing adjustment method, FIG. 2 is a delay phase data storage circuit configuration block diagram according to the present invention, and FIG. 3 is a circuit configuration block diagram of a circuit to be adjusted after timing adjustment according to the present invention. Show the diagram. In the drawing, 21...2n are delay circuits, 6 is a circuit to be adjusted, 7 is a data selector, and 8 is an up/down circuit.
A down counter, 9 a phase comparison circuit, 10 a ROM writer, 11 a semiconductor memory, and 12 a semiconductor memory circuit, respectively.

Claims (1)

[Claims] 1. A plurality of series-connected delay circuits that create timings of synchronization signals of a plurality of phases and pulse widths, a semiconductor memory that stores delay phase data for selecting the plurality of delay circuits, and a semiconductor memory that stores delay phase data for selecting the plurality of delay circuits; a write circuit for writing delayed phase data into a semiconductor memory; and a data selector for selectively controlling the plurality of delay circuits based on the delayed phase data in the semiconductor memory or output from a counter, A phase comparison circuit compares a phase difference between an output signal input to the timing generation circuit and an input signal input to the timing generation circuit, and selects the plurality of delay circuits in a scanning manner by updating the output of the counter. The method is characterized in that the comparison is continued, and when the phase difference reaches a predetermined value, updating of the counter is stopped, and the value of the counter at this time is written into the semiconductor memory as the delayed phase data. How to adjust timing.