JP2000268587A - Synchronizing type semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a synchronizing type semiconductor integrated circuit device in which the setup time, holding time, access time, and data holding time can be easily changed, the developing period of a system can be shortened and the manufacturing cost can be reduced. SOLUTION: This device is provided with input circuits 1, 1-1 to 1-n of a first external signal and a second external signal, variable delay circuits 2-a, 2-b, 2-1 to 2-n, external signal judging circuits 3-1 to 3-n judging the output of the variable delay circuit 2-1 to 2-n synchronizing with the output of the variable delay circuit 2-b, an internal logic circuit 4 performing a prescribed internal operation by their output and first external signal, output control circuits 5-1 to 5-n outputting the result synchronizing with the output of the variable delay circuit 2-a, and a storage circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor integrated circuit device which synchronizes with an externally input signal, takes in other input signals, and outputs an output signal. An object of the present invention is to provide a synchronous semiconductor integrated circuit device in which an access time and a data hold time can be easily changed.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a configuration of a conventional synchronous semiconductor integrated circuit device. In the configuration shown in the figure, input circuits 1, 1-1 to 1-n provided respectively for a first external signal serving as a reference signal and a plurality of second external signals are provided.
A fixed delay circuit 7-1 to 7-n which is fixed to a predetermined delay amount and delays an input signal; and a delay circuit 7 which is synchronized with the first external signal and provided for the second external signal.
External signal determination circuits 3-1 to 3-n for determining the logic levels (high or low) of the outputs of -1 to 7-n, an internal logic circuit 4 for performing a predetermined internal operation using the results,
An output control circuit 5-1 for outputting a result obtained by the internal logic circuit 4 to the outside of the semiconductor integrated circuit device in synchronization with an external clock.
5-m.

In such a configuration, a setup time and a hold time between a first external signal and a second external signal serving as reference signals are determined by delay circuits 7-1 to 7-1 provided for the second external signal. 7-n is determined according to the fixed delay amount.

Also, a state setting circuit for setting a state by a state setting command and an address input and outputting a signal is provided so that the setup time and the hold time can be changed. A synchronous semiconductor integrated circuit device has also been proposed in which a setup time and a hold time can be determined by delaying two external signals.

[0005]

As described above, in a conventional synchronous semiconductor integrated circuit device in which a setup time and a hold time (typically about 1 ns to 3 ns) are determined according to a fixed delay amount, a conventional semiconductor integrated circuit device is used. When operating, an input signal must be input to the semiconductor integrated circuit within the prescribed time. Further, the signal output from the synchronous semiconductor integrated circuit device is also output in synchronization with the first external signal, and its data hold time (usually 2 ns to 3 ns) is determined in the same manner as the setup time and the hold time. Time (the output signal is cut off at a fixed time), and within that time, it is necessary to complete the reception of the signal of another synchronous semiconductor integrated circuit device. Therefore, in another semiconductor integrated circuit device that exchanges signals with the synchronous semiconductor integrated circuit device, the first external signal serving as a reference signal and the timing adjustment of other second external signals and the first external signal are used. Increased design man-hours of the semiconductor integrated circuit device itself for delicate timing adjustment of received signals, and the use of a multi-layer substrate with less timing deviation between the first external signal and other signals cause factors in cost increase as a system. Had become.

Further, in a synchronous semiconductor integrated circuit device in which a state is set by a state setting command and an address input and a setup time and a hold time can be determined by a signal from a state setting circuit for outputting a signal, the synchronous semiconductor integrated circuit is provided. Another synchronous semiconductor integrated circuit device that sends data to the device must be designed in advance so that the state can be set to the state setting circuit, and when the system is constructed, the design of the semiconductor integrated circuit device or the semiconductor integrated circuit When a delay difference between the first external signal and the second external signal is large due to a problem of a board between circuit devices and a change in setting information to the state setting circuit occurs, the design change is performed. This increases the man-hours and delays the development period.

According to the present invention, the setup time, the hold time, the access time, and the data hold time of a synchronous semiconductor integrated circuit device can be easily changed. It is an object of the present invention to provide a synchronous semiconductor integrated circuit device capable of shortening and reducing costs.

[0008]

According to a first aspect of the present invention, there is provided a synchronous semiconductor integrated circuit device which inputs a plurality of second external signals and outputs a plurality of signals in synchronization with a first external signal. An integrated circuit device, comprising: an input circuit for receiving a first external signal and a second external signal; a variable delay circuit capable of delaying an output of the input circuit; and a variable delay circuit for the first external signal. An external signal determining circuit for determining the logical level of the output of the second external signal variable delay circuit in synchronization with the output; and a predetermined internal circuit based on the output of the first external signal and the external signal determining circuit captured by the input circuit. An internal logic circuit for performing an operation, an output control circuit for outputting a result obtained by the internal logic circuit to the outside of the semiconductor integrated circuit in synchronization with an output of the first external signal variable delay circuit, and a programmable storage circuit The provided, depending on the information stored in the memory circuit, it is characterized in that the delay amounts of the plurality of variable delay circuit can be changed independently.

According to the synchronous semiconductor integrated circuit device of the first aspect, the setup of the synchronous semiconductor integrated circuit device,
The hold time, access, and data hold time can be easily changed. This makes it possible to set the optimal setup, hold time, access, and data hold time for another synchronous semiconductor integrated circuit device that exchanges data with the synchronous semiconductor integrated circuit device of the present invention. The efficiency of development of a system including a semiconductor integrated circuit can be improved.

According to a second aspect of the present invention, there is provided a synchronous semiconductor integrated circuit device according to the first aspect, wherein the variable delay circuit connected to the first external signal input circuit has two circuits for an input determination circuit and an output control circuit. It is composed of

According to the synchronous semiconductor integrated circuit device of the second aspect, in addition to the same effects as those of the first aspect, the setup, hold time and access, and data hold time of the synchronous semiconductor integrated circuit device are individually set. Can be changed. As a result, a more flexible synchronous semiconductor integrated circuit device can be realized.

According to a third aspect of the present invention, there is provided a synchronous semiconductor integrated circuit device according to the first aspect, wherein the storage circuit uses an arbitrarily rewritable nonvolatile memory.

According to the synchronous semiconductor integrated circuit device of the third aspect, the same effect as that of the first aspect is obtained.

According to a fourth aspect of the present invention, there is provided a synchronous semiconductor integrated circuit device according to the first aspect, wherein the storage circuit uses a register which can be rewritten according to the state of the potential of the second external signal when the power is turned on. .

According to the synchronous semiconductor integrated circuit device of the fourth aspect, the same effect as that of the first aspect is obtained.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a configuration of a semiconductor integrated circuit device according to one embodiment of the present invention. As shown in FIG. 1, input circuits 1 and 1-1 for taking into a semiconductor integrated circuit device a first external signal serving as a reference signal and a plurality of second external signals 1 to n for controlling the semiconductor integrated circuit device. ~ 1-n
And variable delay circuits 2-a, 2-a that can delay the output of the input circuit for the first external signal and the second external signal.
-B, 2-1 to 2-n, and the output of the second external signal variable delay circuits 2-1 to 2-n in synchronization with the output signal of the first external signal variable delay circuit 2-b. External signal determination circuits 3-1 to 3-n for determining a logic level (high or low)
And a first external signal and external signal determination circuit 3-1 to 3-
n internal logic circuit 4 which performs a predetermined internal operation based on the output result of n
Output control circuits 5-1 to 5-m for outputting the result obtained by the internal logic circuit 4 to the outside of the semiconductor integrated circuit device in synchronization with the output of the first external signal variable delay circuit 2-a; And a programmable storage circuit 6. The output of the storage circuit 6 is controlled so that the delay amount of the variable delay circuit is independently determined according to the stored information.
b and 2-1 to 2-n. The variable delay circuits 2-a and 2-b connected to the first external signal input circuit 1 include two circuits for an input determination circuit and an output control circuit.

FIG. 2 shows variable delay circuits 2-a, 2-b, 2
FIG. 3 is a diagram illustrating the operation principle of −1 to n. Based on the information in the storage circuit 6, one of the outputs obtained by adding different delay amounts to the input signal is selected by a selector and output. In the example of FIG. 2, any one of four signals A, B, C, and D having different delay amounts can be selected based on 2-bit storage information. For example, when the stored information signals 1 and 2 are 0 and 0, respectively, the delay signal A having the smallest delay amount is selected, and the stored information signals 1 and 2 are selected.
2 is 1 and 0 respectively, the delay signal B with the next smallest delay is selected, and the stored information signals 1 and 2 are 0 and 1 respectively.
In the case of (1), the delay signal C having the next smallest delay amount is selected, and when the storage information signals 1 and 2 are 1, 1 respectively, the delay signal D having the largest delay amount is selected.

FIG. 3A shows operation timing waveforms of the first and second external signals when the amount of delay is changed in accordance with the information stored in the storage circuit 6. In the present embodiment, a clock is input as a first external signal at a certain period, and at the rising edge of the clock, the level of the second external signal is determined and the internal operation is determined. Here is an example. Accordingly, the setup times ts, ts ₁ are from the transition of the second external signal to the rising edge of the first external signal, and the hold times th, from the rising edge of the first external signal to the transition of the second external signal.
th ₁ to become. If the margin is small in set-up time, when the stored information signal 1 is allowed to store information in the memory circuit 6 so as to 0,0, respectively, Fig. (A ₁₎
As described above, the amount of delay of the second external signal is reduced, the margin of the setup time is further expanded inside the semiconductor integrated circuit device, the device operates normally even with the smaller setup time, and the margin of the hold time is small. case, when allowed to store information in the memory circuit 6 as stored information signal 1 is 1,1, respectively, as in FIG. (a _2), the delay amount of the second external signal is increased In the semiconductor integrated circuit device, the margin of the hold time is further expanded, and the semiconductor device operates normally even with a shorter hold time.

FIG. 3B shows an operation timing waveform of the output signal when the delay amount is changed. Less margin access time when (Margin no setup time of a semiconductor integrated circuit device which receives a signal of the semiconductor integrated circuit device), as shown in FIG. (B _1), the input circuit of the first external signal By selecting a signal with a small delay in the variable delay circuit connected to No. 1, the margin of the access time (setup time) can be maximized, and the margin of the data hold time is small (this semiconductor integrated circuit). If there is no margin in the hold time of a semiconductor integrated circuit device which receives a signal of the circuit arrangement), as shown in FIG. (b _2), a large delay in the first variable delay circuit which is connected to an external signal By selecting a signal, the margin of the data hold time (hold time) can be maximized.

Based on the information stored in the storage circuit 6, the variable delay circuits 2-a, 2-b, 2-1 to 2-n
Arbitrarily change the amount of delay, and allow the external signal determination circuit 3 to determine in synchronization with the first external signal, and by controlling the output signal, the setup, hold time and access time, data The hold time can be arbitrarily changed. Therefore, when a system is constructed using such a synchronous semiconductor integrated circuit device, the setup time and the hold time between the initially specified semiconductor integrated circuit devices are shifted, and normal operation cannot be performed. Even in this case, by using the semiconductor integrated circuit of the present invention and changing and using the storage information of the storage circuit in the semiconductor integrated circuit device, the setup time and the hold time during which the system operates normally can be changed. Become like Therefore, from the beginning of the system design, the system can be designed without much concern for the setup time and the hold time between the semiconductor integrated circuit devices, and the number of steps can be reduced. In addition, it is possible to use a less expensive substrate that does not care much about the transmission delay difference between the first external signal and the second external signal.

The memory circuit 6 may be a nonvolatile memory such as a flash memory which can be arbitrarily rewritten, or a register which can determine the potential of an external signal at power-on and store the stored information. The stored information can be programmed arbitrarily after the manufacture of the semiconductor integrated circuit device, and the synchronous semiconductor integrated circuit device does not make any changes to another semiconductor integrated circuit device that exchanges data with the semiconductor integrated circuit device. Can be used to build a system.

FIG. 4 shows means for judging the potential of an external signal at the time of power-on and storing information, and using a register capable of storing information in a specific external signal state. FIG.

When the power is turned on (when the potential rises from 0 V to a predetermined power supply level), a power-on detection circuit 10 for detecting a change in the potential and generating an output signal thereof; An input pin level determination circuit 11 for determining a potential level of an input pin for inputting an external signal at that time using an output; a register 12 for storing information obtained by the input pin level determination circuit 11;
And a register output circuit 13 for outputting the above information.

By configuring the storage circuit 6 with such a configuration, regarding storage of information in the storage circuit 6, it is necessary to connect an input pin required for information storage to a power supply via a resistor on a substrate. And by connecting to ground. This means that the semiconductor integrated circuit device that exchanges signals with the synchronous semiconductor integrated circuit device itself does not require any design change, and the advantages of shortening the development period and reducing the cost are extremely large.

As described above, according to this embodiment, information is stored in the programmable storage circuit, and the delay amount of the variable delay circuit connected to the first and second external signals is independently controlled by the information. Can be changed. Thereby, the phase of the first external signal and the second external signal serving as the reference signal, and the phase of the first external signal and the output signal can be adjusted, the setup time of the second external signal,
The hold time, the access time, and the data hold time can be easily changed, and a synchronous semiconductor integrated circuit device that can be independently and arbitrarily changed can be realized. Therefore, it is possible to easily avoid a malfunction due to a mismatch in setup and hold time between the semiconductor integrated circuit devices at the beginning of the system design without any design change for other synchronous semiconductor integrated circuit devices, and to reduce the number of design changes. In addition, the development time can be shortened, the man-hours required for system design can be reduced, and the difference in transmission delay between the reference signal and other signals can be reduced. The cost can be reduced, and the effect is extremely large.

By using a nonvolatile memory whose storage circuit can be arbitrarily rewritten, a system can be created without any change for another semiconductor integrated circuit device which exchanges data with the present semiconductor integrated circuit device. Becomes

[0028]

According to the synchronous semiconductor integrated circuit device of the first aspect, the setup, hold time, access, and data hold time of the synchronous semiconductor integrated circuit device can be easily changed. Thereby, the optimum setup for another synchronous semiconductor integrated circuit device that exchanges data with the synchronous semiconductor integrated circuit device of the present invention,
A hold time, an access time, and a data hold time can be set, and the efficiency of system development including these synchronous semiconductor integrated circuits can be improved.

According to the synchronous semiconductor integrated circuit device of the second aspect, in addition to the same effects as those of the first aspect, the setup, hold time and access, and data hold time of the synchronous semiconductor integrated circuit device are individually set. Can be changed. As a result, a more flexible synchronous semiconductor integrated circuit device can be realized.

According to the synchronous semiconductor integrated circuit device of the third aspect, the same effect as that of the first aspect is obtained.

According to the synchronous semiconductor integrated circuit device of the fourth aspect, the same effect as that of the first aspect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a variable delay circuit according to an embodiment of the present invention.

FIG. 3 is an operation timing waveform chart according to the embodiment of the present invention.

FIG. 4 is a block diagram of a storage circuit in one embodiment of the present invention.

FIG. 5 is a block diagram of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1-1 to 1-n input circuit 2-1 to 2-n variable delay circuit 5-1 to 5-m output control circuit 1 input circuit 2-a variable delay circuit 2-b variable delay circuit 3 external signal determination circuit 4 Internal logic circuit 6 Storage circuit 7 Fixed delay circuit 10 Power-on detection circuit 11 Input pin level judgment circuit 12 Register 13 Register output circuit

Claims (4)

[Claims] 1. A semiconductor integrated circuit device that inputs a plurality of second external signals and outputs a plurality of signals in synchronization with a first external signal, wherein the first external signal and the second An input circuit that captures an external signal of; a variable delay circuit that can delay an output of the input circuit; and an output circuit of the second external signal in synchronization with an output of the variable delay circuit of the first external signal. An external signal determination circuit that determines a logic level of an output of the variable delay circuit; and an internal logic circuit that performs a predetermined internal operation from an output of the first external signal and the external signal determination circuit captured by the input circuit. An output control circuit for outputting a result obtained by the internal logic circuit to the outside of the semiconductor integrated circuit in synchronization with an output of the variable delay circuit of a first external signal; and a programmable storage circuit. Depending on the information stored in the circuit, a synchronous semiconductor integrated circuit device, characterized in that the delay amount of the plurality of the variable delay circuit can be changed independently. 2. A variable delay circuit connected to an input circuit for a first external signal, comprising: a variable delay circuit for an input determination circuit and an output control circuit;
2. The synchronous semiconductor integrated circuit device according to claim 1, wherein said synchronous semiconductor integrated circuit device comprises two circuits. 3. The synchronous semiconductor integrated circuit device according to claim 1, wherein the storage circuit uses an arbitrarily rewritable nonvolatile memory. 4. The synchronous semiconductor integrated circuit device according to claim 1, wherein the memory circuit uses a register that can be rewritten according to the state of the potential of the second external signal when the power is turned on.