JPH0272695A - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPH0272695A
JPH0272695A JP63222413A JP22241388A JPH0272695A JP H0272695 A JPH0272695 A JP H0272695A JP 63222413 A JP63222413 A JP 63222413A JP 22241388 A JP22241388 A JP 22241388A JP H0272695 A JPH0272695 A JP H0272695A
Authority
JP
Japan
Prior art keywords
copper
ceramic substrate
hybrid integrated
copper plate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63222413A
Other languages
English (en)
Japanese (ja)
Inventor
Norio Kasai
笠井　則男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Lighting and Technology Corp
Original Assignee
Toshiba Lighting and Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Lighting and Technology Corp filed Critical Toshiba Lighting and Technology Corp
Priority to JP63222413A priority Critical patent/JPH0272695A/ja
Priority to US07/402,854 priority patent/US5036167A/en
Priority to FR8911726A priority patent/FR2636170A1/fr
Priority to DE3929789A priority patent/DE3929789C2/de
Publication of JPH0272695A publication Critical patent/JPH0272695A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/098—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/047—Attaching leadframes to insulating supports, e.g. for tape automated bonding [TAB]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
JP63222413A 1988-09-07 1988-09-07 混成集積回路 Pending JPH0272695A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP63222413A JPH0272695A (ja) 1988-09-07 1988-09-07 混成集積回路
US07/402,854 US5036167A (en) 1988-09-07 1989-09-06 Board for hybrid integrated circuit
FR8911726A FR2636170A1 (fr) 1988-09-07 1989-09-07 Circuit integre hybride dans lequel une plaque de cuivre est formee directement sur le substrat de ceramique, et son procede de fabrication
DE3929789A DE3929789C2 (de) 1988-09-07 1989-09-07 Schaltkreissubstrat für Dickfilmschaltung und Verfahren zu dessen Herstellung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63222413A JPH0272695A (ja) 1988-09-07 1988-09-07 混成集積回路

Publications (1)

Publication Number Publication Date
JPH0272695A true JPH0272695A (ja) 1990-03-12

Family

ID=16781995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63222413A Pending JPH0272695A (ja) 1988-09-07 1988-09-07 混成集積回路

Country Status (4)

Country Link
US (1) US5036167A (enExample)
JP (1) JPH0272695A (enExample)
DE (1) DE3929789C2 (enExample)
FR (1) FR2636170A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003111486A (ja) * 2001-09-26 2003-04-11 Kusatsu Electric Co Ltd 定点停止機能付き電動機
JP2005530353A (ja) * 2002-06-20 2005-10-06 クラミック エレクトロニクス ゲーエムベーハー 電気回路またはモジュール用の金属セラミック基板と、そのような基板およびそのような基板を含むモジュールを製作する方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991016805A1 (fr) * 1990-04-16 1991-10-31 Denki Kagaku Kogyo Kabushiki Kaisha Carte a circuits en ceramique
JPH04221888A (ja) * 1990-12-21 1992-08-12 Matsushita Electric Ind Co Ltd セラミック配線基板とその製造方法
US5210941A (en) * 1991-07-19 1993-05-18 Poly Circuits, Inc. Method for making circuit board having a metal support
JPH05166969A (ja) * 1991-10-14 1993-07-02 Fuji Electric Co Ltd 半導体装置
US5242535A (en) * 1992-09-29 1993-09-07 The Boc Group, Inc. Method of forming a copper circuit pattern
US6441313B1 (en) * 1999-11-23 2002-08-27 Sun Microsystems, Inc. Printed circuit board employing lossy power distribution network to reduce power plane resonances
EP1187521A1 (de) * 2000-09-09 2002-03-13 AB Mikroelektronik Gesellschaft m.b.H. Verfahren zur Herstellung einer Trägerplatte für elektronische Bauteile
DE102009047592B4 (de) * 2009-12-07 2019-06-19 Robert Bosch Gmbh Verfahren zur Herstellung eines Siliziumzwischenträgers
CN110226363B (zh) * 2017-03-30 2022-08-02 株式会社东芝 陶瓷铜电路基板及使用了其的半导体装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3549784A (en) * 1968-02-01 1970-12-22 American Lava Corp Ceramic-metallic composite substrate
US3787219A (en) * 1972-09-22 1974-01-22 Du Pont CaTiO{11 -CRYSTALLIZABLE GLASS DIELECTRIC COMPOSITIONS
US4129243A (en) * 1975-07-30 1978-12-12 General Electric Company Double side cooled, pressure mounted semiconductor package and process for the manufacture thereof
JPS6054721B2 (ja) * 1977-12-15 1985-12-02 日本電気株式会社 絶縁体形成用ペースト組成物
EP0074605B1 (en) * 1981-09-11 1990-08-29 Kabushiki Kaisha Toshiba Method for manufacturing multilayer circuit substrate
FR2556503B1 (fr) * 1983-12-08 1986-12-12 Eurofarad Substrat d'interconnexion en alumine pour composant electronique
US4563383A (en) * 1984-03-30 1986-01-07 General Electric Company Direct bond copper ceramic substrate for electronic applications
JPS61229389A (ja) * 1985-04-03 1986-10-13 イビデン株式会社 セラミツク配線板およびその製造方法
JPS61236192A (ja) * 1985-04-12 1986-10-21 株式会社日立製作所 セラミツク基板の電極形成方法
DE3621667A1 (de) * 1985-06-29 1987-01-08 Toshiba Kawasaki Kk Mit einer mehrzahl von dickfilmen beschichtetes substrat, verfahren zu seiner herstellung und dieses enthaltende vorrichtung
US4725333A (en) * 1985-12-20 1988-02-16 Olin Corporation Metal-glass laminate and process for producing same
US4687540A (en) * 1985-12-20 1987-08-18 Olin Corporation Method of manufacturing glass capacitors and resulting product
US4753694A (en) * 1986-05-02 1988-06-28 International Business Machines Corporation Process for forming multilayered ceramic substrate having solid metal conductors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003111486A (ja) * 2001-09-26 2003-04-11 Kusatsu Electric Co Ltd 定点停止機能付き電動機
JP2005530353A (ja) * 2002-06-20 2005-10-06 クラミック エレクトロニクス ゲーエムベーハー 電気回路またはモジュール用の金属セラミック基板と、そのような基板およびそのような基板を含むモジュールを製作する方法

Also Published As

Publication number Publication date
DE3929789A1 (de) 1990-03-29
DE3929789C2 (de) 1993-12-02
FR2636170A1 (fr) 1990-03-09
FR2636170B1 (enExample) 1995-03-17
US5036167A (en) 1991-07-30

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