JPH02234128A - Production of liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the conductive phenomenon of a thin film transistor by photoirradiation from being caused by forming an island-shaped electrode film of a gate electrode which consists of an opaque metallic film and is connected to a scanning signal line through a transparent conductive film and taking the island-shaped electrode film as a photomask so that the pattern of the semiconductor layer of the thin film transistor may be formed. CONSTITUTION:The gate electrode GT consists of the opaque metallic film g12 and is connected to the scanning signal line through the transparent conductive film g11. Since the pattern of the semiconductor layer AS of the thin film transistor TFT is formed by taking the island-shaped electrode film of the gate electrode GT as the photomask, the positional deviation of the island- shaped electrode film of the gate electrode GT from the semiconductor layer AS is not caused and backlight is not projected to the semiconductor layer AS. Thus, the conductive phenomenon of the thin film transistor TFT by the photoirradiation is prevented from being caused.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a method for manufacturing a liquid crystal display device such as an active matrix color liquid crystal display device in which a thin film transistor and a pixel electrode are used as constituent elements of a pixel. [Prior Art] In a conventional method for manufacturing an active matrix type liquid crystal display device, a photomask for forming an i-type semiconductor layer pattern is used when forming an i-type semiconductor layer pattern of a thin film transistor. An active matrix type liquid crystal display device using thin film transistors is known, for example, from "Nikkei Electronics," page 211, September 10, 1984, published by Nikkei McGraw-Hill. [Problems to be Solved by the Invention] However, in this method of manufacturing a liquid crystal display device, misalignment between the gate electrode made of an opaque metal film and the i-type semiconductor layer may occur, and in this case, the back The light hits the J-type semiconductor layer, and the light irradiation causes a conductive phenomenon in the thin film transistor. The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing a liquid crystal display device that does not cause a conductive phenomenon in thin film transistors due to light irradiation. [Means for Solving the Problems] In order to achieve this object, the present invention provides a method for manufacturing an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode are constituent elements of a pixel. An island-shaped electrode film of a gate electrode is formed and connected to a scanning signal line through a transparent conductive film, and a pattern of a semiconductor layer of the thin film transistor is formed using the island-shaped electrode film as a photomask. [Operation] In this method of manufacturing a liquid crystal display device, the pattern of the semiconductor layer of the thin film transistor is formed using the island-like electrode film of the gate electrode as a photomask, so that misalignment between the island-like electrode film of the gate electrode and the semiconductor layer is prevented. The backlight never hits the semiconductor layer. [Example] One pixel of the liquid crystal display section of an active matrix color liquid crystal display device to which this invention is applied is shown in FIG. Fig. 3 shows a cross section. Furthermore, FIG. 4 (plan view of main part) shows the main part of the liquid crystal display section in which a plurality of pixels shown in FIG. 2 are arranged. As shown in FIGS. 2 to 4, the liquid crystal display device includes a pixel having a thin film transistor TPT and a transparent pixel electrode ITO on the inner surface (liquid crystal side) of a lower transparent glass substrate SUBI. Lower transparent glass substrate SUBI
For example, 1. It is composed of a thickness of about 1 [n+m]. Each pixel is connected to two adjacent scanning signal lines (gate signal lines or horizontal signal lines) OL and two adjacent video signal lines (
(drain signal line or vertical signal line) DL (in the area surrounded by four signal lines).
As shown in FIGS. 2 and 4, the scanning signal line OL is
They extend in the column direction, and a plurality of them are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. The thin film transistor TPT of each pixel has three
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFTI, TPT2, and TFT3. Each of the thin film transistors TPT1 to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPT1 to TFT3 mainly has a gate electrode G.
T, insulating film GI. i-type (intrinsic, not doped with conductivity type determining impurities) silicon (Si
), a pair of source electrodes SDI
and a drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following explanation, for convenience, one side will be fixed as the source and the other as the drain. As shown in detail in FIG. 5 (a plan view of a main part in a predetermined manufacturing process), the gate electrode GT has a T-shape that protrudes from the scanning signal line GL in the row direction (downward in FIGS. 2 and 5). It is composed of shapes (branched into a T-shape). That is, the gate electrode GT is configured to extend substantially parallel to the video signal line DL. The gate electrode GT is configured to protrude to the formation region of each of the thin film transistors TPTI to TFT3.
The respective gate electrodes GT of the thin film transistors TPT1 to TFT3 are integrally formed (as a common gate electrode) and are continuously formed on the same scanning signal line OL. The gate electrode GT is formed of a single first conductive film g1 so as to avoid forming a large step as much as possible in the region where the thin film transistor TPT is formed. The first conductive film g1 is formed using, for example, a chromium (Cr) film formed by sputtering, and has a thickness of about 1100 [:person]. The gate electrode GT is formed to be thicker than the 51-type semiconductor layer AS (as viewed from below) so as to completely cover the 51-type semiconductor layer AS, as shown in FIGS. 2, 3, and 6. Therefore, when a backlight such as a fluorescent lamp is attached below the lower transparent glass substrate SUBI, the gate electrode GT made of opaque chromium becomes a shadow, and the i-type semiconductor layer A
s is not illuminated by backlight light, and the conductive phenomenon described above due to light irradiation, that is, the deterioration of the off-characteristics of the thin film transistor TPT, occurs one more time. Note that the original size of the gate electrode GT is the minimum required size (including the alignment margin between the gate electrode and the source/drain electrode) to straddle the source/drain electrodes SDI and SDZ, and the size of the channel lw The depth length that determines the gate width in this liquid crystal display device is determined by the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance [11]. The size of the electrode is of course larger than the original size mentioned above. Considering only the function of the gate and light shielding of the gate electrode GT, the gate electrode GT and its wiring GL may be integrally formed in a single layer. In this case, aluminum containing silicon is used as an opaque conductive material. Al). Pure aluminum, aluminum containing palladium (Pd), silicon, aluminum containing titanium (Ti), silicon, aluminum containing copper (Cu), etc. can be selected. The scanning signal line OL is constituted by a composite film consisting of a first conductive film g1 and a second conductive film g2 provided on top of the first conductive film g1. The first conductive film g1 of this scanning signal line (EL) is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and the second conductive film g1 is integrally formed with the first conductive film g1 of the gate electrode GT.
2 uses, for example, an aluminum film formed by sputtering, and is formed with a thickness of about 900 to 4000[:person]. The second conductive film g2 reduces the resistance value of the scanning signal line GL,
The structure is such that the signal transmission speed can be increased (writing characteristics of pixel information). Furthermore, the scanning borrow line GL is configured such that the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL is configured so that the step shape of its side wall can be made gentle, so that the surface of the insulating film GI on the upper layer thereof can be flattened. The insulating film GI is used as a gate insulating film for each of the thin film transistors TPTI to TFT3. Insulating film GI
teeth. It is formed in the upper layer of the gate electrode GT and the scanning signal line GL. The insulating film G1 is formed using, for example, a silicon nitride film formed by plasma CVD, and is formed to a film thickness of about 3500 mm.As mentioned above, the surface of the insulating film GI is
Forming regions of thin film transistors TF'1'1 to TFT3 and scanning signal lines G. The area where L is formed is flattened. The i-type semiconductor MAS is used as a channel formation region for each of the thin film transistors TPTI to TFT3 divided into a plurality of parts, as shown in detail in FIG. The i-type semiconductor layer AS of each of the plurality of divided thin film transistors TPT1 to TFT3 is integrally formed within the pixel. That is, a plurality of thin film transistors TP in which a pixel is divided
Each of T1 to TFT3 is composed of an island region of one (common) i-type semiconductor layer AS. i-type semiconductor layer A
S is formed of a non-quality silicon film or a polycrystalline silicon film, and is formed to a film thickness of approximately 2000 mm. This i-type semiconductor layer AS is formed by changing the components of the supplied gas.
Subsequently to the formation of the insulating film GI made of i3N4, it is formed using the same plasma CVD apparatus without being exposed to the outside from the apparatus. Further, a P-doped N+ type semiconductor layer do (FIG. 3) for ohmic contact is similarly formed continuously to a thickness of about 300 cm. Thereafter, the lower transparent glass substrate SUBI is taken out from the CVD apparatus, and the N1-type semiconductor layer dO and the i-type semiconductor layer AS are separated as shown in FIGS. 2, 3, and 6 using photo processing technology. It is buttered into island shapes. In this way, by integrally configuring the respective i-type semiconductor layers AS of the thin film transistors TPTI to TFT3 divided into a plurality of pixels, the thin film transistors TPTI
The drain electrode SD2 common to each of ~TFT3 is i
type semiconductor layer AS (actually, the film thickness of the first conductive film g1, N
Drain electrode SD
2 side toward the i-type semiconductor layer AS side. The probability of disconnection of the drain electrode SD2 is reduced, and the probability of point defects occurring can be reduced.
That is, in this liquid crystal display device, the point defects that occur within the pixel when the drain electrode SD2 crosses the step of the i-type semiconductor layer AS can be reduced to one-third. Although the layout of this liquid crystal display device is different, when the video signal line DL directly crosses over the i-type semiconductor layer AS and the video signal line DL in this overpassed portion is configured as the drain electrode SD2, the video signal line DL (drain Electrode SD
2) It is possible to reduce the probability of line defects occurring due to disconnection when the wire crosses the i-type semiconductor layer AS. In other words, the thin film transistor TPTI divided into multiple pixels
~By integrally configuring the respective i-type semiconductor layers AS of the TFT3, the video signal line DL (drain electrode SD2
) crosses the i-type semiconductor layer AS only once (actually twice, at the beginning and end of the ride). As shown in detail in FIGS. 2 and 6, the i-type semiconductor layer AS is provided so as to extend to a point where the scanning signal line GL and the video signal line DL intersect (crossover section). ing. This extended i-type semiconductor layer AS is configured to reduce short circuits between the scanning signal line GL and the video signal line DL at the intersection. Thin film transistors TPT1-T divided into a plurality of pixels
Each source electrode SDI and drain electrode S of FT3
As shown in detail in FIG. 2, FIG. 3, and FIG. 7 (plan views of main parts in predetermined manufacturing steps), D2 is provided separately on the i-type semiconductor layer As. Each of the source electrode SDI and drain electrode SD2 is configured such that when the bias polarity of the circuit changes, the source and drain are interchanged in operation. In other words, the thin film transistor TPT is bidirectional like a FET. Each of the source electrode SD1 and the drain electrode SD2 is
It is constructed by sequentially overlapping a first conductive film d1, a second conductive film d2, and a third conductive film d3 from the lower layer side in contact with the N+ type semiconductor layer do. First conductive film d of source electrode SDI
1. The second conductive film d2 and the third conductive film d3 are formed in the same manufacturing process as the drain electrode SD2. The first conductive film d1 is formed using a chromium film formed by sputtering, and has a thickness of 500 to 1000 [people] (in this liquid crystal display device, a film thickness of about .600 [people]). The thicker the chromium film is formed, the greater the stress, so it should be formed to a thickness of approximately 2,000 r. The chromium film has good contact with the N+ type semiconductor layer do. The chromium film prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer dO.
It makes up the so-called 7 layers of Paris. As the first conductive film d1, in addition to the chromium film, high melting point metals (Mo.Ti.Ta.W) are used.
) film, high melting point metal silicide (MoSi., TiSi.
．． , T a Si. , WSi, ) film. After patterning the first conductive film d1 by photoprocessing, the N+ type semiconductor layer do is removed using the same photoprocessing mask or using the first conductive film d1 as a mask. That is, the portion of the N+ type semiconductor layer dO remaining on the i-type semiconductor layer AS except for the first conductive film d1 is removed by the self-alignment. At this time, since the N+ type semiconductor layer dO is etched so that its entire thickness is removed, the i-type semiconductor layer AS is also slightly etched at its surface, but the extent can be controlled by the etching time. Thereafter, the second conductive film d2 is formed by sputtering aluminum to a thickness of 3,000 to 5,500 [people] (in this liquid crystal display device, a film thickness of about 3,500 [people]). The aluminum film has less stress than the chromium film and can be formed to a thick film thickness, making it suitable for the source electrode SDI.
, is configured to reduce the resistance values of the drain electrode SD2 and the video signal line DL. The second conductive film d2 is configured to increase the operating speed of the thin film transistor TPT and the signal transmission speed of the video signal line DL. In other words, the second conductive film d2 can improve the write characteristics of the pixel. In addition to the aluminum film, the second conductive film d2 may be formed of an aluminum film containing silicon, palladium, titanium, copper, or the like as an additive. After patterning the second conductive film d2 by photo processing technology,
The third conductive film d3 is a transparent conductive film (I
TO: Nesa film) is used, and the film thickness is 300 to 2400 [in] (in this liquid crystal display device, the film thickness is about 1200 [in]).
is formed. This third conductive film d3 is connected to the source electrode SD
I, the drain electrode SD2, and the video signal line DL, as well as the transparent pixel electrode ITO. First conductive film d1 of source electrode SDI, drain electrode SD
Each of the two first conductive films d1 has a channel forming region side larger in size than the second conductive film d2 and the third conductive film d3. In other words, the first conductive film d
1, even if mask misalignment occurs in the manufacturing process between the first conductive film d1, the second conductive film d2, and the third conductive film d3, it is larger than that between the second conductive film d2 and the third conductive film d3. Size (channel formation region side of each of the first conductor @dl to third conductor 111d3 may be on-the-line)
is configured to be. The first source electrode SDI
The conductive film d1 and the first conductive film d1 of the drain electrode SD2 are each configured to define the gate length L of the thin film transistor TPT. In this way, in the thin film transistors TPTI to TFT3 divided into a plurality of pixels, the source pole SDI, the do
By configuring the channel forming region side of each of the conductive films d1 of the source electrode SD2 to have a larger size than the second conductive film d2 and the third conductive film d3, the 1 conductive film d
With dimensions between l. *The gate length L of the membrane transistor TPT can be defined. Separation dimension between the first conductive films d1 (
The gate length) can be defined by processing accuracy (patterning accuracy), so thin film transistors TFT1~
The gate length L of each TFT 3 can be made uniform. As mentioned above, the source electrode SDI is connected to the transparent pixel electrode IT.
Connected to O. The source electrode SDI has a step shape of the i-type semiconductor layer AS (a step corresponding to the sum of the thickness of the first conductive film g1, the thickness of the N1-type semiconductor layer do, and the thickness of the i-type semiconductor layer AS). ). Specifically, the source electrode SDi includes a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS.
A second conductive film d2 is formed on the upper part of the conductive film d1 with a smaller size on the side connected to the transparent pixel electrode To.
and a third conductive film d3 connected to the first conductive film d1 exposed from the second conductive film d2. Source f! The first conductive film d1 of @sDI is an N+ type semiconductor layer dO
It has good adhesion to the second conductive film d2, and is mainly configured as a barrier layer against diffused substances from the second conductive film d2. The second conductive film d2 of the source electrode SDI cannot be formed thickly because the chromium film of the first conductive film d1 cannot be formed thickly due to increased stress, and the i-type semiconductor layer A. Since the step shape of S cannot be overcome, it is configured to overcome this i-type semiconductor layer AS. In other words, the second conductive film d2 improves the stepping force barrier by forming it thickly. Since the second conductive film d2 can be formed thickly, it greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). The third conductive film d3 is the second conductive film d
Since the step shape caused by the i-type semiconductor layer AS of No. 2 cannot be overcome, the second conductive film d2 is configured to be connected to the exposed first conductive film d1 by reducing its size. The first conductive film d1 and the third conductive film d3 are
Not only does it have good adhesion, but it also has a small step shape at the connection part between the rain showers, so it can be connected reliably. In this way, the source electrode SD of the thin film transistor TPT
I, a first conductive film d1 as a barrier layer formed along at least the i-type semiconductor layer AS, and this first conductive film d
The second conductive film d2 is formed on top of the second conductive film d2 and has a smaller specific resistance value than the first conductive film d1 and a smaller size than the first conductive film d1. A third transparent pixel electrode IT○ is formed on the exposed first conductive film d1.
By connecting the conductive film d3, the thin film transistor T
Since the PT and the transparent pixel electrode ITO can be reliably connected, point defects caused by disconnections can be reduced. Furthermore, the second conductive film d2 (aluminum film) having a low resistance value can be used for the source electrode SDI due to the barrier effect of the first conductive film d1, so that the resistance value can be reduced. The drain electrode SD2 is configured integrally with the video signal line DL, and is formed in the same manufacturing process. The drain electrode SD2 has an L-shape that protrudes in the column direction intersecting the video signal line DL. That is, the respective drain electrodes SD2 of the thin film transistors TPTI to TFT3 divided into a plurality of pixels are connected to the same video signal line DL. The transparent pixel electrode ITO is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode ITO is divided into three transparent pixel electrodes (divided transparent pixel electrodes) ITOI, ITO2, and ITO3 corresponding to each of the plurality of divided thin film transistors TPT1 to TFT3 of the pixel. The transparent pixel electrode ITOI is
It is connected to the source electrode SDI of the thin film transistor TFTI. The transparent pixel electrode ITO2 is connected to the source electrode SDI of the thin film transistor TFT2. The transparent pixel electrode ITO3 is connected to the source electrode SDI of the thin film transistor TFT3. Transparent pixel electrode ITOI~
Each of ITO3 is a thin film transistor TPT1 to T
Like each of the FT3s, they are constructed of virtually the same size. Each of the transparent pixel electrodes ITOI to IT○3 is integrally formed with the respective i-type semiconductor layers As of the thin film transistors TPTI to TFT3 (the divided thin film transistors TPT are arranged in a concentrated manner in one place). ), it is constructed in an L-shape. In this way, the thin film transistor TPT of a pixel arranged in the intersection area of two adjacent scanning signal lines OL and two adjacent video signal lines DL is replaced by a plurality of thin film transistors T.
By dividing the pixel into PTI to TFT3 and connecting each of the plurality of divided transparent pixel electrodes ITOI to ITO3 to each of the plurality of divided thin film transistors TPTI to TFT3, a divided part of the pixel (for example, the thin film transistor TF -T 1 ) becomes a point defect, but the pixel as a whole is not a point defect (the thin film transistors TFT2 and TFT3 are not point defects), so that the point defects of the pixel as a whole can be reduced. Further, since some of the point defects in which the pixel is divided are smaller than the entire area of the pixel (in the case of this liquid crystal display device, the area is one-third of the pixel), the point defects can be made difficult to see. Can be done. Further, the divided transparent pixel electrodes IT01 to I of the pixel
By configuring each TO3 to have substantially the same size, the area of point defects within a pixel can be made uniform. Furthermore, the divided transparent pixel electrodes ITo1 to ITo of the pixel are
By configuring each of the TO3 to have substantially the same size, each liquid crystal capacitor (Cpix) constituted by each of the transparent pixel electrodes ITOI to ITO3 and the common transparent pixel electrode ITO, and the transparent pixel electrodes ITOI to ITO
Transparent pixel electrode ITOI added to each of TO3~
The overlap capacitance (Cgs) caused by the overlap of ITO3 and gate electrode GT can be made uniform. In other words, since each of the transparent pixel electrodes ITOI to ITO3 can have a uniform liquid crystal capacitance and superimposed capacitance,
The DC component that is applied to the liquid crystal molecules of the liquid crystal LC due to this superimposed capacitance can be made uniform, and if a method of canceling this DC component is adopted, there will be variations in the DC component applied to the liquid crystal of each pixel. can be made smaller. A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode ITo. The protective film PSVI is formed mainly to protect the thin film transistor TPT from moisture, etc., and a film with high transparency and good moisture resistance is used. The protective film psvi is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and
It is formed with a film thickness of ooo to 11,000 [people] (in this liquid crystal display device, the film thickness is about 8,000 [people]). A shielding film LS is provided above the protection IIPsVI on the thin film transistor TFT to prevent external light from entering the i-type semiconductor layer AS used as a channel formation region. As shown in FIG. 2, the shielding film LS is configured within a region surrounded by a dotted line. The shielding film L S is formed of a film having a high light shielding property, such as an aluminum film or a chromium film, and is formed by sputtering to a thickness of approximately 1000 mm. Therefore, the common semiconductor RAS of the thin film transistors TPTI to TFT3 is sandwiched between the upper and lower light shielding films LS and the thick gate electrode GT, and is not exposed to external natural light or backlight light. The light shielding film LS and the gate electrode GT are formed to be thicker than the semiconductor layer AS and have a similar shape, and the sizes of the two are considered to be approximately the same (
In the figure, the gate electrode GT is drawn smaller than the light shielding film LS so that the boundary line can be seen). Note that it is also possible to attach the backlight to the upper transparent glass substrate SUB2 side and place the lower transparent glass substrate SUBI on the a side (externally exposed side). In this case, the light shielding film LS is connected to the gate electrode G' of the backlight light. r acts as a natural light shield. The thin film transistor TPT is configured such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large. That is, the thin film transistor TPT is configured to control the voltage applied to the transparent pixel electrode ITO. The liquid crystal LC is defined and sealed by a lower alignment film ○RII and an upper alignment film ORI2 that set the orientation of liquid crystal molecules in a space formed between a lower transparent glass substrate SUBI and an upper transparent glass substrate SUB2. ing. The lower alignment film ORII is attached to the lower transparent glass substrate SUB 1
0 [ is formed on top of the protective film PSVI. On the inner surface (liquid crystal side) of the upper transparent glass substrate SUB2, a color filter FIL, a protective film PSv2, a common transparent pixel electrode (COM) ITO, and the upper alignment film ORI are disposed.
2 are sequentially stacked. The common transparent pixel electrode IT○ is connected to the lower transparent glass substrate S.
It faces the transparent pixel electrode IT○ provided for each pixel on the UBI side, and is configured integrally with another adjacent common transparent pixel electrode ITO. A common voltage Vcom is applied to this common transparent pixel electrode ITO. The common voltage vcoII+ is an intermediate potential between the low-level instant voltage V d win applied to the video signal gDL and the high-level north dynamic voltage dmax. The color filter FIL is constructed by coloring a dyed base material made of a resin material such as acrylic resin with a dye. The color filter F I L is arranged for each pixel at a position facing the pixel, and is colored differently. That is,
The color filter FIL is similar to the pixel. Two scanning signal lines GL that are in contact with each other and two adjacent video signal lines D
It is configured within the intersection area with L. Each pixel is divided into a plurality of parts within each predetermined color filter of the color filter FIL. The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter formation area is removed using photolithography technology. After this, the dyed base material is dyed with red dye, fixed treatment is applied, and red filter R
form. Next, a green filter G and a blue filter B are sequentially formed by performing similar steps. In this way, by forming each color filter of the color filter FIL in the intersecting area facing each pixel, the scanning signal line OL and the video signal line DL each exist between each color filter of the color filter F-L. Therefore, it is possible to secure an alignment margin (enlarge the alignment margin) between each pixel and each color filter of the color filter FIL by the amount corresponding to their existence. Furthermore, when forming each color filter of the color filter FIL, it is possible to secure alignment margin dimensions between different color filters. That is, in this liquid crystal display device, a pixel is formed within the intersection area of two adjacent scanning signal lines GL and two adjacent video signal lines DL, and this pixel is divided into a plurality of parts, and the pixel is divided into a plurality of parts. By forming each color filter of the color filter FIL in the position where the color filter FIL is located, it is possible to reduce the above-mentioned point defects and to secure alignment margin between each pixel and each color filter. The protective film PSV2 is provided to prevent the dyes used to dye the color filters FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of a transparent resin material such as acrylic resin or epoxy resin. This liquid crystal display device has a lower transparent glass substrate SU? l side,
It is assembled by forming each layer on the upper transparent glass substrate SUB2 side separately, then overlapping the lower transparent glass substrate SUBI and the upper transparent glass substrate SUB2, and sealing the liquid crystal LC between them. As shown in FIG. 4, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal line OL extends, and a plurality of pixels are arranged in the same column direction as the direction in which the scanning signal line OL extends. , x,, x,, X4, respectively. Each pixel column X,, X,,X,, X4,
Each pixel of... is a thin film transistor TFTI
~The arrangement positions of TFT3 and transparent pixel electrodes ITo1 to ITO3 are configured to be the same. In other words, pixel rows X■,X
Each pixel of 3, . . . is a thin film transistor TP.
The arrangement position of TI~TFT3 is on the left side, transparent pixel electrode ITO
I to ITO3 are arranged on the right side. Each pixel in the next pixel column X,, X4,... in the row direction of each pixel column X, X3,... The video signal MDL
It is composed of pixels arranged line-symmetrically with respect to the In other words, a painting? In each pixel in columns X, X4, . . . , the thin film transistors TPTI to TFT3 are arranged on the right side, and the transparent pixel electrodes ITOI to ITO3 are arranged on the left side. Then, pixel row X. , X4,...
Each pixel of . In other words, if each pixel interval of pixel row X is 1.0 (1.O pitch), then the next pixel row They are shifted by 0.5 pixel intervals (0.5 pitch). The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X. In this way, in the liquid crystal display section, the thin film transistor T
A plurality of pixels with the same PT and transparent pixel electrode ITO arranged in the same position are arranged in the column direction to form a pixel column X, and the pixels in the next pixel column X and the previous pixel column It is composed of pixels arranged symmetrically with respect to the line DL, and by moving the next pixel column by half a pixel interval with respect to the previous pixel column, it is possible to overlap the pixels and color filters (see Fig. 8). As shown in the main part plan view in the combined state), a pixel in the previous stage pixel row X on which a predetermined color filter is formed (for example, a pixel in which a red filter R in pixel row The pixels in column X on which the same color filters are formed (for example, the pixels on pixel column X on which red filters R are formed) can be separated by 1.5 pixel intervals (1.5 pitch). In other words, the pixels in the previous pixel column
The color filter FIL can have an RGB triangular arrangement structure. Color filter FIL RO
The triangular arrangement structure of B can improve the color mixing of each color, so it can improve the resolution of the color image. Further, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. So, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal MDL and eliminate the multilayer wiring structure. The circuit configuration of this liquid crystal display section is shown in FIG. 9 (equivalent circuit diagram of the liquid crystal display section). XiG, X. i+IG, . . . are video signal lines DL connected to the pixels where the green filter G is formed.
It is. XiB, Xi+IB, . . . are video signal lines DLC'Al. X i + 1. R, X i + 2 R
, - is the video signal connected to the pixel where the red filter R is formed! It is DL. These video signal lines DL are selected by a video signal speeding circuit. Yi is a scanning signal line OL that selects the pixel column X1 shown in FIGS. 4 and 8.
It is. Similarly, each of Yi+1, Yi+2, . . . is a scanning signal line OL that selects each of the pixel columns X2, X, . These scanning signal lines OL are connected to a vertical scanning circuit. The center part of FIG. 3 shows the cross section of one pixel part, while the left side shows the cross section of the left edge part of the lower transparent glass substrate STJBI and the upper transparent glass substrate SUB2 where external lead wiring exists. ．． On the right side, transparent glass substrates SUBI and ST. It shows a cross section of the right side edge of JB2 where no external lead wiring is present. The sealing materials SL shown on the left and right sides of FIG. 3 are as follows:
It is configured to seal the liquid crystal LC, and is formed along the entire edges of the transparent glass substrates StJB1 and SUB2 except for the liquid crystal sealing opening (not shown). The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode IT○ on the side of the upper transparent glass substrate SUBZ is coated with silver paste material S at least in one place.
It is connected by IL to an external lead wiring formed on the lower transparent glass substrate SUBI side. This external lead wiring includes the aforementioned gate electrode GT, source electrode SDI,
It is formed in the same manufacturing process as each of the drain electrodes SD2. Said alignment film ○RII and ORI2, transparent pixel electrode IT
O, common transparent pixel electrode ITO. Protective film PSVI and P
Each layer of SV2 and insulating film GI is formed inside the sealing material SL. The polarizing plate POL is formed on the outer surface of each of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2. FIG. 10 is a cross-sectional view of the main part of the pixel and the periphery of the seal part of the liquid crystal display part of another active matrix type color liquid crystal display device to which the present invention is applied, and FIG.
0 is a plan view showing one pixel of the liquid crystal display section of the liquid crystal display device shown in FIG. A plan view of a main part of a liquid crystal display section in which a plurality of pixels are arranged, FIGS. 14 to 16 are plan views of main parts in a predetermined manufacturing process of the pixel shown in FIG. 11, and FIG. FIG. 3 is a plan view of main parts in a state in which color filters are superimposed. In this liquid crystal display device, it is possible to improve the aperture ratio of each pixel in the liquid crystal display section, reduce the direct current component applied to the liquid crystal, reduce point defects in the liquid crystal display section, and reduce black unevenness. . In this liquid crystal display device, as shown in FIG. 11, the i-type semiconductor layer AS in each pixel of the liquid crystal display section is
It is divided into FT1 to TFT3. In other words, the thin film transistor TPTI divided into a plurality of pixels
Each of the TFTs 3 is composed of an independent island region of an i-type semiconductor layer As. In addition, thin film transistors T F 'I' 1 to TFT3
Transparent pixel electrodes ITO1 to ITO connected to each of
3 are thin film transistors T P T 1 to T
On the side opposite to the side connected to FT3, it is overlapped with the scanning signal line GL of the next stage in the row direction. In this superposition, each of the transparent pixel electrodes IT○1 to ITQ3 is used as one electrode. A holding capacitor element (electrostatic capacitor element) Cadd is configured with the next stage scanning signal line GL as the other electrode. The dielectric film of this storage capacitor element C add is used as the gate insulating film of the thin film transistor TFT.
It is composed of the same layer as the lamina GI. The gate electrode GT is formed to be thicker than the i-type semiconductor 711AS, as in the liquid crystal display device shown in FIG.
In this liquid crystal display device, thin film transistors TPTI to TF
Since T3 is formed for each independent i-type semiconductor layer AS, a thick pattern is formed for each thin film transistor TPT. Furthermore, the scanning signal line GL. of the upper transparent glass substrate SUB2. Video signal line DL, thin film transistor T
Black matrix pattern B on the part corresponding to PT
Since M is provided, the outline of the pixel becomes clear, so that the contrast is improved and it is possible to prevent external natural light from hitting the thin film transistor TPT. The equivalent circuit of the pixel shown in Fig. 11 is shown in Fig. 18 (equivalent circuit diagram). In FIG. 18, as before, C
gs is a superimposed capacitance formed by the gate electrode GT and source electrode SDI of the thin film transistor TPT. The dielectric film of the superposed capacitance Cgs is an insulating film GI. C
p. f is a liquid crystal capacitance formed between the transparent pixel electrode ITO (PIX) and the common transparent pixel electrode ITO (COM). The dielectric films of the liquid crystal capacitor C pix are the liquid crystal LC, the protective film psv1, and the alignment films ORII and ORI2. Vi
e is the midpoint potential. The storage capacitance element C add is a thin film transistor TP
When T switches, the midpoint potential (pixel electrode potential)
It works to reduce the influence of gate potential change ΔVg on Vic. This situation can be expressed as the following formula. ΔV lc = ((Cgs/ (Cgs+Cadd+
Cpix)) xΔVg Here, ΔVlc represents the change in midpoint potential due to ΔVg. This change ΔVlc causes a DC component applied to the liquid crystal, but the storage capacitance element C
The larger the storage capacity of add, the smaller the value /h can be. In addition, the storage capacitance element C add has the effect of lengthening the discharge time, and the thin film transistor TF
To store video information for a long time after 1' is turned off. liquid crystal LC
Reducing the DC component applied to the LCD can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching between liquid crystal display screens. As mentioned above, since the gate electrode GT is large enough to completely cover the semiconductor layer AS, the overlap area with the source/drain electrodes SDI and SD2 increases, and therefore the parasitic capacitance Cgs increases, and the midpoint potential Vlc increases. This has the opposite effect of becoming more susceptible to the influence of the gate (scanning) signal Vg. However, this disadvantage can be overcome by providing the storage capacitor element Cadd. Further, in a liquid crystal display device having pixels in an intersection area of two scanning signal lines GL and two video signal lines DL, one scanning signal line GL of the two scanning signal lines GL may be
The thin film transistor TPT of the pixel selected in is divided into a plurality of parts, and the divided thin film transistors TPT1 to TF
A transparent pixel electrode ITO divided into a plurality of parts (ITOI to ITO3) is connected to each of T3, and the pixel electrode ITO is used as one electrode for each of the divided transparent pixel electrodes ITOI to ITO3, and the two scanning electrodes are connected to each other. By using the other scanning signal line GL of the signal lines GL as a capacitor electrode line to configure the storage capacitor element Cadd, which serves as the other electrode, a portion of the divided pixel can be prevented from becoming a point defect, as described above. Since the pixel as a whole is not a point defect, it is possible to reduce the point defect of the pixel, and it is also possible to reduce the DC component applied to the liquid crystal LC by the storage capacitor element C add, so that the liquid crystal LC can improve the lifespan of In particular, by dividing the pixel, it is possible to reduce point defects caused by short circuits between the gate electrode GT and the source electrode SDI or drain electrode SD2 of the thin film transistor TPT, and also to reduce the point defects caused by short circuits between the gate electrode GT of the thin film transistor TPT and the source electrode SDI or drain electrode SD2, and to reduce the point defects caused by short circuits between the transparent pixel electrodes ITOI to TO3. Point defects caused by short circuits between the capacitive element Cadd and the other electrode (capacitive electrode line) can be reduced. In this liquid crystal display device, the number of point defects on the latter side is one third. As a result, some of the point defects into which the pixel is divided are smaller than the entire area of the pixel, making it difficult to see the point defects. The storage capacitance of the storage capacitance element C add is 4 to 8 times (4
・Cpix<Cadd< 8 ・Cpix) . 8 to 32 times the superposition capacitance Cgs<8 ・Cgs<C
add<32・Cgs). Further, the scanning signal line GL is connected to a first conductive film (chromium film) g.
The other electrode of the storage capacitor element C add, that is, the branched portion of the capacitor electrode wire, is formed by a composite film in which a second conductive film (aluminum film) g2 is superimposed on the second conductive film (aluminum film) g2. By constructing the single-layer film consisting of one conductive film g1, it is possible to reduce the resistance value of the scanning signal line GL and improve the writing characteristics, and also to improve the storage capacitance element C a
One electrode of the storage capacitor element C add (transparent pixel electrode ITO)
can be bonded onto the insulating film GI, thereby reducing disconnection of one electrode of the storage capacitor element Cadd. Further, by configuring the other electrode of the storage capacitor element C add with the single-layer first conductive film g1 and not comprising the second conductive film g2 which is an aluminum film, the retention capacitor element C add due to hillocks of the aluminum film can be A short circuit between the other electrode and one M1 pole can be prevented. Similar to the source electrode SDI, a branched portion is provided between each of the transparent pixel electrodes ITOI to ITO3 overlapped to form the storage capacitor element C add and the branched portion of the capacitor electrode line. In order to prevent the transparent pixel electrode ITO from breaking when climbing over the stepped part,
An island region made up of a first conductive film d1 and a second conductive film d2 is provided. This island area is a transparent pixel electrode IT
The structure is made as small as possible so as not to reduce the area of O (aperture ratio). In this way, the first conductive film d1 and the first conductive film d1 formed thereon are connected between one electrode of the storage capacitor element Cadd and the insulating film used as its dielectric film. A base layer formed of the second conductive film d2 having a smaller specific resistance value and smaller size than that of the one electrode (
By connecting the third conductive film d3) to the first conductive film d1 exposed from the second conductive film d2 of the base layer, the storage capacitor can be reliably moved along the step portion based on the other electrode of the storage capacitor element Cadd. Since one electrode of the element C add can be bonded, disconnection of one electrode of the storage capacitor element C add can be reduced.The storage capacitor element C add is attached to the transparent pixel electrode IT○ of the pixel.
The liquid crystal display section of the liquid crystal display device provided with d is constructed as shown in FIG. 20 (equivalent circuit diagram showing the liquid crystal display section). The liquid crystal display section is constructed by repeating a unit basic pattern including pixels, scanning signal lines GL, and video signal lines DL. As shown in FIG. 20, the final stage scanning signal line GL (or first stage scanning signal line OL) used as a capacitor electrode line is connected to a common transparent pixel electrode (Vcom) I To
Connect to. As shown in FIG. 3, the common transparent pixel electrode ITO is connected to the external wiring at the periphery of the liquid crystal display device using a silver paste material SL. Moreover, some conductive layers (gl and g2) of this external lead wiring
is constructed in the same manufacturing process as the scanning signal IOL. As a result, the final stage scanning signal line OL (capacitive electrode line) can be easily connected to the common transparent pixel electrode ITO. In this way, by connecting the final stage of the capacitive electrode line to the common transparent pixel electrode (Vcom) I To of the pixel, the final stage of the capacitive electrode line is integrated with a part of the conductive layer of the external wiring. Moreover, since the common transparent pixel electrode ITO is connected to the external lead wiring, the final stage capacitor electrode line can be connected to the common transparent pixel electrode ITO with a simple configuration.
You can connect to. In addition, the liquid crystal display device is based on the DC cancellation method (DC cancellation method) described in Japanese Patent Application No. 62-95125 previously filed by the applicant, as shown in FIG. 19 (time chart). , by controlling the dynamic voltages of the scanning signal lines DL, it is possible to further reduce the DC component applied to the liquid crystal LC. In FIG. 19, Vi is the drive voltage of an arbitrary scanning borrow line GL, and Vi+1 is the drive voltage of the next stage scanning signal line OL. Vea is a low-level collective voltage Vd+*in applied to the scanning signal line OL
．． Vdd is a high-level drive voltage Vdwax applied to the scanning signal line GI. Each time t=j, ~t
The voltage change ΔVe~Δv4 of the midpoint potential Vlc (see Figure 18) at 4 is the total capacitance of the pixel (Cgs+
If Cpix+Cadd) is C, the following equation is obtained. ΔVm= (Cgs/C)・V2 ΔV2=+(Cgs/C)'(V1+V2)-(Cad
d/C)・V2 Δv,=1(Cgs/C)・v1+(Cadd/C){V1+V2) ΔV,=1(Cadd/C)・■1 Here, the drive applied to the scanning signal line OL If the voltage is sufficient (see below)

(See note), the DC voltage applied to the liquid crystal LC is expressed by the following formula. ΔV, +AV4=(Cadd-V2-Cgs-V1)/
C Therefore, if Cadd-v2=Cgs-v1,
The DC voltage applied to the liquid crystal LC becomes O.

〔Effect of the invention〕

As explained above, in the liquid crystal display device according to the present invention, the gate electrode film of the gate electrode is used as a photomask to form the semiconductor layer of the thin film transistor.
There is no misalignment between the island-shaped electrode film of the gate electrode and the semiconductor layer, and the backlight does not hit the semiconductor layer, so there is no conductivity phenomenon in the thin film transistor caused by light irradiation. In this way, the effects of this invention are remarkable.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a method for manufacturing an active matrix color liquid crystal display device according to the present invention, and FIG. 2 is a pixel of a liquid crystal display section of an active matrix color liquid crystal display device to which the present invention is applied. Figure 3 is a cross-sectional view of the area taken along the U-11 cutting line in Figure 2 and the area around the seal, Figure 4 is a liquid crystal display section with multiple pixels shown in Figure 2. Figures 5-1 and 7 are plan views of essential parts of the pixel shown in Figure 2 in a predetermined manufacturing process, and Figure 8 is a superimposition of the pixel shown in Figure 4 and a color filter. FIG. 9 is an equivalent circuit diagram showing the liquid crystal display section of the above-mentioned active matrix color liquid crystal display device, and FIG. 10 is a plan view of another active matrix color liquid crystal display device to which the present invention is applied. FIG. 11 is a cross-sectional view of the main part of a pixel and the vicinity of a sealing part of the liquid crystal display section of the liquid crystal display device, FIG. 11 is a plan view showing one pixel of the liquid crystal display section of the liquid crystal display device shown in FIG. 10, and FIG. A cross-sectional view of the part taken along the line A-A in Figure 11, and Figure 13 is the 1st
FIG. 1 is a plan view of a main part of a liquid crystal display section with a plurality of pixels arranged as shown in FIG. 1, FIGS. 18 is an equivalent circuit diagram of the pixel shown in FIG. 11, and FIG. 19 is a fluctuation voltage of the scanning signal line using the DC cancellation method. 20 and 21 are equivalent circuit diagrams showing the liquid crystal display section of the active matrix color liquid crystal display device shown in FIG. 13, and FIG. 22 is a time chart showing the manufacturing method shown in FIG. FIG. 3 is a plan view showing one pixel of the liquid crystal display section of the liquid crystal display device described above. SUB...Transparent glass substrate OL...Scanning signal line DL...Video signal line GI...Insulating film GT...Gate electrode AS...I-type semiconductor layer SD...Source electrode or drain electrode psv...
Protective film LS...Light shielding film LC...Liquid crystal TPT...Thin film transistor ITO (COM)...Transparent pixel electrodes g1, g2...
・First and second conductive films d1 to d3...First to third conductive films C add...Holding capacitor element Cgs...Superposition capacitor Cpix...Liquid crystal capacitor BM...Black matrix pattern gll... ...Transparent conductive film gl2... Opaque metal film 1 Figure 18 VLc 1;2 t. 5 t4 GL-111 Scan I Tomi No. 7 GT---Ke・Ito 1! Stone i gll=-1 bright conductive film gl2--10,000*pF+Golden bird moon mo

Claims (1)

[Claims] 1. In a method for manufacturing an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode are one component of a pixel, a gate electrode made of an opaque metal film and connected to a scanning signal line via a transparent conductive film is used. A method for manufacturing a liquid crystal display device, comprising forming an island-like electrode film, and forming a pattern of a semiconductor layer of the thin film transistor using the island-like electrode film as a photomask.