JP2660532B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a liquid crystal display device, in particular, an active matrix type liquid crystal display device in which pixels are constituted by thin film transistors and pixel electrodes. [Prior Art] The present applicant has previously proposed an active matrix type liquid crystal display device in which a pixel electrode is divided into a plurality of pixels (Japanese Patent Application No. Sho 62).
No. 309601). For convenience of explanation, the contents of the proposal are reproduced in FIGS. 2A to 14 in the present application. In the present application, FIG. 1A and FIG. 1B are added in relation to those figures, and an improved technique for the earlier application will be described. In addition, as a result of conducting a prior art search for the present application, the pixel division technology in an active matrix liquid crystal display device is disclosed in JP-A-57-49994, JP-A-59-78388, and JP-A-60-78388.
It was found to be known in JP-A-97322 and JP-A-61-77886. [Problem to be Solved by the Invention] In the above-mentioned prior application, although the pixel defect rate of the display panel as a whole can be reduced, it has been found that light leaks from a gap between the divided pixel electrodes, and the contrast deteriorates. An object of the present invention is to provide a liquid crystal display device capable of improving contrast. Another object of the present invention is to provide a liquid crystal display device in which degradation of TFT off characteristics caused by light incident on the TFT is reduced. Another object of the present invention is to provide a liquid crystal display device capable of improving the TFT off-characteristics and suppressing a DC component applied to the liquid crystal. Another object of the present invention is to provide a technique in a liquid crystal display device capable of reducing point defects in which pixels of a liquid crystal display section become defective. It is another object of the present invention to provide a technique capable of making it difficult to see a point defect in a liquid crystal display portion in a liquid crystal display device. Another object of the present invention is to provide a technique capable of reducing a point defect in which a pixel of a liquid crystal display section becomes defective and reducing black unevenness of the liquid crystal display section in a liquid crystal display device. Another object of the present invention is to achieve the above object, reduce the resistance value of a scanning signal line, and reduce point defects caused by a short circuit between a pixel electrode of a pixel and the scanning signal line in a liquid crystal display device. Is to provide a possible technology. Another object of the present invention is to reduce the black unevenness,
It is an object of the present invention to provide a technique capable of preventing disconnection of an electrode of a storage capacitor element for reducing the black unevenness. It is another object of the present invention to provide a technique capable of reducing the black unevenness with a simple configuration in a liquid crystal display device. It is another object of the present invention to provide a technique capable of reducing a DC component applied to liquid crystal of a liquid crystal display unit in a liquid crystal display device, thereby reducing the black unevenness. The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings. [Means for Solving the Problems] According to Embodiment III of the present invention shown in FIG.
Light shielding films 1 and 2 are provided so as to fill the gap between TO1 and ITO3. According to Embodiment IV of the present invention shown in FIG. 1B, the light-shielding film
3 and 4 are electrically connected to the adjacent scanning line GL. [Operation] According to Embodiment III, the problem that light from a backlight or the like leaks through a gap between pixel electrodes is almost eliminated. According to Embodiment VI, a capacitor can be equivalently formed between the light shielding films 3 and 4 (adjacent scanning lines GL) and each divided pixel electrode. Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to an active matrix type color liquid crystal display device. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted. The embodiments of the prior application (Japanese Patent Application No. 62-309601) are described in (Example I) and (Example II) with reference to FIGS. Example III) and Example I
V) will be described later with reference to FIGS. 1A and 1B. [Example] (Example I) One pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device according to Example I of the present invention is shown in FIG. A cross section taken along the line II-II is shown in FIG. 2B. FIG. 3 (a plan view of a main part) shows a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 2A are arranged. As shown in FIG. 2A to FIG. 3, in the liquid crystal display device, a pixel having a thin film transistor TFT and a transparent pixel electrode ITO is formed on a surface inside (liquid crystal side) of a lower transparent glass substrate SUB1. The lower transparent glass substrate SUB1 is, for example,
It has a thickness of about 1.1 [mm]. Each pixel is located within an intersection area (4 lines) between two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines) DL. (In the area surrounded by the signal lines of FIG. 3). As shown in FIGS. 2A and 3, a plurality of scanning signal lines GL extend in the column direction and are arranged in the row direction. Video signal line DL
Extend in the row direction and are arranged in the column direction. The thin film transistor TFT of each pixel has 3
And a plurality of thin film transistors (divided thin film transistors) TFT1, TFT2 and TFT3. Each of the thin film transistors TFT1 to TFT3 has substantially the same size (the same channel length and width). Each of the divided thin film transistors TFT1 to TFT3 mainly includes a gate electrode GT, an insulating film GI, and an i-type (intrinsic, intrinsic)
c, non-doped conductivity type determining impurities) amorphous Si
Semiconductor layer AS, a pair of source electrode SD1 and drain electrode SD2
It is composed of It should be understood that the source and the drain are originally determined by the bias polarity between them, and the polarity of the circuit of the present display device is inverted during the operation, so that the source and the drain are switched during the operation. However, also in the following description, for convenience, one is fixed as a source and the other is fixed as a drain. As shown in detail in FIG. 4 (a plan view of a main part in a predetermined manufacturing process), the gate electrode GT projects from the scanning signal line GL in the row direction (downward in FIGS. 2A and 4). It is configured in a T-shape (branched into a T-shape). That is, the gate electrode GT is configured to extend substantially parallel to the video signal line DL. Gate electrode GT
Are configured to protrude to respective formation regions of the thin film transistors TFT1 to TFT3. Thin film transistor TFT1
To TFT3 are integrally formed (as a common gate electrode) and are formed continuously on the same scanning signal line GL. The gate electrode GT is formed of a single-layer first conductive film g1 so that a large step is not formed as much as possible in the formation region of the thin film transistor TFT. First conductive film
g1 is formed with a film thickness of about 1000 [Å] using, for example, a chromium (Cr) film formed by sputtering. As shown in FIGS. 2A, 2B, and 5, this gate electrode GT is formed larger than that so as to completely cover the semiconductor layer AS (as viewed from below). Therefore, the substrate
When a backlight such as a fluorescent lamp is attached below SUB1,
This opaque Cr gate electrode GT becomes a shadow, and the semiconductor layer AS
Is not irradiated with the backlight, and the above-described conduction phenomenon due to the light irradiation, that is, the deterioration of the TFT off characteristics is less likely to occur. Note that the original size of the gate electrode GT has a minimum width (including a margin for the alignment between the gate electrode and the source / drain electrode) extending across the source / drain electrodes SD1 and SD2, and a channel width. The depth length that determines W is the distance (channel length) L between the source and drain electrodes.
, The factor that determines the transconductance gm
It is determined by the number of W / L. The size of the gate electrode in this embodiment is, of course, larger than the original size described above. Considering only the gate electrode GT and the light shielding function, the gate electrode and its wiring GL may be integrally formed in a single layer, in this case, Al containing Si as an opaque conductive material, pure Al or Pd-containing Al can be selected. The scanning signal line GL is formed of a composite film including a first conductive film g1 and a second conductive film g2 provided thereon. The first conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is integrally formed. The second conductive film g2 is, for example, an aluminum (Al) film formed by sputtering,
It is formed with a thickness of about 00 [Å]. The second conductive film g2 is configured to reduce the resistance value of the scanning signal line GL and increase the signal transmission speed (write characteristics of pixel information). Further, the scanning signal line GL is configured such that the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL can be formed so that the step shape of the side wall thereof is gentle, so that the surface of the upper insulating film GI can be flattened. The insulating film GI is used as each gate insulating film of the thin film transistors TFT1 to TFT3. The insulating film GI is the gate electrode
It is formed above the GT and the scanning signal line GL. Insulating film GI
Is formed, for example, using a silicon nitride film formed by plasma CVD and having a thickness of about 3000 [Å]. As aforementioned,
The surface of the insulating film GI is flattened in a region where each of the thin film transistors TFT1 to TFT3 is formed and a region where the scanning signal line GL is formed. The i-type semiconductor layer AS is used as a channel forming region of each of the plurality of divided thin film transistors TFT1 to TFT3 as shown in detail in FIG. 5 (a plan view of a main part in a predetermined manufacturing process). Thin-film transistor TF divided into multiple
Each of the i-type semiconductor layers AS of T1 to TFT3 is integrally formed in the pixel. That is, each of the plurality of thin film transistors TFT1 to TFT3 in which the pixel is divided is formed of one (common) island region of the i-type semiconductor layer AS. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of about 1800 [Å]. This i-type semiconductor layer AS is made of Si ₃ N
_{Fourth, following} the formation of the gate insulating film GI, the gate insulating film GI is formed in the same plasma CVD apparatus without being exposed to the outside from the apparatus. Similarly, a P-doped N ⁺ layer for ohmic contact and d0 (FIG. 2B) are similarly formed to a thickness of about 400 [Å] continuously. Thereafter, the substrate SUB1 is taken out of the CVD apparatus, and the N ⁺ layer d0 and the i layer
AS is patterned into independent islands as shown in FIGS. 2A, 2B and 5. As described above, by integrally configuring the respective i-type semiconductor layers AS of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels, the drain electrode SD2 common to each of the thin-film transistors TFT1 to TFT3 forms the i-type semiconductor layer AS ( In fact, the first
A step corresponding to the sum of the thickness of the conductive film g1, the thickness of the N ⁺ type semiconductor layer d0, and the thickness of the i-type semiconductor layer AS) from the drain electrode SD2 side to the i-type semiconductor layer AS side. Only once, the probability of disconnection of the drain electrode SD2 decreases, and the probability of occurrence of point defects can be reduced. That is, in the embodiment I, the point defect generated in the pixel when the drain electrode SD2 gets over the step of the i-type semiconductor layer AS can be reduced to one third. Although different from the layout of the embodiment I, when the video signal line DL directly goes over the i-type semiconductor layer AS, and the video signal line DL in the portion where the video signal line DL goes over is formed as the drain electrode SD2, the video signal line DL (drain) It is possible to reduce the probability of occurrence of line defects due to disconnection when the electrode SD2) gets over the i-type semiconductor layer AS. That is, by integrally forming the respective i-type semiconductor layers AS of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels, the video signal line DL (drain electrode SD2) passes over the i-type semiconductor layer AS only once. There is no such thing (actually, twice at the start and end of the ride). As shown in detail in FIGS. 2A and 5, the i-type semiconductor layer AS is provided so as to extend between both intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. ing. The extended i-type semiconductor layer AS is configured to reduce a short circuit between the scanning signal line GL and the video signal line DL at the intersection. Thin-film transistor TFT1 to TFT3 divided into multiple pixels
The source electrode SD1 and the drain electrode SD2 of the
As shown in detail in FIG. 2, FIG. 2B, and FIG. 6 (a plan view of a main part in a predetermined manufacturing process), they are separately provided on the i-type semiconductor layer AS. Source electrode SD1, drain electrode S
Each of D2 is configured so that, when the bias polarity of the circuit changes, the source and the drain are switched in operation. That is, the thin film transistor TFT is bidirectional, like the FET. Each of the source electrode SD1 and the drain electrode SD2 is configured by sequentially stacking a second conductive film d1, a second conductive film d2, and a third conductive film d3 from the lower side in contact with the N ⁺ type semiconductor layer d0. . The first conductive film d1, the second conductive film d2, and the third conductive film d3 of the source electrode SD1 are formed in the same manufacturing process as each of the drain electrode SD2. The first conductive film d1 uses a chromium film formed by sputtering and has a thickness of 500 to 1000 [Å] (in this embodiment, 600 [Å]).
(About the same thickness). The chromium film is formed in a range that does not exceed about 2000 [Å] because the stress increases when the chromium film is formed thick. The chromium film has good contact with the N ⁺ type semiconductor layer d0. The chromium film is formed by a second
It forms a so-called barrier layer that prevents aluminum of the conductive film d2 from diffusing into the N ⁺ type semiconductor layer d0. First conductive film d1
In addition to chromium film, refractory metals (Mo, Ti, Ta, W)
Film, refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ )
It may be formed of a film. After patterning the first conductive film d1 by photo processing, the same photo processing mask or N ⁺
Layer d0 is removed. That is, the N ⁺ layer remaining on the i-layer AS
As for d0, portions other than the first conductive film d1 are removed by self-alignment. At this time, since the N ⁺ layer d0 is etched so as to completely remove its thickness, the i layer AS is also slightly etched at its surface, but the degree may be controlled by the etching time. Thereafter, the second conductive film d2 is formed to a thickness of 3000 to 4000 [Å] by sputtering of aluminum (in this embodiment, 3000 to 4000 [Å]).
[Å]. The aluminum film is
The stress is smaller than that of the chromium film, it can be formed in a thick film, and the resistance value of the source electrode SD1, the drain electrode SD2 and the video signal line DL is reduced. The second conductive film d2 is configured to increase the operation speed of the thin film transistor TFT and increase the signal transmission speed of the video signal line DL. That is, the second
The conductive film d2 can improve the writing characteristics of the pixel.
The second conductive film d2 may be formed of an aluminum film containing silicon (Si) or copper (Cu) as an additive, in addition to the aluminum film. After patterning the second conductive film d2 by a photoprocessing technique, a third conductive film d3 is formed by a transparent conductive film (ITO:
The film is formed to a thickness of 1000 to 2000 [Å] (in this embodiment, about 1200 [の]). The third conductive film d3 forms the source electrode SD1, the drain electrode SD2, and the video signal line DL, and also forms the transparent pixel electrode ITO. Each of the first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 has a larger size on the channel forming region side than the upper second conductive film d2 and the third conductive film d3. I have. That is, even if a mask misalignment occurs in the manufacturing process between the first conductive film d1 and the second conductive film d2 and the third conductive film d3, the first conductive film d2 and the third conductive film Larger size than the film d3 (the first conductive film d1 to the third conductive film
Each of the channel forming regions d3 may be on the line). Each of the first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 is configured to define the gate length L of the thin film transistor TFT. As described above, in the thin film transistors TFT1 to TFT3 divided into a plurality of pixels, the source electrode SD1 and the drain electrode S
By configuring the channel forming region side of each first conductive film d1 of D2 with a size larger than the second conductive film d2 and the third conductive film d3, the first conductive film d1 of each of the source electrode SD1 and the drain electrode SD2 is formed. The dimension between the films d1 can define the gate length L of the thin film transistor TFT. Since the separation dimension (gate length L) between the first conductive films d1 can be defined by processing accuracy (patterning accuracy), the thin film transistor TF
The gate length L of each of T1 to TFT3 can be made uniform. The source electrode SD1 is connected to the transparent pixel electrode ITO as described above. The source electrode SD1 has a step shape of the i-type semiconductor layer AS (a step corresponding to a thickness obtained by adding the thickness of the first conductive film g1, the thickness of the N ⁺ layer d0, and the thickness of the i-type semiconductor layer AS). It is configured along. Specifically, the source electrode SD1
Represents a first portion formed along the step shape of the i-type semiconductor layer AS.
A conductive film d1, a second conductive film d2 formed on the upper side of the first conductive film d1 and connected to the transparent pixel electrode ITO with a smaller size, and a first conductive film exposed from the second conductive film. And a third conductive film d3 connected to the film d1.
The first conductive film d1 of the source electrode SD1 has good adhesion to the N ⁺ -type semiconductor layer d0, and is mainly configured as a barrier layer against diffusion from the second conductive film d2. Since the second conductive film d2 of the source electrode SD1 cannot form a thick chrome film of the first conductive film d1 due to an increase in stress and cannot overcome the step of the i-type semiconductor layer AS, the second conductive film d2 is It is configured to get over. That is, the second conductive film
d2 improves the step coverage by being formed thick. Since the second conductive film d2 can be formed thick, it greatly contributes to a reduction in the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL). Third conductive film
Since d3 cannot get over the stepped shape caused by the i-type semiconductor layer AS of the second conductive film d2, the d3 is connected to the exposed first conductive film d1 by reducing the size of the second conductive film d2. It is configured. First conductive film d1 and third conductive film d3
In addition to the fact that the adhesiveness is good, the connection between the two has a small step, so that the connection can be surely made. Thus, the source electrode SD1 of the thin film transistor TFT
At least a first conductive film d1 as a barrier layer formed along the i-type semiconductor layer AS and a specific resistance value higher than the first conductive film formed on the first conductive film d1. A second conductive film that is small and smaller in size than the first conductive film
The thin film transistor TFT is connected to the transparent pixel electrode ITO by connecting the third conductive film d3 which is a transparent pixel electrode ITO to the first conductive film d1 exposed from the second conductive film d2. Therefore, point defects due to disconnection can be reduced. Moreover, the source electrode SD1
Since the second conductive film d2 (aluminum film) having a small resistance value can be used due to the barrier effect of the first conductive film d1, the resistance value can be reduced. The drain electrode SD2 is formed integrally with the video signal line DL, and is formed in the same manufacturing process. Drain electrode
SD2 is formed in an L-shape protruding in the column direction intersecting with the video signal line DL. That is, each of the drain electrodes SD of the thin film transistors TFT1 to TFT3 divided into a plurality of pixels
2 are connected to the same video signal line DL. The transparent pixel electrode ITO is provided for each pixel, and constitutes one of the pixel electrodes of the liquid crystal display unit. The transparent pixel electrode ITO is a thin film transistor T divided into a plurality of pixels.
Each of FT1 to TFT3 is divided into three transparent pixel electrodes (divided transparent pixel electrodes) ITO1, ITO2, and ITO3.
The transparent pixel electrode ITO1 is connected to the source electrode SD1 of the thin film transistor TFT1. The transparent pixel electrode ITO2 is connected to the source electrode SD1 of the thin film transistor TFT2. The transparent pixel electrode ITO3 is the source electrode of the thin film transistor TFT3
Connected to SD1. Each of the transparent pixel electrodes ITO1 to ITO3 is a thin film transistor
Like each of TFT1 to TFT3, they have substantially the same size. Each of the transparent pixel electrodes ITO1 to ITO3 is formed integrally with each of the i-type semiconductor layers AS of the thin film transistors TFT1 to TAT3 (each of the divided thin film transistors TFT
Are concentrated in one place), so that it is configured in an L-shape. In this manner, the thin film transistor TFT of the pixel arranged in the intersection area between the two adjacent scanning signal lines GL and the two adjacent video signal lines DL is replaced with a plurality of thin film transistors TFT1 to TFT
FT3, and the thin-film transistor T
Transparent pixel electrodes ITO1 to I divided into multiples for each of FT1 to TFT3
By connecting each of TO3, only a part of the divided pixel (for example, TFT1) becomes a point defect and the whole pixel is not a point defect (TFT2 and TFT3 are not a point defect). Point defects can be reduced. In addition, the point defect of the divided part of the pixel is smaller than the entire area of the pixel (in the case of the present embodiment, 3% of the pixel).
(One-half the area), so that the point defect can be made difficult to see. Further, the transparent pixel electrodes ITO1 to ITO3 obtained by dividing the pixels.
Are made to have substantially the same size, the area of the point defect in the pixel can be made uniform. Further, the transparent pixel electrodes ITO1 to ITO3 obtained by dividing the pixels.
Are configured to have substantially the same size, so that each of the liquid crystal capacitors (Cpix) composed of each of the transparent pixel electrodes ITO1 to ITO3 and the common transparent pixel electrode ITO and the transparent pixel electrodes ITO1 to ITO3 Transparent pixel electrodes ITO1 to
The overlapping capacitance (Cgs) generated by the overlapping of the ITO3 and the gate electrode GT can be made uniform. That is, since each of the transparent pixel electrodes ITO1 to ITO3 can make the liquid crystal capacitance and the overlap capacitance uniform, the DC component to be applied to the liquid crystal molecules of the liquid crystal LC caused by the overlap capacitance is made uniform. When the method of canceling out the direct current component is adopted, the variation of the direct current component applied to the liquid crystal of each pixel can be reduced. On the thin film transistor TFT and the transparent pixel electrode ITO, a protective film PSV1 is provided. The protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a thickness of about 8000 [Å]. On top of the protective film PSV1 on the thin film transistor TFT, an i-type semiconductor layer where external light is used as a channel formation region
A shielding film LS is provided so as not to be incident on the AS.
As shown in FIG. 2A, the shielding film LS is configured in a region surrounded by a dotted line. The shielding film LS is formed of, for example, an aluminum film, a chromium film, or the like having a high light shielding property, and is formed to a thickness of about 1000 [Å] by sputtering. Accordingly, the common semiconductor layers AS of the TFTs 1 to 3 are sandwiched by the upper and lower light shielding films LS and the large gate electrodes GT, so that external natural light or backlight does not shine. The light-shielding film LS and the gate electrode GT are larger than the semiconductor layer AS and are substantially similar to the semiconductor layer AS, and have substantially the same size (in the figure, GT is drawn smaller than LS so that the boundary line can be seen). . Note that the backlight can be attached to the SUB2 side, and the SUB1 can be the observation side (exposed side).
LS functions as a backlight for the backlight, and the gate electrode GT functions as a light shield for natural light. The thin film transistor TFT is configured such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases. That is, the thin film transistor TFT is configured to control the voltage applied to the transparent pixel electrode ITO. The liquid crystal LC is defined and enclosed in a lower alignment film ORI1 and an upper alignment film ORI2 for setting the direction of liquid crystal molecules in a space formed between the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2. . The lower alignment film ORI1 is formed above the protective film PSV1 on the lower transparent glass substrate SUB1 side. On the inner (liquid crystal side) surface of the upper transparent glass substrate SUB2, a color filter FIL, a protective film PSV2, a common transparent pixel electrode (COM) ITO, and the upper alignment film ORI2 are sequentially laminated. The common transparent pixel electrode ITO has a lower transparent glass substrate SUB
One side faces the transparent pixel electrode ITO provided for each pixel, and is configured integrally with another adjacent common transparent pixel electrode ITO. The common transparent pixel electrode ITO is configured to be applied with a common voltage Vcom. The common voltage Vcom is
Low-level drive voltage Vdmin applied to video signal line DL
And a high-level drive voltage Vdmax. The color filter FIL is configured by coloring a dye on a dyed base material formed of a resin material such as an acrylic resin.
The color filter FIL is configured for each pixel at a position facing the pixel and is dyed separately. That is, the color filter FIL is configured in an intersection area between two adjacent scanning signal lines GL and two adjacent video signal lines DL, similarly to the pixel. Each pixel is divided into a plurality of parts in each predetermined color filter of the color filter FIL. The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, by performing similar steps, a green filter G and a blue filter B are sequentially formed. As described above, by forming each color filter of the color filter FIL in the intersection area facing each pixel, the scanning signal lines GL,
Since each of the video signal lines DL is present, a margin for alignment between each pixel and each color filter of the color filter FIL can be secured (enlargement of the alignment margin) corresponding to the existence of each of the video signal lines DL. Furthermore, color filter FI
When forming each color filter of L, it is possible to secure a margin for alignment between different color filters. That is, in this embodiment, two adjacent scanning signal lines are used.
A pixel is formed in an intersection area between the GL and two adjacent video signal lines DL, the pixel is divided into a plurality of pixels, and each color filter of the color filter FIL is formed at a position facing the pixel. Point defects can be reduced, and the alignment margin between each pixel and each color filter can be secured. The protective film PSV2 is provided in order to prevent the dye obtained by dyeing the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin. In this liquid crystal display device, the respective layers on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side are separately formed, then the upper and lower transparent glass substrates SUB1 and SUB2 are overlapped, and the liquid crystal LC is sealed between the two. Assembled by As shown in FIG. 3, a plurality of pixels of the liquid crystal display unit are arranged in the same column direction as the direction in which the scanning signal lines GL extend, and pixel columns X ₁ , X ₂ , X ₃ , X ₄ ,. Each of which constitutes. Each pixel of each pixel row X ₁ , X ₂ , X ₃ , X ₄ ,.
The arrangement positions of TFT1 to TFT3 and transparent pixel electrodes ITO1 to ITO3 are the same. In other words, the respective pixels of the pixel rows X ₁ , X ₃ ,...
The arrangement positions of the transparent pixel electrodes ITO1 to ITO3 are configured on the right side. The next row of pixel columns X ₂ , X in the row direction of the pixel columns X ₁ , X ₃ ,.
Each of the pixels ₄ ,... Is constituted by a pixel in which each pixel of a pixel column X ₁ , X ₃ ,. That is, each pixel in the pixel rows X ₂ , X ₄ ,.
The arrangement positions of the thin film transistors TFT1 to TFT3 are on the right side, and the arrangement positions of the transparent pixel electrodes ITO1 to ITO3 are on the left side. The respective pixels in the pixel rows X ₂ , X ₄ ,... Correspond to the pixel rows X ₁ , X ₃ ,.
Are shifted (shifted) by a half pixel interval in the column direction with respect to each of the pixels. That is, assuming that each pixel interval of the pixel row X is 1.0 (1.0 pitch), the pixel row X in the next stage is
Has a pixel interval of 1.0, and is shifted by 0.5 pixel interval (0.5 pitch) in the column direction with respect to the preceding pixel column X. The video signal lines DL extending in the row direction between the pixels are configured to extend in the column direction by half pixel intervals (0.5 pitch) between the pixel columns X. Thus, in the liquid crystal display unit, the thin film transistor
A pixel row X is formed by arranging a plurality of pixels having the same arrangement position of the TFT and the transparent pixel electrode ITO in the column direction, and a pixel row X in the next stage of the pixel row X and a pixel in the pixel row X in the preceding row are image signals. FIG. 7 (Pixel and color filter are overlapped) by using pixels arranged in line symmetry with respect to line DL, and by moving the next pixel row by a half pixel interval with respect to the previous pixel row. As shown in the main part plan view in the combined state), the pixels (for example, the pixel columns X) on which the predetermined color filter of the previous pixel column X is formed
Pixels to which the same color filters are formed of X ₃ of the red filter R is formed of pixels) and next pixel column X (e.g., the pixel row
X ₄ of the red filter R is formed of pixels) can be spaced 1.5 pixel interval (1.5 pitch). That is, the pixels of the preceding pixel row X are configured to be always separated by 1.5 pixels at intervals from the pixels of the next nearest pixel row on which the same color filter is formed, and the color filter FIL is RGB.
Can be configured. The RGB triangular arrangement structure of the color filter FIL can improve the color mixture of each color, so that the resolution of a color image can be improved. In addition, since the video signal lines DL extend in the column direction only by half pixel intervals between the pixel columns X, they do not cross adjacent video signal lines DL. Therefore, it is possible to eliminate the routing of the video signal line DL and reduce the occupied area thereof,
In addition, the bypass of the video signal line DL can be eliminated, and the multilayer wiring structure can be eliminated. FIG. 9 (equivalent circuit diagram of the liquid crystal display) shows a circuit configuration of the liquid crystal display. XiG, Xi + 1G,... Shown in FIG. 9 are video signal lines DL connected to the pixels on which the green filter G is formed. XiB, Xi + 1B, ...
Is a video signal line DL connected to the pixel on which the blue filter B is formed. Xi + 1R, Xi + 2R, ... are red filters R
Are the video signal lines DL connected to the pixels where are formed. These video signal lines DL are selected by a video signal drive circuit. Yi is a scanning signal line GL for selecting the pixel column X ₁ shown in the FIGS. 3 and 7 FIG. Similarly, Yi + 1, Yi + 2 , ... Each of the, a scanning signal line GL for selecting the pixel column X _2, X _3, ..., respectively of. These scanning signal lines GL are connected to a vertical scanning circuit. The center part of FIG. 2B shows a cross section of one pixel portion, while the left side shows a cross section of a left edge portion of the transparent glass substrates SUB1 and SUB2 where external lead-out wiring exists. The right side shows a cross section of a portion on the right side edge of the transparent glass substrates SUB1 and SUB2 where there is no external lead-out wiring. The sealing material SL shown on the left and right sides of FIG.
It is configured to seal the LC, and is formed along the entire periphery of the transparent glass substrates SUB1 and SUB2 except for the liquid crystal sealing port (not shown). The sealing material SL is formed of, for example, an epoxy resin. The common transparent pixel electrode IT on the upper transparent glass substrate SUB2 side
O is connected to the external lead-out wiring formed on the lower transparent glass substrate SUB1 side by the silver paste material SIL at least at one place. This external lead-out wiring is formed in the same manufacturing process as the above-described gate electrode GT, source electrode SD1, and drain electrode SD2. The respective layers of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO, the common transparent pixel electrode ITO, the protective films PSV1 and PSV2, and the insulating film GI are formed inside the sealing material SL. Polarizer POL
Is the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2
Are formed on the respective outer surfaces. Example II In Example II, the aperture ratio of each pixel of the liquid crystal display unit of the liquid crystal display device was improved, the DC component applied to the liquid crystal was reduced, the point defects of the liquid crystal display unit were reduced, and 14 is another embodiment of the present invention in which unevenness is reduced. One pixel of the liquid crystal display portion of the liquid crystal display device according to the embodiment II of the present invention is shown in FIG. 8A (plan view of a main part), and a portion (TFT3) surrounded by a thick solid line frame B shown at the lower left of FIG. FIG. 8 shows an enlarged view of (and its surroundings) three times. As shown in FIGS. 8A and 8B, the liquid crystal display device of Example II is configured such that the i-type semiconductor layer AS in each pixel of the liquid crystal display portion is divided for each of the thin film transistors TFT1 to TFT3. That is, the thin film transistors TFT1 to TFT1 to
Each of the TFTs 3 is constituted by an island region of an independent i-type semiconductor layer AS. In the pixel configured in this manner, each of the thin film transistors TFT1 to TFT3 can be uniformly distributed and arranged in the row direction in which the video signal line DL extends.
Transparent pixel electrodes ITO1 to ITO3 connected to each of TFT1 to TFT3
Can be configured in a square shape. Each of the rectangular transparent pixel electrodes ITO1 to ITO3 reduces the separation area in the row direction between adjacent transparent pixel electrodes ITO in the pixel (the area corresponding to the hatched area in FIG. 2A). Area (aperture ratio)
Can be improved. In addition, as shown in FIG. 8 by attaching a symbol A and encircling a dotted line, when changing the shape of each of the transparent pixel electrodes ITO1 to ITO3, the angle of inclination with respect to the scanning signal line GL or the video signal line DL is changed. (For example, a line at an angle of 45 degrees). That is, each of the transparent pixel electrodes ITO1 to ITO3 has a smaller separation area between the transparent pixel electrodes ITO than when the shape is changed by a line parallel to or orthogonal to the scanning signal line GL or the video signal line DL. Since it can be reduced, the aperture ratio can be improved. Further, each of the transparent pixel electrodes ITO1 to ITO3 is overlapped with the next-stage scanning signal line GL in the row direction on the side opposite to the side connected to the thin film transistor TFT. This superposition is performed, as in the case of the gate electrodes GT of the thin film transistors TFT1 to TFT3, by connecting the scanning signal line DL for selecting the gate electrode GT (scanning signal line DL for selecting a pixel) and the next scanning signal line DL adjacent thereto. It is performed by branching into a character shape. The branched scanning signal line GL is a thin film transistor TFT
Like the gate electrode GT, the first conductive film (chromium film) g1 has a single layer. The superposition is a transparent pixel electrode
Each of ITO1 to ITO3 is used as one electrode, and the next stage scanning signal line
A storage capacitance element (capacitance element) Cadd is formed using GL as a capacitance electrode line and using a portion branched therefrom as the other electrode. The dielectric film of the storage capacitor Cadd is an insulating film G used as a gate insulating film of the thin film transistor TFT.
It is composed of the same layer as I. The gate electrode GT is formed larger than the semiconductor layer AS as in the embodiment I. However, in this embodiment, since the TFTs 1 to 3 are formed for each independent semiconductor layer AS, a larger pattern is provided for each TFT. Formed and branched gate wiring GL
(G1). Another layout of the storage capacitor Cadd is shown in FIG. 10 (a plan view of a main part showing another example of a pixel), and an equivalent circuit of the pixel shown in FIGS. 8 and 10 is shown in FIG. (Equivalent circuit diagram). The storage capacitor Cadd of the pixel shown in FIG.
Increases the amount of overlap between each of the transparent pixel electrodes ITO1 to ITO3 and the branched portion of the capacitor electrode line (the other electrode of the storage capacitor Cadd), thereby increasing the storage capacitance. Basically, the storage capacitor Cadd shown in FIG. 10 is the same as the storage capacitor Cadd shown in FIG. In FIG. 11,
As before, Cgs is the gate electrode of the thin film transistor TFT
This is a superposition capacitance formed by GT and the source electrode SD1. The dielectric film of the overlap capacitance Cgs is the insulating film GI. Cpi
x is transparent pixel electrode ITO (PIX) and common transparent pixel electrode ITO
This is the liquid crystal capacitance formed between (COM). LCD capacitance Cpix
Are the liquid crystal LC, the protective film PSV1, and the alignment films ORI1, 2. Vlc is the midpoint potential. The holding capacitance element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the TFT switches. This state is represented by the following equation: ΔVlc = {(Cgs / (Cgs + Cadd + Cpix)} × ΔVg, where ΔVlc represents a change in the midpoint potential due to ΔVg. However, as the storage capacitance Cadd is increased, the value can be reduced, and the storage capacitance Cadd also has an effect of increasing the discharge time, and accumulates long image information after the TFT is turned off. The reduction of the DC component applied to the LC improves the life of the liquid crystal LC and can reduce the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched, as described in the first embodiment. GT is the semiconductor layer AS
, The overlap area with the source / drain electrodes SD1 and SD2 increases, so that the parasitic capacitance Cgs increases and the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. The opposite effect occurs. However, this disadvantage can be eliminated by providing the storage capacitor Cadd. In a liquid crystal display device having a pixel in an intersection area between two scanning signal lines GL and two video signal lines DL, one of the two scanning signal lines GL is selected by one of the two scanning signal lines GL. The thin-film transistor TFT of the pixel to be divided into a plurality of pixels, and each of the divided thin-film transistors TFT1 to TFT3 is connected to a plurality of divided transparent pixel electrodes ITO (ITO1 to ITO3). Each of the pixel electrodes ITO to ITO3 constitutes a storage capacitance element Cadd which uses the pixel electrode ITO as one electrode and uses the other of the two scanning signal lines DL as a capacitance electrode line and the other electrode. As a result, as described above, since only a part of the divided pixel becomes a point defect and the pixel is not a point defect as a whole, the point defect of the pixel can be reduced, and the storage capacitor Cadd can be reduced. Direct current added to liquid crystal LC Since the amount can be reduced, the life of the liquid crystal LC can be improved. In particular, by dividing the pixels, it is possible to reduce point defects caused by a short circuit between the gate electrode GT of the thin film transistor TFT and the source electrode SD1 or the drain electrode SD2, and to reduce the storage capacitance of each of the transparent pixel electrodes ITO1 to ITO3. Point defects caused by a short circuit with the other electrode (capacitor electrode line) of the element Cadd can be reduced. The point defect on the latter side is reduced to one third in this embodiment. As a result, some of the divided point defects of the pixel are smaller than the entire area of the pixel, so that it is difficult to see the point defect. The storage capacitance of the storage capacitance element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4 · Cpix <Cadd) due to the writing characteristics of the pixel.
<8 · Cpix), 8 to 32 times (8
・ Set to a value of about Cgs <Cadd <32 · Cgs). Further, the scanning signal line GL is connected to a first conductive film (chrome film) g1.
And a second conductive film (aluminum film) g2 is superposed on the composite film, and the other electrode of the storage capacitor Cadd, that is, the branched portion of the capacitor electrode line is connected to the first conductive film of one layer of the composite film. With the single-layer film composed of the film g1, the resistance value of the scanning signal line GL can be reduced, the writing characteristics can be improved, and along the step portion based on the other electrode of the storage capacitor Cadd. Since one electrode (transparent pixel electrode ITO) of the storage capacitor Cadd can be securely bonded onto the insulating film GI, disconnection of one electrode of the storage capacitor Cadd can be reduced. Further, the other electrode of the storage capacitor Cadd is formed of the single-layer first conductive film g1 and the second conductive film g2 of the aluminum film is not formed, so that the other electrode of the storage capacitor Cadd due to the hillock of the aluminum film is formed. A short circuit between the electrode and one of the electrodes can be prevented. A part between each of the transparent pixel electrodes ITO1 to ITO3 and the branched part of the capacitor electrode line, which are overlapped to constitute the storage capacitor Cadd, is branched in the same manner as the source electrode SD1. The first conductive film d1 and the second conductive film d1 are used to prevent disconnection of the transparent pixel electrode ITO when the vehicle passes over the stepped portion.
An island region composed of the conductive film d2 is provided. This island region is configured as small as possible so as not to reduce the area (opening ratio) of the transparent pixel electrode ITO. As described above, the first conductive film d1 is located between one electrode of the storage capacitor Cadd and the insulating film GI used as a dielectric film thereof, as compared with the first conductive film d1 formed thereon. An underlayer formed of the second conductive film d2 having a small specific resistance and a small size constitutes an underlayer, and the one electrode (the third conductive film d2) is formed.
3) is connected to the first conductive film d1 exposed from the second conductive film d2 of the underlying layer, thereby ensuring one of the storage capacitor elements Cadd along a step portion based on the other electrode of the storage capacitor element Cadd. Since the electrodes can be bonded, disconnection of one electrode of the storage capacitor Cadd can be reduced. The liquid crystal display of the liquid crystal display device in which the storage capacitor Cadd is provided on the transparent pixel electrode ITO of the pixel is configured as shown in FIG. 13 (an equivalent circuit diagram showing the liquid crystal display). The liquid crystal display unit is configured by repeating a unit basic pattern including pixels, scanning signal lines GL, and video signal lines DL. The final scanning signal line GL (or the first scanning signal line GL) used as the capacitor electrode line is connected to the common transparent pixel electrode (Vcom) ITO as shown in FIG. The common transparent pixel electrode ITO is
As shown in FIG. 2B, the periphery of the liquid crystal display device is connected to an external lead-out line by a silver paste material SL. In addition, some of the conductive layers (g1 and
g2) is formed in the same manufacturing process as the scanning signal line GL.
As a result, the last-stage scanning signal line GL (capacitance electrode line) can be easily connected to the common transparent pixel electrode ITO. As described above, by connecting the last stage of the capacitor electrode line to the common transparent pixel electrode (Vcom) ITO of the pixel, the last stage capacitor electrode line is integrally formed with a part of the conductive layer of the external lead-out wiring. In addition, since the common transparent pixel electrode ITO is connected to the external lead-out line, the last stage capacitor electrode line can be connected to the common transparent pixel electrode ITO with a simple configuration. In addition, the liquid crystal display device employs a direct current canceling method (D / A) described in Japanese Patent Application No. 62-95125 previously filed by the present applicant.
As shown in FIG. 12 (time chart) based on the C cancellation method, the DC component applied to the liquid crystal LC can be further reduced by controlling the drive voltage of the scanning signal line DL. In FIG. 12, Vi is an arbitrary scanning signal line
The driving voltage of GL, Vi + 1, is the driving voltage of the next-stage scanning signal line GL. Vee is a low-level driving voltage Vdmin applied to the scanning signal line GL, and Vdd is a high-level driving voltage Vdmax applied to the scanning signal line GL. The voltage change ΔV ₁ to the midpoint potential Vlc (see FIG. 11) at each time t = t _{1 to} t ₄
ΔV ₄ is as follows. t = t ₁ : ΔV ₁ = − (Cgs / C) · V2 t = t ₂ : ΔV ₂ = + (Cgs / C) · (V1 + V2) − (Cadd / C) ·
V2 t = t ₃ : ΔV ₃ = − (Cgs / C) · V1 + (Cadd / C) · (V1 + V
2) t = t ₄ : ΔV ₄ = − (Cadd / C) · V1, where total capacitance of the pixels: C = Cgs + Cpix + Cadd Here, if the drive voltage applied to the scanning signal line GL is sufficient (described below)

Note: The DC voltage applied to the liquid crystal LC is ΔV ₃ + ΔV ₄ = (Cadd · V2−Cgs · V1) / C. Therefore, if Cadd · V2 = Cgs · V1 = 0, the liquid crystal LC
Is zero.

〔The invention's effect〕

As described above, according to the embodiment of the present invention, in the case where no measures are taken, light leaking from the gap between the divided pixels is
Since the light is shielded by the light-shielding film provided therebetween, the contrast is improved.

[Brief description of the drawings]

FIGS. 2A to 14 show Japanese Patent Application No. Sho 62, which was previously proposed by the present applicant.
FIG. 1A and FIG.
FIG. 1B is a diagram showing an embodiment in which the embodiment is improved, and each diagram is as follows. FIG. 1A is a plan view of an essential part showing one pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device which is Embodiment III of the present invention. FIG. 1B is an active matrix type which is Embodiment IV of the present invention. FIG. 2A is a plan view of a principal part showing one pixel of a liquid crystal display portion of a matrix type color liquid crystal display device. FIG. FIG. 2B is a cross-sectional view of a portion cut along the II-II cutting line in FIG. 2A and a peripheral portion of the seal portion, and FIG. 3 is a plurality of pixels shown in FIG. 2A. FIGS. 4 to 6 are plan views of main parts in a predetermined manufacturing process of the pixel shown in FIG. 2A. FIG. 7 is a plan view of the main part of the pixel shown in FIG. FIG. 8A is a plan view of a main part in a state where the color filter and the color filter are superimposed. FIG. 8B is a partial plan view showing one pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device which is Embodiment II of the present invention, FIG. 8B is a partially enlarged view thereof, and FIG. FIG. 10 is an equivalent circuit diagram showing a liquid crystal display portion of an active matrix type color liquid crystal display device of each of Examples I and II. FIG. 10 is a plan view of a main part showing one pixel of a layout different from the pixel shown in FIG. FIG. 11, FIG. 11 is an equivalent circuit diagram of the pixel described in each of FIG. 8 and FIG. 10, FIG. 12 is a time chart showing a driving voltage of a scanning signal line by a DC cancellation method, FIG. FIG. 14 is an equivalent circuit diagram showing a liquid crystal display section of an active matrix type color liquid crystal display device according to Embodiment II of the present invention. In the figure, 1 to 4: light-shielding film between divided pixels, SUB: transparent glass substrate, GL: scanning signal line, DL: video signal line, GI
Insulating film, GT ... Gate electrode, AS ... i-type semiconductor layer, SD ...
... Source or drain electrode, PSV ... Protective film, LS ...
… Light shielding film, LC …… Liquid crystal, TFT …… Thin film transistor, ITO
(COM): transparent pixel electrode, g, d: conductive film, Cadd: storage capacitance element, Cgs: superimposed capacitance, Cpix: liquid crystal capacitance.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Katsuhiko Yarita, Inventor 3300 Hayano, Mobara-shi, Chiba In-house Mobara Plant, Hitachi, Ltd. Inside

Claims (2)

(57) [Claims] 1. An active matrix type liquid crystal display device comprising a plurality of unit pixels each having a thin film transistor and a transparent pixel electrode on an inner surface of a transparent glass substrate, wherein the unit pixels are arranged in two adjacent scanning signals. A unit pixel formed in a crossing area between a line and two adjacent video signal lines, wherein the unit pixel selected by one of the scanning signal lines and one of the video signal lines is divided into a plurality of thin film transistors A liquid crystal display device comprising a plurality of independent transparent pixel electrodes, each of which is provided with a light shielding film that fills a gap between the plurality of transparent pixel electrodes. 2. An active matrix type liquid crystal display device comprising a plurality of unit pixels each having a thin film transistor and a transparent pixel electrode on an inner surface of a transparent glass substrate, wherein the unit pixels are arranged in two adjacent scanning signals. A unit pixel formed in a crossing area between a line and two adjacent video signal lines, wherein the unit pixel selected by one of the scanning signal lines and one of the video signal lines is divided into a plurality of thin film transistors And a plurality of independent transparent pixel electrodes, each of which is filled with a gap between the plurality of transparent pixel electrodes, and a light shielding film electrically connected to the scanning signal line is arranged. Liquid crystal display device.