JP2786871B2 - Method for forming terminals of liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device such as an active matrix type color liquid crystal display device in which a thin film transistor and a pixel electrode are one component of a pixel. 2. Description of the Related Art In a conventional method of manufacturing an active matrix type liquid crystal display device, as shown in US Pat. No. 3,824,003, after forming an insulating film used as a gate insulating film, a drain is formed. Terminals are formed. A configuration in which the drain signal line is formed of aluminum and the drain terminal is formed of chromium is known from Japanese Patent Application Laid-Open No. 62-143028. A configuration in which a drain terminal is formed of a chromium film and a transparent conductive film covering the chromium film is known from Japanese Patent Application Laid-Open No. 62-35669. A prior art in which a gate terminal is formed of chromium and a gate signal line is formed of aluminum is disclosed in JP-A-1-287625. However, in any of the prior arts, the signal line is formed of a multilayer film of the first conductive film and the second conductive film, and the signal line of the multilayer film is completely covered with the insulating film, and the signal line of the multilayer film of the terminal portion is formed. Is exposed from the insulating film, and thereafter, the second conductive film of the multilayer wiring exposed from the insulating film is removed, and the first conductive film exposed from the insulating film and the second conductive film is removed.
There is no description of a structure in which a terminal is formed by forming a transparent conductive film over the conductive film. [Problems to be Solved by the Invention] However, in such a method for manufacturing a liquid crystal display device, after forming the uppermost layer of the terminal, an insulating film used as a protective film covering the thin film transistor and the signal line is formed. Therefore, the uppermost layer of the terminal may be contaminated by the formation of the insulating film used as the protective film, and the terminal may have a poor connection. In the case where an insulating film is formed between the step of forming the signal line and the step of forming the uppermost layer of the terminal, the surface of the conductive film forming the signal line is contaminated by the insulating film forming step. As a result, there is a possibility that the signal line and the terminal may cause a connection failure. The present invention has been made to solve the above-described problem, and has as its object to provide a method for forming a terminal of a liquid crystal display device in which a signal line and a terminal do not cause a connection failure. [Means for Solving the Problems] In order to achieve this object, in the present invention, a plurality of pixels are provided on one glass substrate of a liquid crystal display device to supply signals to the plurality of pixels. A signal line and a plurality of terminal portions to be terminals respectively connected to the plurality of signal lines are formed by a first conductive film and a second conductive film deposited on the first conductive film and selectively etchable with respect to the first conductive film. A step of forming a multilayer film with a conductive film; a step of forming an insulating film covering the plurality of signal lines and the plurality of terminal portions on the glass substrate; and removing the insulating film over the plurality of terminal portions Performing the step of removing the second conductive film exposed from the insulating film of the plurality of terminal portions; and removing the second conductive film of the plurality of terminal portions from the portion of the first conductive film from which the second conductive film is removed. Third conductive layer made of transparent conductive film A method for forming a terminal of a liquid crystal display device, comprising a step of forming a film. [Operation] In this method of forming the terminals of the liquid crystal display device, the first
At the same time as forming a signal line composed of a multilayer film of a conductive film and a second conductive film, forming a first conductive film and a second conductive film of a terminal, forming an insulating film covering the signal line, and then insulating the terminal portion. Since the film is removed and the second conductive film on the first conductive film exposed from the insulating film is removed, the surface of the first conductive film of the terminal is not contaminated by the insulating film forming step. Further, since the third conductive film of the terminal is formed after the formation of the insulating film covering the signal line, the terminal surface is not contaminated by the insulating film forming step. In addition, the third conductive film of the terminal is formed in a portion where the insulating film and the second conductive film on the first conductive film are removed and is not affected by contamination in the insulating film forming step. First
There is no separation from the conductive film. Further, since the third conductive film of the terminal is made of a transparent conductive film, it is hardly oxidized and the terminal does not corrode. [Embodiment] One pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device to which the present invention is applied is shown in FIG. 2 (plan view of a main part), and is cut by a II-II section line in FIG. The cross section is shown in FIG. FIG. 4 (plan view of a main part) shows a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 2 are arranged. As shown in FIGS. 2 to 4, in the liquid crystal display device, a pixel having a thin film transistor TFT and a transparent pixel electrode ITO is formed on the inner surface (liquid crystal side) of a lower transparent glass substrate SUB1. The lower transparent glass substrate SUB1 is 1.
The thickness is about 1 mm. Each pixel is located within an intersection area (4 lines) between two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines) DL. (In the area surrounded by the signal lines of FIG. 3).
As shown in FIGS. 2 and 4, the scanning signal lines GL extend in the column direction and are arranged in a plurality in the row direction. The video signal lines DL extend in the row direction and are arranged in a plurality in the column direction. The thin film transistor TFT of each pixel has 3
It is divided into two (plurality), and is constituted by thin film transistors (divided thin film transistors) TFT1, TFT2 and TFT3.
Each of the thin film transistors TFT1 to TFT3 has substantially the same size (the same channel length and width). Each of the divided thin film transistors TFT1 to TFT3 mainly includes a gate electrode GT, an insulating film GI, an i-type (intrinsic, in
An i-type semiconductor layer AS made of silicon (Si) (trinsic, not doped with a conductivity type determining impurity), and a pair of source electrode SD1 and drain electrode SD2. In addition,
It is to be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of the liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are switched during the operation. However, also in the following description, for convenience, one is fixed as a source and the other is fixed as a drain. The gate electrode GT projects from the scanning signal line GL in the row direction (downward in FIGS. 2 and 5), as shown in detail in FIG. It is configured in a T-shape (branched into a T-shape). That is, the gate electrode GT is configured to extend substantially parallel to the video signal line DL. Gate electrode GT
Are configured to protrude to respective formation regions of the thin film transistors TFT1 to TFT3. Thin film transistor
The respective gate electrodes GT of TFT1 to TFT3 are integrally formed (as a common gate electrode) and have the same scanning signal line.
It is formed continuously to GL. The gate electrode GT is formed of a single-layer first conductive film g1 so that a large step is not formed as much as possible in the formation region of the thin film transistor TFT. The first conductive film g1 is formed with a film thickness of about 1100 [Å] using, for example, a chromium (Cr) film formed by sputtering. As shown in FIGS. 2, 3 and 6, the gate electrode GT is formed to be larger than that (as viewed from below) so as to completely cover the i-type semiconductor layer AS. Therefore, when a backlight such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, this opaque Cr gate electrode
The GT becomes a shadow, and the semiconductor layer AS is not irradiated with the backlight, so that the above-described conductive phenomenon due to the light irradiation, that is, the deterioration of the TFT off characteristics is less likely to occur. Note that the original size of the gate electrode GT has a minimum width (including a margin for alignment between the gate electrode and the source / drain electrode) that extends between the source / drain electrodes SD1 and SD2, and a channel width. The depth length that determines W is determined by the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W / L that determines the transconductance gm. The size of the gate electrode in this liquid crystal display device is, of course, larger than the above-mentioned original size. The gate electrode GT and its wiring GL may be formed integrally in a single layer, considering only the gate and the light-shielding function of the gate electrode GT.
Al containing Si, pure Al, Al containing Pd, and the like can be selected. The scanning signal line GL is composed of a composite film including a first conductive film g1 and a second conductive film g2 provided thereon. The first conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is integrally formed. The second conductive film g2 is, for example, an aluminum (Al) film formed by sputtering,
It is formed with a film thickness of about [Å]. The second conductive film g2 is configured to reduce the resistance value of the scanning signal line GL and increase the signal transmission speed (write characteristics of pixel information). Further, the scanning signal line GL is configured such that the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL can be formed so that the step shape of the side wall thereof is gentle, so that the surface of the upper insulating film GI can be flattened. The insulating film GI is used as a gate insulating film of each of the thin film transistors TFT1 to TFT3. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. The insulating film GI is formed to have a thickness of about 3000 [CVD] using, for example, a silicon nitride film formed by plasma CVD. As described above, the surface of the insulating film GI is flattened in the respective forming regions of the thin film transistors TFT1 to TFT3 and the forming region of the scanning signal line GL. The i-type semiconductor layer AS is used as a channel forming region of each of the divided thin film transistors TFT1 to TFT3, as shown in detail in FIG. 6 (a plan view of a main part in a predetermined manufacturing process). Each of the i-type semiconductor layers AS of the thin-film transistors TFT1 to TFT3 divided into a plurality is integrally formed in the pixel. That is, each of the plurality of thin-film transistors TFT1 to TFT3 obtained by dividing the pixel includes:
It is composed of an island region of one (common) i-type semiconductor layer AS. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of about 1800 [Å]. This i-type semiconductor layer AS is made of Si ₃ N
_Following the formation of the insulating film GI consisting of ₄ , the same plasma CVD
The device is formed without being exposed to the outside from the device. Similarly, a P-doped N ⁺ type semiconductor layer d0 (FIG. 3) for ohmic contact is continuously formed by about 400 μm.
It is formed to a thickness of [Å]. Thereafter, the lower transparent glass substrate SUB1 is taken out of the CVD apparatus, and the N ⁺ type semiconductor layer d0 and the i type semiconductor layer AS
As shown in FIG. 3, FIG. 3 and FIG. 6, patterning is performed in an independent island shape. As described above, by integrally configuring the respective i-type semiconductor layers AS of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels, the drain electrode SD2 common to each of the thin-film transistors TFT1 to TFT3 has the i-type semiconductor layer AS ( Actually, a step corresponding to a thickness obtained by adding the thickness of the first conductive film g1, the thickness of the N ⁺ -type semiconductor layer d0, and the thickness of the i-type semiconductor layer AS) to the i-type from the drain electrode SD2 side. Since it only gets over once toward the semiconductor layer AS side, the probability of disconnection of the drain electrode SD2 is reduced, and the probability of occurrence of point defects can be reduced. That is, in this liquid crystal display device, the point defect generated in the pixel when the drain electrode SD2 gets over the step of the i-type semiconductor layer AS can be reduced to one third. Also, although different from the layout of this liquid crystal display device, i
In the case where the video signal line DL directly passes over the semiconductor layer AS and the video signal line DL in the portion over which the video signal line DL passes is configured as the drain electrode SD2, when the video signal line DL (drain electrode SD2) passes over the i-type semiconductor layer AS, It is possible to reduce the probability of occurrence of a line defect due to disconnection. That is, by integrally forming the respective i-type semiconductor layers AS of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels, the video signal line DL (drain electrode SD2) passes over the i-type semiconductor layer AS only once. There is no such thing (actually, twice at the start and end of the ride). As shown in detail in FIGS. 2 and 6, the i-type semiconductor layer AS is provided so as to extend to both the intersections (crossover portions) between the scanning signal lines GL and the video signal lines DL. ing. The extended i-type semiconductor layer AS is configured to reduce a short circuit between the scanning signal line GL and the video signal line DL at the intersection. Thin-film transistor TFT1 to TFT3 divided into multiple pixels
The source electrode SD1 and the drain electrode SD2 are formed on the i-type semiconductor layer AS, respectively, as shown in detail in FIGS. 2, 3, and 7 (plan views of main parts in a predetermined manufacturing process). They are provided separately. Each of the source electrode SD1 and the drain electrode SD2 is configured such that when the bias polarity of the circuit changes, the source and the drain are switched in operation. That is, the thin film transistor TFT is bidirectional, like the FET. The source electrode SD1 and the drain electrode SD2 are respectively connected to the first conductive film d1 and the second conductive film d1 from the lower side in contact with the N ⁺ type semiconductor layer d0.
The conductive film d2 and the third conductive film d3 are sequentially overlapped. The first conductive film d1, the second conductive film d2, and the third conductive film d3 of the source electrode SD1 are formed in the same manufacturing process as that of each of the drain electrodes SD2. The first conductive film d1 uses a chromium film formed by sputtering and has a thickness of 500 to 1000 [Å] (in this liquid crystal display device,
(Thickness of about 00 [Å]). The chromium film, when formed with a large thickness, increases the stress.
It is formed in a range that does not exceed a certain thickness. The chromium film is N ⁺
Good contact with the mold semiconductor layer d0. The chromium film forms a so-called barrier layer that prevents aluminum of a second conductive film d2 described later from diffusing into the N ⁺ -type semiconductor layer d0. First
As the conductive film d1, in addition to the chromium film, a high melting point metal (Mo,
Ti, Ta, W) film, refractory metal silicide (MoSi ₂ , TiS)
i ₂ , TaSi ₂ , WSi ₂ ) film. After patterning the first conductive film d1 by photo processing, the N ⁺ type semiconductor layer d0 is removed using the same photo processing mask or using the first conductive film d1 as a mask. That is, the i-type semiconductor layer
The portion of the N ⁺ -type semiconductor layer d0 remaining on the AS other than the first conductive film d1 is removed by self-alignment. At this time, since the N ⁺ type semiconductor layer d0 is etched so as to remove all of its thickness, the i type semiconductor layer AS is also slightly etched at its surface, but the degree may be controlled by the etching time. . Thereafter, the second conductive film d2 is formed to a thickness of 3000 to 5500 [Å] (about 3500 [Å] in this liquid crystal display device) by sputtering of aluminum. The aluminum film has less stress than the chromium film and can be formed with a large thickness, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. The second conductive film d2 is a thin film transistor TFT
And the signal transmission speed of the video signal line DL can be increased. That is, the second conductive film d2 can improve the writing characteristics of the pixel. The second conductive film d2 may be formed of an aluminum film containing silicon (Si), copper (Cu), or palladium (Pd) as an additive, in addition to the aluminum film. After patterning the second conductive film d2 by the photo processing technique,
A transparent conductive film (ITO:
The film is formed to a thickness of 1000 to 2000 [Å] (in this liquid crystal display device, a thickness of about 1200 [Å]). The third conductive film d3 forms the source electrode SD1, the drain electrode SD2, and the video signal line DL, and includes the transparent pixel electrode IT3.
O is configured. Each of the first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 has a channel forming region side larger in size than the upper second conductive film d2 and the third conductive film d3. I have. That is, the first conductive film d1 is the first conductive film
Even if a mask misalignment occurs in the manufacturing process between d1 and the second conductive film d2 and the third conductive film d3, the size of the first conductive film d1 is larger than that of the second conductive film d2 and the third conductive film d3. ~
(Each channel forming region side of the third conductive film d3 may be on the line.) First conductive film d1 of source electrode SD1, first conductive film of drain electrode SD2
Each of d1 is configured to define the gate length L of the thin film transistor TFT. As described above, in the thin film transistors TFT1 to TFT3 divided into a plurality of pixels, the source electrode SD1 and the drain electrode S
By configuring the channel forming region side of each first conductive film d1 of D2 with a size larger than the second conductive film d2 and the third conductive film d3, the source electrode SD1 and the drain electrode SD2 are formed.
The gate length L of the thin film transistor TFT can be defined by the dimension between the first conductive films d1. Since the separation dimension (gate length L) between the first conductive films d1 can be defined by processing accuracy (patterning accuracy), the gate length L of each of the thin film transistors TFT1 to TFT3 can be made uniform. The source electrode SD1 is connected to the transparent pixel electrode ITO as described above. The source electrode SD1 corresponds to a stepped shape of the i-type semiconductor layer AS (the thickness obtained by adding the thickness of the first conductive film g1, the thickness of the N ⁺ -type semiconductor layer d0, and the thickness of the i-type semiconductor layer AS). (Step). Specifically, the source electrode SD1 is connected to a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and to a transparent pixel electrode ITO above the first conductive film d1. The second conductive film d2 has a small size on the side of the second conductive film, and the third conductive film d3 is connected to the first conductive film d1 exposed from the second conductive film. The first conductive film d1 of the source electrode SD1 has good adhesion to the N ⁺ -type semiconductor layer d0, and is mainly configured as a barrier layer against diffusion from the second conductive film d2. As for the second conductive film d2 of the source electrode SD1, the chrome film of the first conductive film d1 cannot be formed thick due to an increase in stress, and the i-type semiconductor layer
Since it is not possible to get over the step shape of AS, it is configured to get over this i-type semiconductor layer AS. That is, the second
The step coverage is improved by forming the conductive film d2 thick. Since the second conductive film d2 can be formed thick,
Resistance value of source electrode SD1 (drain electrode SD2 and video signal line
The same applies to DL). Third
Since the conductive film d3 cannot get over the step shape caused by the i-type semiconductor layer AS of the second conductive film d2, the second conductive film
It is configured to be connected to the first conductive film d1 exposed by reducing the size of d2. The first conductive film d1 and the third conductive film d3 not only have good adhesiveness, but also have a small step at the connection between them, so that they can be reliably connected. Thus, the source electrode SD1 of the thin film transistor TFT
A first conductive film d1 as a barrier layer formed at least along the i-type semiconductor layer AS, and a specific resistance value formed on the first conductive film d1 and lower than the first conductive film d1. ,
And a second conductive film d2 smaller in size than the first conductive film d1.
And the first conductive film exposed from the second conductive film d2.
By connecting the third conductive film d3, which is a transparent pixel electrode ITO, to d1, the thin film transistor TFT and the transparent pixel electrode ITO can be reliably connected, so that point defects due to disconnection can be reduced. Moreover, the source electrode SD1
Since the second conductive film d2 (aluminum film) having a small resistance value can be used due to the barrier effect of the first conductive film d1, the resistance value can be reduced. The drain electrode SD2 is formed integrally with the video signal line DL, and is formed in the same manufacturing process. Drain electrode
SD2 is formed in an L-shape protruding in the column direction intersecting with the video signal line DL. That is, the drain electrodes SD2 of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels are connected to the same video signal line DL. The transparent pixel electrode ITO is provided for each pixel, and constitutes one of the pixel electrodes of the liquid crystal display unit. The transparent pixel electrode ITO is a thin film transistor T divided into a plurality of pixels.
It is divided into three transparent pixel electrodes (divided transparent pixel electrodes) ITO1, ITO2, and ITO3 corresponding to each of FT1 to TFT3. The transparent pixel electrode ITO1 is connected to the source electrode SD1 of the thin film transistor TFT1. Transparent pixel electrode ITO2
Is connected to the source electrode SD1 of the thin film transistor TFT2. The transparent pixel electrode ITO3 is connected to the source electrode SD1 of the thin film transistor TFT3. Each of the transparent pixel electrodes ITO1 to ITO3 has substantially the same size as each of the thin film transistors TFT1 to TFT3. Since each of the transparent pixel electrodes ITO1 to ITO3 is formed integrally with the respective i-type semiconductor layer AS of the thin film transistors TFT1 to TFT3 (the divided thin film transistors TFT are intensively arranged in one place). , L-shape. In this manner, the thin film transistor TFT of the pixel arranged in the intersection area between the two adjacent scanning signal lines GL and the two adjacent video signal lines DL is replaced with a plurality of thin film transistors TFT1 to TFT
FT3, and the thin-film transistor T
Transparent pixel electrode ITO divided into multiple parts for each of FT1 to TFT3
By connecting each of 1 to ITO3, only a part of the divided pixel (for example, thin film transistor TFT1) becomes a point defect and the whole pixel is not a point defect (the thin film transistors TFT2 and TFT3 are not a point defect).
Therefore, it is possible to reduce point defects in the entire pixel. Further, some of the point defects obtained by dividing the pixel are smaller than the entire area of the pixel (in the case of this liquid crystal display device,
(One-third the area of a pixel), making it difficult to see the point defects. Further, the transparent pixel electrodes ITO1 to ITO3 obtained by dividing the pixels.
Are substantially the same size, the area of the point defect in the pixel can be made uniform. Further, the transparent pixel electrodes ITO1 to ITO3 obtained by dividing the pixels.
Are configured to have substantially the same size, so that each of the liquid crystal capacitors (Cpix) constituted by each of the transparent pixel electrodes ITO1 to ITO3 and the common transparent pixel electrode ITO
In addition, the overlap capacitance (Cgs) generated by overlapping the transparent pixel electrodes ITO1 to ITO3 and the gate electrode GT added to each of the transparent pixel electrodes ITO1 to ITO3 can be made uniform. That is, since each of the transparent pixel electrodes ITO1 to ITO3 can make the liquid crystal capacitance and the overlap capacitance uniform, the DC component to be applied to the liquid crystal molecules of the liquid crystal LC caused by the overlap capacitance is made uniform. When the method of canceling out the direct current component is adopted, the variation of the direct current component applied to the liquid crystal of each pixel can be reduced. On the thin film transistor TFT and the transparent pixel electrode ITO,
A protective film PSV1 is provided. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a thickness of 5000 to 11000.
The film is formed to have a thickness of [Å] (about 8000 [Å] in this liquid crystal display device). On top of the protective film PSV1 on the thin film transistor TFT, an i-type semiconductor layer where external light is used as a channel formation region
A shielding film LS is provided so as not to be incident on the AS.
As shown in FIG. 2, the shielding film LS is formed in a region surrounded by a dotted line. The shielding film LS is formed of, for example, an aluminum film or a chromium film having a high light shielding property, and is formed to a thickness of about 1000 [Å] by sputtering. Therefore, the common semiconductor layer AS of the thin film transistors TFT1 to TFT3 is composed of the upper and lower light shielding films LS and the large gate electrode.
It is sandwiched by the GT, and no external natural light or backlight light hits it. The light-shielding film LS and the gate electrode GT are larger than the semiconductor layer AS and are formed in a shape substantially similar to the semiconductor layer AS.
The sizes of the two are almost the same (in the figure, the gate electrode GT is drawn smaller than the light shielding film LS so that the boundary line can be seen). In addition, the backlight can be attached to the upper transparent glass substrate SUB2 side, and the lower transparent glass substrate SUB1 can be the observation side (externally exposed side). In this case, the light shielding film LS is used for backlight light, and the gate electrode GT is used for natural light. Works as a light shield. The thin film transistor TFT is configured such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases. That is, the thin film transistor TFT is configured to control the voltage applied to the transparent pixel electrode ITO. The liquid crystal LC is defined and sealed in a lower alignment film ORI1 and an upper alignment film ORI2 for setting the direction of liquid crystal molecules in a space formed between the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2. . The lower alignment film ORI1 is formed above the protective film PSV1 on the lower transparent glass substrate SUB1 side. On the inner (liquid crystal side) surface of the upper transparent glass substrate SUB2, a color filter FIL, a protective film PSV2, a common transparent pixel electrode (COM) ITO, and the lower alignment film ORI2 are sequentially laminated. The common transparent pixel electrode ITO has a lower transparent glass substrate SUB
One side faces the transparent pixel electrode ITO provided for each pixel, and is configured integrally with another adjacent common transparent pixel electrode ITO. The common transparent pixel electrode ITO is configured to be applied with a common voltage Vcom. The common voltage Vcom is
Low-level drive voltage Vdmin applied to video signal line DL
And a high-level drive voltage Vdmax. The color filter FIL is configured by coloring a dye on a dyed base material formed of a resin material such as an acrylic resin.
The color filter FIL is configured for each pixel at a position facing the pixel and is dyed separately. That is, the color filter FIL is configured in an intersection area between two adjacent scanning signal lines GL and two adjacent video signal lines DL, similarly to the pixel. Each pixel is divided into a plurality of parts in each predetermined color filter of the color filter FIL. The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, by performing similar steps, a green filter G and a blue filter B are sequentially formed. As described above, by forming each color filter of the color filter FIL in the intersection region facing each pixel, each of the scanning signal lines GL and the video signal lines DL exists between the color filters of the color filter FIL. To the extent corresponding to their existence, it is possible to secure a margin for alignment between each pixel and each color filter of the color filter FIL (enlarge the alignment margin). In addition, color filters
When forming each color filter of the FIL, it is possible to secure an alignment allowance between the different color filters. That is, in this liquid crystal display device, a pixel is formed in an intersection area between two adjacent scanning signal lines GL and two adjacent video signal lines DL, and this pixel is divided into a plurality of pixels, and the pixel is opposed to the pixel. By forming each color filter of the color filter FIL at the position where the color filter FIL is formed, the above-mentioned point defects can be reduced, and a margin for alignment between each pixel and each color filter can be secured. The protective film PSV2 is provided in order to prevent the dye obtained by dyeing the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin and an epoxy resin. In this liquid crystal display device, the layers on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side are separately formed, and then the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, and the liquid crystal is interposed between the two. Assembled by enclosing LC. As shown in FIG. 4, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal lines GL extend, and pixel columns X ₁ , X ₂ , X ₃ , X ₄ ,. Each of which is configured. Each pixel of each pixel column X ₁ , X ₂ , X ₃ , X ₄ ,.
Thin film transistors TFT1 to TFT3 and transparent pixel electrodes ITO1 to
The arrangement position of ITO3 is the same. That is, the pixel column
Each pixel of X ₁ , X ₃ , ... is a thin film transistor TFT1
To TFT3 are arranged on the left side, and the arrangement positions of the transparent pixel electrodes ITO1 to ITO3 are arranged on the right side. Pixel column X _1, X _3, ... of the next pixel column X ₂ of each row direction, X _4, ... Each of the pixels of the pixel column X _1, X _3, ... the video signal to each pixel of the It is composed of pixels arranged symmetrically with respect to the line DL. That is, each pixel in the pixel rows X ₂ , X ₄ ,.
The arrangement positions of the thin film transistors TFT1 to TFT3 are on the right side, and the arrangement positions of the transparent pixel electrodes ITO1 to ITO3 are on the left side. Then, each pixel in the pixel rows X ₂ , X ₄ ,.
With respect to each of the pixels X ₁ , X ₃ ,..., The pixels are arranged (moved) by a half pixel interval in the column direction. That is, assuming that each pixel interval of the pixel row X is 1.0 (1.0 pitch), the pixel row X of the next stage has the pixel interval of 1.0 and the preceding pixel row X
Is shifted by 0.5 pixel interval (0.5 pitch) in the column direction. The video signal lines DL extending in the row direction between the pixels are configured to extend in the column direction by half pixel intervals (0.5 pitch) between the pixel columns X. Thus, in the liquid crystal display unit, the thin film transistor
A plurality of pixels having the same arrangement positions of the TFT and the transparent pixel electrode ITO are arranged in the column direction to form a pixel row X, and the next pixel row X of the pixel row X and the pixel of the preceding pixel row X are image signals. FIG. 8 (pixels and color filters are overlapped) by forming pixels arranged in line symmetry with respect to the line DL and moving the next pixel row by a half pixel interval with respect to the preceding pixel row. as shown by the fragmentary plan view) in a state where combined, pixels predetermined color filters are formed of the preceding pixel row X (e.g., the next stage of the pixel and the red filter R is formed pixels) of the pixel row X ₃ Pixels in which the same color filter in column X is formed (for example,
And a pixel pixels red filter R is formed in the column X ₄₎ 1.5
Pixel spacing (1.5 pitch) is possible. In other words, the pixels of the previous pixel row X are always separated by 1.5 pixels from the nearest pixel row of the next pixel row on which the same color filter is formed.
FIL can be configured as an RGB triangle arrangement structure. The RGB triangular arrangement structure of the color filter FIL can improve the color mixture of each color, so that the resolution of a color image can be improved. In addition, since the video signal lines DL extend in the column direction only by half pixel intervals between the pixel columns X, they do not cross adjacent video signal lines DL. Therefore, it is possible to eliminate the routing of the video signal line DL and reduce the occupied area thereof,
In addition, the bypass of the video signal line DL can be eliminated, and the multilayer wiring structure can be eliminated. FIG. 9 (equivalent circuit diagram of the liquid crystal display) shows a circuit configuration of the liquid crystal display. XiG, Xi + 1G,... Shown in FIG. 9 are video signal lines DL connected to the pixels on which the green filter G is formed. XiB, Xi + 1B, ...
This is a video signal line DL connected to the pixel on which the blue filter B is formed. Xi + 1R, Xi + 2R,... Are video signal lines DL connected to pixels on which the red filter R is formed. These video signal lines DL are selected by a video signal drive circuit. Yi
Is a scanning signal line GL for selecting the pixel column X ₁ shown in the FIG. 4 and FIG. 8. Similarly, each of Yi + 1, Yi + 2,... Is a scanning signal line for selecting each of the pixel columns X ₂ , X ₃ ,.
GL. These scanning signal lines GL are connected to a vertical scanning circuit. The center part of FIG. 3 shows a cross section of one pixel portion, while the left side shows a cross section of a left edge portion of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 where an external lead-out wiring exists. . The right side shows a cross section of a portion on the right edge portion of the transparent glass substrates SUB1 and SUB2 where no external lead-out wiring exists. The sealing material SL shown on each of the left and right sides of FIG.
The transparent glass substrates SUB1 and SU are configured to seal the liquid crystal LC, excluding the liquid crystal filling port (not shown).
It is formed along the entire periphery of the edge of B2. Seal material SL
Is formed of, for example, an epoxy resin. The common transparent pixel electrode IT on the upper transparent glass substrate SUB2 side
O is connected to the external lead-out wiring formed on the lower transparent glass substrate SUB1 side by the silver paste material SIL at least at one place. This external lead-out wiring is formed in the same manufacturing process as each of the gate electrode GT, the source electrode SD1, and the drain electrode SD2 described above. The respective layers of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO, the common transparent pixel electrode ITO, the protective films PSV1 and PSV2, and the insulating film GI are formed inside the sealing material SL. The polarizing plate POL is formed on the outer surface of each of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2. FIG. 10 is a sectional view of a main part of a pixel of a liquid crystal display portion and a peripheral portion of a seal portion of another active matrix type color liquid crystal display device to which the present invention is applied, and FIG.
FIG. 11B is a plan view of an essential part showing one pixel of a liquid crystal display portion of the liquid crystal display device shown in FIG. 11, FIG. 11B is a cross-sectional view taken along the line AA in FIG. 11A, and FIG. 13 to 15 are main part plan views in a predetermined manufacturing process of the pixel shown in FIG. 11a, and FIGS.
The figure is a plan view of a main part in a state where the pixel and the color filter shown in FIG. 12 are overlapped. In this liquid crystal display device, it is possible to improve the aperture ratio of each pixel of the liquid crystal display unit, reduce the DC component applied to the liquid crystal, reduce point defects in the liquid crystal display unit, and reduce black unevenness. it can. In this liquid crystal display device, as shown in FIG. 11a, an i-type semiconductor layer AS in each pixel of a liquid crystal display portion is formed by a thin film transistor TF.
It is configured to be divided for each of T1 to TFT3. That is, each of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels is formed of an independent island region of the i-type semiconductor layer AS. In addition, each of the transparent pixel electrodes ITO1 to ITO3 connected to each of the thin film transistors TFT1 to TFT3 overlaps the next-stage scanning signal line GL in the row direction on the side opposite to the side connected to the thin film transistors TFT1 to TFT3. Have been. This superimposition constitutes a storage capacitance element (capacitance element) Cadd in which each of the transparent pixel electrodes ITO1 to ITO3 is used as one electrode and the next-stage scanning signal line GL is used as the other electrode.
The dielectric film of the storage capacitor Cadd is a thin film transistor
It is composed of the same layer as the insulating film GI used as a TFT gate insulating film. The gate electrode GT is formed to be larger than the i-type semiconductor layer AS, similarly to the liquid crystal display device shown in FIG. 2 and the like. In this liquid crystal display device, the thin film transistors TFT1 to TFT3 are provided for each independent i-type semiconductor layer AS. As a result, a large pattern is formed for each thin film transistor TFT. In addition, since the black matrix pattern BM is provided in a portion corresponding to the scanning signal line GL, the video signal line DL, and the thin film transistor TFT of the upper transparent glass substrate SUB2, the contour of the pixel becomes clear, so that the contrast is improved. In addition, it is possible to prevent external natural light from hitting the thin film transistor TFT. FIG. 17 (equivalent circuit diagram) shows an equivalent circuit of the pixel described in FIG. 11a. In FIG. 17, as in the above, Cgs
Is a superposed capacitance formed by the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. Superposition capacity C
The gs dielectric film is an insulating film GI. Cpix is a transparent pixel electrode IT
This is a liquid crystal capacitance formed between O (PIX) and the common transparent pixel electrode ITO (COM). The dielectric film of the liquid crystal capacitor Cpix is liquid crystal L
C, a protective film PSV1 and alignment films ORI1, ORI2. V1c is a midpoint potential. The storage capacitance element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) V1c when the thin film transistor TFT switches. This situation is represented by the following equation. ΔV1c = {(Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, ΔV1c represents a change in the midpoint potential due to ΔVg, and this change ΔV1c causes a DC component applied to the liquid crystal. The larger the capacitance, the smaller the value can be.The storage capacitor Cadd also has the effect of extending the discharge time, and stores video information after the thin film transistor TFT is turned off for a longer time. The reduction of the DC component that is performed can improve the life of the liquid crystal LC and reduce the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched, as described above. Source / drain electrode SD
1. The area of overlap with SD2 increases, so the parasitic capacitance Cgs increases, and the midpoint potential V1c becomes the gate (scan) signal Vg
Has the opposite effect of being more susceptible to the effects of But,
By providing the storage capacitance element Cadd, this disadvantage can be eliminated. In a liquid crystal display device having a pixel in an intersection area between two scanning signal lines GL and two video signal lines DL, one of the two scanning signal lines GL is selected by one of the two scanning signal lines GL. The thin film transistor TFT of the pixel to be divided into a plurality of TFTs, and each of the divided thin film transistors TFT1 to TFT3 is divided into a plurality of transparent pixel electrodes ITO (ITO1 to ITO
3) Connect the divided transparent pixel electrodes ITO1 to ITO3
The pixel electrode ITO is used as one electrode for each of
By using the other scanning signal line GL of the two scanning signal lines GL as the capacitor electrode line and forming the storage capacitor Cadd as the other electrode, as described above, the divided part of the pixel is dotted. Since only the defect becomes a point defect as a whole of the pixel, the point defect of the pixel can be reduced, and the DC component applied to the liquid crystal LC by the storage capacitor Cadd can be reduced. LC life can be improved. In particular, by dividing the pixel, the gate electrode GT and the source electrode S of the thin film transistor TFT are
Point defects due to short circuit with D1 or drain electrode SD2 can be reduced, and transparent pixel electrodes ITO1 to IT
Point defects caused by a short circuit between each of O3 and the other electrode (capacitor electrode line) of the storage capacitor Cadd can be reduced. The point defect on the latter side is one third in the case of this liquid crystal display device.
become. As a result, some of the divided point defects of the pixel are smaller than the entire area of the pixel, so that it is difficult to see the point defect. The storage capacitance of the storage capacitance element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4 · Cpix <Cadd) due to the writing characteristics of the pixel.
<8 · Cpix), 8 to 32 times (8
・ Set to a value of about Cgs <Cadd <32 · Cgs). Further, the scanning signal line GL is connected to a first conductive film (chrome film) g1.
And a second conductive film (aluminum film) g2 is superposed on the composite film, and the other electrode of the storage capacitor Cadd, that is, the branched portion of the capacitor electrode line is connected to the first conductive film of one layer of the composite film. With the single-layer film composed of the film g1, the resistance value of the scanning signal line GL can be reduced, the writing characteristics can be improved, and along the step portion based on the other electrode of the storage capacitor Cadd. Since one electrode (transparent pixel electrode ITO) of the storage capacitor Cadd can be securely bonded onto the insulating film GI, disconnection of one electrode of the storage capacitor Cadd can be reduced. Further, the other electrode of the storage capacitor Cadd is formed of the single-layer first conductive film g1 and the second conductive film g2 of the aluminum film is not formed, so that the other electrode of the storage capacitor Cadd due to the hillock of the aluminum film is formed. A short circuit between the electrode and one of the electrodes can be prevented. A part between each of the transparent pixel electrodes ITO1 to ITO3 overlapped to form the storage capacitor element Cadd and a branched part of the capacitor electrode line is branched like the source electrode SD1. An island region composed of the first conductive film d1 and the second conductive film d2 is provided so that the transparent pixel electrode ITO is not disconnected when the vehicle passes over the stepped portion.
This island region is configured as small as possible so as not to reduce the area (opening ratio) of the transparent pixel electrode ITO. As described above, the first conductive film d1 is located between one electrode of the storage capacitor Cadd and the insulating film GI used as a dielectric film thereof, as compared with the first conductive film d1 formed thereon. An underlayer formed of the second conductive film d2 having a small specific resistance and a small size constitutes an underlayer, and the one electrode (the third conductive film d2) is formed.
3) is connected to the first conductive film d1 exposed from the second conductive film d2 of the underlying layer, thereby ensuring one of the storage capacitor elements Cadd along a step portion based on the other electrode of the storage capacitor element Cadd. Since the electrodes can be bonded, disconnection of one electrode of the storage capacitor Cadd can be reduced. The liquid crystal display of the liquid crystal display device in which the storage capacitor Cadd is provided on the transparent pixel electrode ITO of the pixel is configured as shown in FIG. 19 (an equivalent circuit diagram showing the liquid crystal display). The liquid crystal display section is configured by repeating a unit basic pattern including pixels, scanning signal lines GL, and video signal lines DL. The final scanning signal line GL (or the first scanning signal line GL) used as the capacitor electrode line is connected to the common transparent pixel electrode (Vcom) ITO as shown in FIG. Common transparent pixel electrode ITO
As shown in FIG. 3, the peripheral portion of the liquid crystal display device is connected to an external lead-out wiring by a silver paste material SL. In addition, some of the conductive layers (g1
And g2) are formed in the same manufacturing process as the scanning signal line GL. As a result, the final scanning signal line GL (capacitance electrode line)
Can be easily connected to the common transparent pixel electrode ITO. As described above, by connecting the last stage of the capacitor electrode line to the common transparent pixel electrode (Vcom) ITO of the pixel, the last stage capacitor electrode line is formed integrally with a part of the external lead-out wiring and the conductive layer. In addition, since the common transparent pixel electrode ITO is connected to the external lead-out line, the last stage capacitor electrode line can be connected to the common transparent pixel electrode ITO with a simple configuration. In addition, the liquid crystal display device employs a direct current canceling method (D / A) described in Japanese Patent Application No. 62-95125 previously filed by the present applicant.
As shown in FIG. 18 (time chart), the DC component applied to the liquid crystal LC can be further reduced by controlling the driving voltage of the scanning signal line DL based on the C cancellation method). In FIG. 18, Vi is a drive voltage of an arbitrary scanning signal line GL, and Vi + 1 is a driving voltage of a scanning signal line GL at the next stage. Vee is a low-level driving voltage Vdmin applied to the scanning signal line GL, and Vdd is a high-level driving voltage Vdmax applied to the scanning signal line GL. Each time t = t _{1 to} t ₄
Voltage change ΔV ₁ of the midpoint potential V1c (see FIG. 17) at
~ ΔV ₄ is the total capacity of pixels (Cgs + Cpix + Cadd) as C
Then, the following equation is obtained. ΔV ₁ = − (Cgs / C) · V2 ΔV ₂ = + (Cgs / C) · (V1 + V2) − (Cadd / C) · V2 ΔV ₃ = − (Cgs / C) · V1 + (Cadd / C) · ( V1 + V2) ΔV ₄ = − (Cadd / C) · V1 Here, if the drive voltage applied to the scanning signal line GL is sufficient (see below)

Note: The DC voltage applied to the liquid crystal LC is expressed by the following equation. ΔV ₃ + ΔV ₄ = (Cadd · V2−Cgs · V1) / C Therefore, if Cadd · V2 = Cgs · V1, the DC voltage applied to the liquid crystal LC becomes zero.

〔The invention's effect〕

As described above, in the method for forming a terminal of a liquid crystal display device according to the present invention, a signal line composed of a multilayer film of a first conductive film and a second conductive film is formed, and at the same time, the first conductive film of the terminal and After forming the second conductive film and forming the insulating film covering the signal line, the insulating film in the terminal portion is removed, and the second conductive film on the first conductive film exposed from the insulating film is removed.
The surface of the first conductive film of the terminal is not contaminated by the insulating film forming step. Further, since the third conductive film of the terminal is formed after the formation of the insulating film covering the signal line, the terminal surface is not contaminated by the insulating film forming step. In addition, the third conductive film of the terminal is formed in a portion where the insulating film and the second conductive film on the first conductive film are removed and is not affected by contamination in the insulating film forming step. First
There is no separation from the conductive film. Further, since the third conductive film of the terminal is made of a transparent conductive film, it is hardly oxidized and the terminal does not corrode. Thus, the effect of the present invention is remarkable.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a method of manufacturing an active matrix type color liquid crystal display device according to the present invention, and FIG. FIG. 3 is a cross-sectional view of a portion taken along the line II-II of FIG. 2 and a peripheral portion of the seal portion, and FIG. 4 is a liquid crystal display portion in which a plurality of pixels shown in FIG. 2 are arranged. 5 to 7 are plan views of main parts in a predetermined manufacturing process of the pixel shown in FIG. 2,
FIG. 8 is a plan view of a main part in a state where the pixel and the color filter shown in FIG. 4 are superimposed, FIG. 9 is an equivalent circuit diagram showing a liquid crystal display unit of the active matrix type color liquid crystal display device, FIG. 10 is a cross-sectional view of a main part of a pixel of a liquid crystal display portion and a peripheral portion of a seal portion of another active matrix type color liquid crystal display device to which the present invention is applied, and FIG. 11a is a liquid crystal shown in FIG. FIG. 11b is a plan view of an essential part showing one pixel of the liquid crystal display portion of the display device, and FIG.
FIG. 12 is a cross-sectional view of a portion cut along the cutting line A, FIG. 12 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 11a are arranged, and FIGS. 16 is a plan view of a main part in a manufacturing process of FIG. 16, FIG. 16 is a plan view of a main part in a state where the pixel shown in FIG. 12 and the color filter are superimposed, and FIG. FIG. 18 is a time chart showing the driving voltage of the scanning signal line by the direct current canceling method, and FIGS. 19 and 20 each show a liquid crystal display section of the active matrix type color liquid crystal display device shown in FIG. The equivalent circuit diagram, FIG. 21 and FIG.
FIG. 23 is a plan view of a part of the liquid crystal display device for explaining a manufacturing method in a predetermined manufacturing process, and FIG. 23 is an explanatory diagram of another active matrix type color liquid crystal display device according to the present invention. SUB: transparent glass substrate GL: scanning signal line DL: video signal line GI: insulating film GT: gate electrode AS: i-type semiconductor layer SD: source or drain electrode PSV: protective film LS: light shielding film LC: liquid crystal TFT: thin film transistor ITO (COM): Transparent pixel electrode g, d: Conductive film Cadd: Holding capacitor Cgs: Overlapping capacitor Cpix: Liquid crystal capacitor BM: Black matrix pattern 1: Drain terminal 4: ITO film

Continuation of the front page (72) Inventor Akira Sasano 3300 Hayano, Mobara-shi, Chiba Pref. In the Mobara Plant of Hitachi Ltd. (56) References JP-A-63-316084 (JP, A) (58) .Cl. ⁶ , DB name) G02F 1/1345

Claims (1)

(57) [Claims] 1. A signal is supplied to the plurality of pixels on one glass substrate of a liquid crystal display device forming a plurality of pixels.
A plurality of signal lines and a plurality of terminal portions serving as terminals connected to the plurality of signal lines, respectively, can be selectively etched with respect to the first conductive film and the first conductive film deposited on the first conductive film. A step of forming a multilayer film with a second conductive film; a step of forming an insulating film covering the plurality of signal lines and the plurality of terminal portions on the glass substrate; and the insulating film on the plurality of terminal portions Removing the second conductive film exposed from the insulating film of the plurality of terminal portions; and removing the second conductive film of the first conductive film of the plurality of terminal portions. Forming a third conductive film made of a transparent conductive film in each of the portions.