JP2846351B2 - Liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a configuration of a scanning signal line, a video signal line, and a terminal of the liquid crystal display device.

[Conventional technology]

For example, an active matrix type liquid crystal display device includes a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active method has better contrast than the so-called simple matrix method that employs the time-division driving method. It is not a technology. A typical switching element is a thin film transistor (TFT).

The liquid crystal display section was provided with a lower transparent glass substrate on which a thin film transistor, a transparent pixel electrode, a protective film for a thin film transistor, and an alignment film were sequentially provided, and a color filter, a protective film for a color filter, a common transparent pixel electrode, and an alignment film. It is composed of an upper transparent glass substrate, liquid crystal sealed and sealed between both substrates, and a sealing material for sealing the liquid crystal.

A liquid crystal display device having a TET and a pixel electrode as one component of a pixel has a liquid crystal display unit in which a plurality of pixels are arranged in a matrix. Each pixel of the liquid crystal display section has an intersection between two adjacent scanning signal lines (also called gate signal lines or horizontal signal lines) and two adjacent video signal lines (also called drain signal lines or vertical signal lines). It is located in the area. The scanning signal lines extend in the column direction (horizontal direction) and are arranged in a row direction (vertical direction). On the other hand, a plurality of video signal lines extend in a row direction intersecting with the scanning signal lines and are arranged in a plurality in a column direction. Terminals for signal input are provided at the ends of each scanning signal line and each video signal line. Each scanning signal line and each video signal line are covered with a protective film, but since the terminal section is connected to the signal output terminal,
Outside the protective film.

Note that an active matrix liquid crystal display device using a TFT is, for example, "12.5 type active matrix color liquid crystal display employing a redundant configuration", Nikkei Electronics, pp. 193-210, December 15, 1986, Nikkei McGraw-Hill, Inc. Issued, known in.

[Problems to be solved by the invention]

In the conventional liquid crystal display device, there is a problem that display unevenness occurs because the resistance between the scanning signal line and the video signal line is not sufficiently small.

An object of the present invention is to sufficiently reduce the resistance of a scanning signal line and a video signal line and improve the characteristics of a liquid crystal display device.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the foregoing description of the specification and the accompanying drawings.

[Means for solving the problem]

In order to achieve the above object, a liquid crystal display device of the present invention includes a plurality of scanning signal lines extending horizontally on an insulating substrate, and a plurality of scanning signal lines provided on the scanning signal lines and intersecting with the scanning signal lines. A video signal line, and a pixel which is arranged in an intersecting region between the two adjacent scanning signal lines and the two adjacent video signal lines, and includes a thin film transistor and a pixel electrode as one component. , The scanning signal line is Ta or Ti
And a second conductive film made of Al laminated on the first conductive film. The surfaces of the first conductive film and the second conductive film are formed by oxidation of the respective conductive films. It is characterized by being covered with a film.

Further, the scanning signal line is characterized in that the width dimension of the second conductive film is substantially smaller than the width dimension of the first conductive film.

[Action]

In the present invention, since Al is used for the scanning signal line or the video signal line, the resistance can be reduced. In addition, since the surface of the Al wiring except for the connection part with the terminal is covered with the self-oxidized film of the AL wiring, the occurrence of Al projections called hillocks and whiskers peculiar to the Al wiring prevents the occurrence of short circuit failure between wirings. I can do it. Also, if Al is used for the terminal portion, electrolytic corrosion occurs,
In the present invention, since a highly reliable ITO is used for the terminal portion without using Al, the reliability of the terminal can be improved.

Furthermore, since the Al wiring and the ITO terminal are electrically connected with a metal different from Al, the power supply to the Al wiring does not occur due to the contact resistance between the Al and the ITO. Will not wake up.

〔Example〕

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to an active matrix type color liquid crystal display device.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 2A is a plan view showing one pixel of an active matrix type color liquid crystal display device to which the present invention is applied and the periphery thereof, and FIG. 2B is a cross-sectional view taken along a line IIB-IIB in FIG. 2A. FIG. 2C is a cross-sectional view of the vicinity of the seal portion of the panel, and FIG. 2C is a cross-sectional view taken along the line IIC-IIC in FIG. 2A. FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged.

<< Pixel Arrangement >> As shown in FIG. 2A, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines). Signal line) DL
(In a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a pixel electrode ITO1, and an additional capacitance Cadd. The scanning signal lines GL extend in the column direction, and a plurality of the scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction and are arranged in a plurality in the column direction.

<< Overall Structure of Panel Section >> As shown in FIG. 2B, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side based on the liquid crystal layer LC, and a color filter is formed on the upper transparent glass substrate SUB2 side. FIL, black matrix pattern B for shading
M is formed. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 [mm].

The center part of FIG. 2B shows a cross section of one pixel part,
The left side shows the left side edge portions of the transparent glass substrates SUB1 and SUB2, and the right side shows the right side edge portions of the transparent glass substrates SUB1 and SUB2, each showing a cross section of a portion of the external lead wiring where the measurement terminal is present. .

The sealing material SL shown on the left and right sides of FIG.
It is configured to seal the LC, and is formed along the entire periphery of the transparent glass substrates SUB1 and SUB2 except for the liquid crystal sealing port (not shown). The sealing material SL is formed of, for example, an epoxy resin.

The common transparent pixel electrode IT on the upper transparent glass substrate SUB2 side
O2 is connected to the external lead-out wiring formed on the lower transparent glass substrate SUB1 side by the silver paste material SIL at at least one place. This external lead-out wiring is formed in the same manufacturing process as the above-described gate electrode GT, source electrode SD1, and drain electrode SD2.

Each layer of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO, the common transparent pixel electrode ITO, the protective films PSV1 and PSV2, and the insulating film GI is formed inside the sealing material SL. The polarizing plate POL is formed on the outer surface of each of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2.

The liquid crystal LC is a lower alignment film ORI1 that sets the orientation of the liquid crystal molecules.
And the upper alignment film ORI2, and is sealed by a seal portion SL.

The lower alignment film ORI1 is formed above the protective film PSV1 on the lower transparent glass substrate SUB1 side.

On the inner (liquid crystal side) surface of the upper transparent glass substrate SUB2, a light-shielding film BM, a color filter FIL, a protective film PSV2, a common transparent pixel electrode (COM) ITO2, and an upper alignment film ORI2 are sequentially laminated. .

In this liquid crystal display device, the respective layers on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side are separately formed, and then the upper and lower transparent glass substrates SUB1 and SUB2 are overlapped, and the liquid crystal LC is sealed between the two. Assembled by

<< Thin Film Transistor TFT >> The thin film transistor TFT operates so that the channel resistance between the source and the drain decreases when a positive bias is applied to the gate electrode GT, and the channel resistance increases when the bias is set to zero.

The thin film transistor TFT of each pixel has 3
One (plural) divided thin film transistors (divided thin film transistors) TFT1, TFT2, and TFT3 are configured. Each of the thin film transistors TFT1 to TFT3 has substantially the same size (the same channel length and width). Each of the divided thin film transistors TFT1 to TFT3 mainly includes a gate electrode GT, a gate insulating film GI, an i-type (intrinsic, intr
Insic, which is not doped with the conductivity type determining impurity), is composed of an amorphous Si semiconductor layer AS, a pair of source electrode SD1 and drain electrode SD2. It should be understood that the source and the drain are originally determined by the bias polarity between them, and the polarity of the circuit of the present display device is inverted during the operation, so that the source and the drain are switched during the operation. However, also in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.

<< Gate Electrode GT >> As shown in detail in FIG. 4 (a plan view depicting only the layers g1, g2, and AS in FIG. 2A), the gate electrode GT has a scanning signal line GL.
From the vertical direction (upward in FIGS. 2A and 4) (branched into a T-shape). The gate electrode GT is configured to protrude to each of the formation regions of the thin film transistors TFT1 to TFT3. The respective gate electrodes GT of the thin film transistors TFT1 to TFT3 are integrally formed (as a common gate electrode) and formed continuously with the scanning signal line GL. The gate electrode GT is formed of a single-layer first conductive film g1 so that a large step is not formed in a region where the thin film transistor TFT is formed. The first conductive film g1 is formed, for example, using a chromium (Cr) film formed by sputtering and having a thickness of about 1000 [Å].

As shown in FIGS. 2A, 2B and 4, the gate electrode GT is formed to be larger than that (as viewed from below) so as to completely cover the semiconductor layer AS. Therefore, the substrate
When a backlight BL such as a fluorescent lamp is mounted below SUB1, the opaque Cr gate electrode GT is shaded, and the semiconductor layer AS is not irradiated with the backlight, and the conductive phenomenon due to light irradiation, that is, the TFT is turned off. Characteristic degradation is less likely to occur. Note that the original size of the gate electrode GT is the minimum necessary to extend between the source / drain electrodes SD1 and SD2 (including the alignment margin between the gate electrode and the source / drain electrodes).
It has a width, and its depth length that determines the channel width W is the ratio to the distance (channel length) L between the source and drain electrodes, that is, a factor W / L that determines the transconductance gm.
Is determined by how many.

The size of the gate electrode in this embodiment is, of course, larger than the original size described above.

Considering only the gate electrode GT and the light shielding function, the gate electrode and its wiring GL may be integrally formed in a single layer, in this case, Al containing Si as an opaque conductive material, pure Al or Pd-containing Al can be selected.

<< Scanning Signal Line GL >> The scanning signal line GL is formed of a composite film including the first conductive film g1 and the second conductive film g2 provided thereon. The first conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is integrally formed. The second conductive film g2 is, for example, an aluminum (Al) film formed by sputtering,
It is formed with a thickness of about 00 [Å]. The second conductive film g2 is configured so as to reduce the resistance value of the scanning signal line GL and increase the signal transmission speed (improve the writing characteristics of pixel information).

Further, the scanning signal line GL is configured such that the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL has a gentle step shape on the side wall.

<< Gate insulating film GI >> The insulating film GI is used as each gate insulating film of the thin film transistors TFT1 to TFT3. The insulating film GI is the gate electrode
It is formed above the GT and the scanning signal line GL. Insulating film GI
Is formed, for example, using a silicon nitride film formed by plasma CVD and having a thickness of about 3000 [Å].

<< Semiconductor Layer AS >> As shown in FIG. 4, the i-type semiconductor layer AS is used as a channel forming region of each of a plurality of divided thin film transistors TFT1 to TFT3. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film,
It is formed with a film thickness of about [Å].

This i-type semiconductor layer AS is made of Si ₃ N
_{Fourth, following} the formation of the gate insulating film GI, the gate insulating film GI is formed in the same plasma CVD apparatus without being exposed to the outside from the apparatus. Similarly, an N ⁺ layer do doped with P for ohmic contact (FIG. 2B) is formed continuously to a thickness of about 400 [400]. Thereafter, the lower substrate SUB1 is taken out of the CVD apparatus, and the N ⁺ layer d0 and the i layer
AS is patterned into independent islands as shown in FIGS. 2A, 2B and 4.

As shown in detail in FIGS. 2A and 4, the i-type semiconductor layer AS is also provided between both intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. This intersection i
The type semiconductor layer AS is configured to reduce a short circuit between the scanning signal line GL and the video signal line DL at the intersection.

<< Source / Drain Electrodes SD1, SD2 >> The source electrode SD1 and the drain electrode SD2 of each of the thin-film transistors TFT1 to TFT3 divided into a plurality are shown in FIGS. 2A and 2B.
FIG. 5 and FIG. 5 (a plan view showing only layers d1 to d3 in FIG. 2A)
As will be described in detail later, they are provided separately on the semiconductor layer AS.

The source electrode SD1 and the drain electrode SD2 are respectively formed from a first conductive film d1 and a second conductive film from the lower side in contact with the N ⁺ type conductive layer d0.
d2 and a third conductive film d3 are sequentially superposed.
The first conductive film d1, the second conductive film d2, and the third conductive film d1 of the source electrode SD1 are formed.
The conductive film d3 is formed in the same manufacturing process as each of the drain electrodes SD2.

The first conductive film d1 uses a chromium film formed by sputtering and has a thickness of 500 to 1000 [Å] (in this embodiment, 600 [Å]).
(About the same thickness). The chromium film is formed so as not to exceed a thickness of about 2000 [Å] because the stress of forming a thick film increases. Chromium film is an N ⁺ type semiconductor layer
Good contact with d0. The chromium film forms a so-called barrier layer that prevents aluminum of a second conductive film d2 described later from diffusing into the N ⁺ -type semiconductor layer d0. As the first conductive film d1, in addition to the chromium film, a high melting point metal (Mo, Ti, Ta, W)
Film, refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ )
It may be formed of a film.

After patterning the first conductive film d1 by photo processing, the same photo processing mask or N ⁺
Layer d0 is removed. That is, the N ⁺ layer remaining on the i-layer AS
As for d0, portions other than the first conductive film d1 are removed by self-alignment. At this time, since the N ⁺ layer d0 is etched so as to completely remove its thickness, the i layer AS is also slightly etched at its surface, but the degree may be controlled by the etching time.

Thereafter, the second conductive film d2 is formed to a thickness of 3000 to 4000 [Å] by sputtering of aluminum (in this embodiment, 3000 to 4000 [Å]).
[Å]. The aluminum film is
The stress is smaller than that of the chromium film, it can be formed in a thick film, and the resistance value of the source electrode SD1, the drain electrode SD2 and the video signal line DL is reduced. The second conductive film d2 may be formed of an aluminum film containing silicon (Si) or copper (Cu) as an additive, in addition to the aluminum film.

After patterning the second conductive film d2 by a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Induim-Tin-Oxide I) formed by sputtering.
TO: Nesa film) and is formed to a thickness of 1000 to 2000 [Å] (in this embodiment, a thickness of about 1200 [Å]). The third conductive film d3 forms the source electrode SD1, the drain electrode SD2, and the video signal line DL, and also forms the transparent pixel electrode ITO1.

Each of the first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 greatly penetrates inside (into the channel region) as compared with the upper second conductive film d2 and the third conductive film d3. I have. That is, the first conductive film in these portions
d1 is configured so that the gate length L of the thin film transistor TFT can be defined independently of the layers d2 and d3.

The source electrode SD1 is, as described above, a transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 is an i-type semiconductor layer AS
(The film thickness of the first conductive film g1, the film thickness of the N ⁺ layer d0, and i
Step equivalent to the film thickness obtained by adding the film thickness of the semiconductor layer AS)
It is configured along. Specifically, the source electrode SD1
Represents a first portion formed along the step shape of the i-type semiconductor layer AS.
A conductive film d1, a second conductive film d2 formed on the upper side of the first conductive film d1 and connected to the transparent pixel electrode ITO1 with a smaller size, and a first conductive film exposed from the second conductive film. And a third conductive film d3 connected to the film d1.
Since the second conductive film d2 of the source electrode SD1 cannot form a thick chrome film of the first conductive film d1 due to an increase in stress and cannot overcome the step of the i-type semiconductor layer AS, the second conductive film d2 is It is configured to get over. That is, the step coverage is improved by forming the second conductive film d2 to be thick. Since the second conductive film d2 can be formed to be thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).
Since the third conductive film d3 cannot overcome the stepped shape caused by the i-type semiconductor layer AS of the second conductive film d2, the first conductive film exposed by reducing the size of the second conductive film d2
It is configured to connect to d1. The first conductive film d1 and the third conductive film d3 not only have good adhesiveness, but also have a small step at the connection between them, so that they can be reliably connected.

<< Pixel Electrode ITO1 >> The transparent pixel electrode ITO1 is provided for each pixel, and constitutes one of the pixel electrodes of the liquid crystal display unit. Transparent pixel electrode ITO1 is a thin-film transistor divided into multiple pixels
It is divided into three transparent pixel electrodes (divided transparent pixel electrodes) E1, E2, and E3 corresponding to each of TFT1 to TFT3. Each of the transparent pixel electrodes E1 to E3 is connected to a source electrode SD1 of the thin film transistor TFT.

Each of the transparent pixel electrodes E1 to E3 is patterned so as to have substantially the same area.

As described above, by dividing the thin film transistor TFT of one pixel into a plurality of thin film transistors TFT1 to TFT3, and connecting each of the plurality of divided transparent pixel electrodes E1 to E3 to each of the plurality of divided thin film transistors TFT1 to TFT3, ,
Even if the divided part (for example, TFT1) becomes a point defect, it is not a point defect in the whole pixel (TFT2 and TFT3).
Is not a defect), the probability of a point defect can be reduced, and the defect can be made difficult to see.

Further, by configuring each of the divided transparent pixel electrodes E1 to E3 of the pixel with substantially the same area, each of the liquid crystal composed of each of the transparent pixel electrodes E1 to E3 and the common transparent pixel electrode ITO2 is formed. The capacity (Cpix) can be made uniform.

<< Protective film PSV1 >> On the thin film transistor TFT and the transparent pixel electrode ITO1,
A protective film PSV1 is provided. The protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance. The protection film PSV1 is formed of, for example, a silicon oxide film or a nitrogen silicon film formed by plasma CVD, and has a thickness of 8000 [Å].
It is formed with a film thickness of about.

<< Shading film BM >> On the upper substrate SUB2 side, an i-type semiconductor layer in which external light (light from above in FIG. 2B) is used as a channel formation region
A shielding film BM is provided so as not to enter the AS, and has a pattern as shown by hatching in FIG. FIG. 6 shows the ITO thin film d3 and the filter layer FIL in FIG. 2A.
FIG. 3 is a plan view illustrating only a light shielding film BM. The light shielding film BM
It is formed of, for example, an aluminum film, a chromium film, or the like having a high light shielding property. In this embodiment, the chromium film is formed to a thickness of about 1300 [Å] by sputtering.

Therefore, the common semiconductor layers AS of the TFTs 1 to 3 are sandwiched by the upper and lower light shielding films BM and the large gate electrodes GT, and the portions are not exposed to external natural light or backlight. The light-shielding film BM is formed around the pixel as shown by the hatched portion in FIG. 6, that is, the light-shielding film BM is formed in a lattice shape (black matrix), and the effective display area of one pixel is partitioned by the lattice. I have. Therefore, the contour of each pixel is clear by the light shielding film BM, and the contrast is improved. That is, the light shielding film BM has two functions, that is, light shielding for the semiconductor layer AS and black matrix.

It should be noted that the backlight can be attached to the SUB2 side and the SUB1 can be the observation side (externally exposed side).

<< Common electrode ITO2 >> The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal is between each pixel electrode ITO1 and the common electrode ITO2. It changes in response to a potential difference (electric field). The common transparent pixel electrode ITO2 is configured to apply a common voltage Vcom. The common voltage Vcom is a low-level drive voltage Vd min and a high-level drive voltage applied to the video signal line DL.
It is an intermediate potential with Vd max.

<< Color Filter FLL >> The color filter FIL is formed by coloring a dye on a dye substrate formed of a resin material such as an acrylic resin.
The color filter FIL is formed in a dot shape for each pixel at a position facing the pixel (FIG. 7) and is dyed separately (FIG. 7 shows the third conductive film layer d3 and the color filter layer of FIG. 3).
Only the FIL is drawn, and each of the R, G, and B filters has a 45 の, 135 ゜, cross hatch.) As shown in FIG. 6, the color filter FIL has a pixel electrode ITO1 (E
1 to E3) is formed to be large enough to cover all of
M is formed inside the periphery of the pixel electrode ITO1 so as to overlap the color filter FIL and the edge of the pixel electrode ITO1.

The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, by performing similar steps, a green filter G and a blue filter B are sequentially formed.

The protective film PSV2 is provided in order to prevent the dye obtained by dyeing the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin.

<< Pixel Arrangement >> As shown in FIGS. 3 and 7, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal lines GL extend, and the pixel columns X1, X2, X3 , X4, ... respectively. Each pixel in each of the pixel rows X1, X2, X3, X4,... Has the same arrangement position of the thin film transistors TFT1 to TFT3 and the transparent pixel electrodes E1 to E3. That is, each pixel of the odd-numbered pixel rows X1, X3,... Has the thin film transistors TFT1 to TFT3 arranged on the left and the transparent pixel electrodes E1 to E3 arranged on the right. Each of the even-numbered pixel columns X2, X4,... Adjacent in the row direction of the odd-numbered pixel columns X1, X3,.
Are turned upside down in line symmetry with respect to the extending direction of the video signal line DL. That is, each pixel of the pixel rows X2, X4,... Has the thin film transistors TFT1 to TFT3 arranged on the right and the transparent pixel electrodes E1 to E3 arranged on the left. Then, pixel rows X2, X4,
Are arranged (moved) by a half pixel interval in the column direction with respect to the pixels of the pixel columns X1, X3,. That is, assuming that the pixel interval of the pixel row X is 1.0 (1.0 pitch), the pixel row X of the next stage has the pixel interval of 1.0.
It is shifted by 0.5 pixel interval (0.5 pitch) in the column direction with respect to the preceding pixel column X. The video signal lines DL extending in the row direction between the pixels are configured to extend in the column direction by half pixel intervals (0.5 pitch) between the pixel columns X.

As a result, as shown in FIG. 7, a pixel of a predetermined color filter of the preceding pixel row X are formed (e.g., pixels red filter R of the pixel column X ₃ is formed) and the next pixel column X A pixel on which the same color filter is formed (for example, a pixel on which the red filter R of the pixel column X4 is formed) is spaced by 1.5 pixels (1.5 pixels).
Pitch), and the RGB color filters FIL are arranged in a triangle. The RGB triangular arrangement structure of the color filter FIL can improve the color mixture of each color, so that the resolution of a color image can be improved.

In addition, since the video signal lines DL extend in the column direction only by half pixel intervals between the pixel columns X, they do not cross adjacent video signal lines DL. Therefore, it is possible to eliminate the routing of the video signal line DL and reduce the occupied area thereof,
In addition, the bypass of the video signal line DL can be eliminated, and the multilayer wiring structure can be eliminated.

<< Equivalent Circuit of Entire Display Panel >> FIG. 8 shows an equivalent circuit of the liquid crystal display unit. XiG,
Xi + 1G,... Are video signal lines DL connected to the pixels on which the green filter G is formed. XiB, Xi + 1B,... Are video signal lines DL connected to the pixels on which the blue filters B are formed. Xi + 1R, Xi + 2R,... Are video signal lines DL connected to pixels on which the red filter R is formed. These video signal lines DL are alternately drawn out on both sides and are selected by two video signal drive circuits. Yi is a scanning signal line GL for selecting the pixel column X1 shown in FIG. 3 and FIG. Similarly, Yi + 1,
Each of Yi + 2,... Is a scanning signal line GL for selecting each of the pixel columns X2, X3,. These scanning signal lines GL are connected to a vertical scanning circuit. Cadd indicates an additional capacity, and Vcom indicates a common voltage.

<< Structure of Additional Capacitor Cadd >> Each of the transparent pixel electrodes E1 to E3 is a thin film transistor TFT.
At the end opposite to the end connected to the scanning signal line GL, it is bent in an L-shape so as to overlap the adjacent scanning signal line GL. As is clear from FIG. 2C, this superposition is performed by using a storage capacitor (capacitance) in which each of the transparent pixel electrodes E1 to E3 is set as one electrode PL2 and the adjacent scanning signal line GL is set as the other electrode PL1. (Element) constitutes Cadd. The dielectric film of the storage capacitor Cadd is formed of the same layer as the insulating film GI used as the gate insulating film of the thin film transistor TFT.

As is apparent from FIG. 4, the storage capacitor Cadd is formed at a portion where the width of the first layer g1 of the gate line GL is increased.
Note that the portion of the layer g1 that intersects with the drain line GL is thinned in order to reduce the probability of a short circuit with the drain line.

Like the source electrode SD1, a portion between each of the transparent pixel electrodes E1 to E3 and the capacitor electrode line (g1) which are superimposed to form the storage capacitor Cadd, when climbing over a stepped shape, To prevent the transparent pixel electrode ITO1 from breaking,
An island region constituted by the conductive film d1 and the second conductive film d2 is provided. This island region is configured to be as small as possible so as not to reduce the area (opening ratio) of the transparent pixel electrode ITO1.

<< Equivalent Circuit of Additional Capacitor Cadd and Its Operation >> FIG. 9 shows an equivalent circuit of the pixel shown in FIG. 2A. In FIG. 9, Cgs is a gate electrode of the thin film transistor TFT.
This is a parasitic capacitance formed between GT and the source electrode SD1.
The dielectric film of the parasitic capacitance Cgs is the insulating film GI. Cpix is transparent pixel electrode ITO1 (PIX) and common transparent pixel electrode ITO2 (COM)
This is the liquid crystal capacitance formed between the two. The dielectric films of the liquid crystal capacitor Cpix are the liquid crystal LC, the protective film PSV1, and the alignment films ORI1, ORI2. V
lc is the midpoint potential.

The holding capacitance element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the TFT switches. This state can be expressed by an equation as follows: ΔTlc = {(Cgs / (Cgs + Cadd + Cpix)} × ΔVg, where ΔVlc represents a change in the midpoint potential due to ΔVg. However, as the storage capacitance Cadd is increased, the value can be reduced, and the storage capacitance Cadd also has an effect of increasing the discharge time, and accumulates long image information after the TFT is turned off. Reduction of the DC component applied to the LC improves the life of the liquid crystal LC, and can reduce so-called burn-in in which a previous image remains when the liquid crystal display screen is switched.

As described above, the gate electrode GT is enlarged so as to completely cover the semiconductor layer AS, so that the source / drain electrode SD
1.The area of overlap with SD2 increases, so the parasitic capacitance Cg
As s increases, the midpoint potential Vlc has an adverse effect of being easily affected by the gate (scan) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cadd.

The storage capacitance of the storage capacitance element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4 · Cpix <Cadd) due to the writing characteristics of the pixel.
<8 · Cpix), 8 to 32 times (8
・ Set to a value of about Cgs <Cadd <32 · Cgs).

<< Connection method of additional capacitance Cadd electrode line >> Scan signal line of the last stage used only as capacitance electrode line
The GL (or the first-stage scanning signal line GL) is connected to the common transparent pixel electrode (Vcom) ITO2 as shown in FIG. As shown in FIG. 2B, the common transparent pixel electrode ITO2 is connected to an external lead-out line by a silver paste material SL at a peripheral portion of the liquid crystal display device. In addition, some of the conductive layers (g1 and g2) of the external lead wiring are formed in the same manufacturing process as the scanning signal line GL. As a result, the last stage capacitor electrode line GL can be easily connected to the common transparent pixel electrode ITO2.

Alternatively, as shown by the dotted line in FIG. 8, the last (first) capacitor electrode line GL may be connected to the first (last) scanning signal line GL. This connection can be made by an internal wiring in the liquid crystal display unit or an external lead-out wiring.

<< DC Cancellation by Additional Capacitance Cadd Scanning Signal >> This liquid crystal display device is based on a DC cancellation system (DC cancellation system) described in Japanese Patent Application No. 62-95125 filed by the present applicant. As shown in the diagram (time chart), by controlling the drive voltage of the scanning signal line DL, the DC component applied to the liquid crystal LC can be further reduced. In FIG. 10, Vi is a drive voltage of an arbitrary scanning signal line GL, and Vi + 1 is a driving voltage of a scanning signal line GL at the next stage. Vee is a low-level driving voltage Vd min applied to the scanning signal line GL, and Vdd is a high-level driving voltage Vd max applied to the scanning signal line GL. Voltage changes ΔV _{1 to} ΔV ₄ of the midpoint potential Vlc (see FIG. 9) at each time t = t _{1 to} t ₄
Is as follows.

t = t ₁ : ΔV ₁ = − (Cgs / C) · V2 t = t ₂ : ΔV ₂ = + (Cgs / C) · (V1 + V2) − (Cadd / C)
・ V2 t = t ₃ : ΔV ₃ = − (Cgs / C) ・ V1 + (Cadd / C) ・ (V1 +
2V) t = t ⁴ : ΔV ₄ = − (Cadd / C) · V1 where the total capacitance of the pixels: C = Cgs + Cpix + Cadd Here, if the drive voltage applied to the scanning signal line GL is sufficient (see the following [ Note], the DC voltage applied to the liquid crystal LC is ΔV ₃ + ΔV ₄ = (Cadd · V2−Cgs · V1) / C. Therefore, if Cadd · V2 = CgS · V1, the DC voltage applied to the liquid crystal LC is It becomes 0.

Note: the time t _1, the variation of the scanning line Vi at t ₂ is affects the mid-point potential Vlc, mid-point potential Vlc during the period t ₂ ~t ₃ signal line X
The potential is set to the same as the video signal potential through i (sufficient writing of the video signal). The potential applied to the liquid crystal is almost determined by the potential immediately after the TFT is turned off (the TFT off period is much longer than the on period). Therefore, the calculation of the DC component applied to the liquid crystal, the period t ₁ ~t ₃ is almost negligible, TFT may be considered potential immediately after the off, i.e. the effect of the transient at time t _3, t _4. Note that the polarity of the video signal Vi is inverted for each frame or for each line, and the DC component due to the video signal itself is set to zero. In other words, the DC cancellation method uses the superposition capacity Cgs
The drive voltage applied to the storage capacitor Cadd and the next-stage scanning signal line GL (capacitance electrode line) pushes up the drop due to the pulling of the midpoint potential Vlc due to the above, and the DC component applied to the liquid crystal LC can be extremely small. it can. As a result, the liquid crystal display device can improve the life of the liquid crystal LC. Of course, when the gate GT is increased to increase the light blocking effect, the value of the storage capacitor Cadd may be increased accordingly.

<< Configuration of Scanning Signal Line, Video Signal Line, and Terminal >> FIG. 1A is a schematic plan view showing the scanning signal line or the video signal line and the terminal of the liquid crystal display device. FIG. 1B is a cross-sectional view of an example of a scanning signal line or a video signal line. FIG. 1C is a longitudinal sectional view of an example of a scanning signal line or a video signal line and a terminal. SUB1 is a lower transparent glass substrate, SUB2 is an upper transparent glass substrate, PSV1 is a protective film, GL or DL is a scanning signal line or a video signal line, and T is a terminal.

In the liquid crystal display device of the present embodiment, an Al layer or Al-Si is provided on the scanning signal lines or the video signal lines GL or DL inside the protective film PSV1.
Or an Al alloy such as Ai-Pd. On the other hand, the terminal T outside the protective film PSV1 does not contain Al.

Further, an Al layer or an Al alloy is used for the scanning signal line or the video signal line GL or DL, and the surface thereof is anodized to form an anodized film.

Also, scan signal lines or video signal lines GL or DL
(Lower layer) / Al (upper layer) or two layers of Ti / Al.

In addition, the scanning signal line or the video signal line GL or DL,
Two layers of Ta / Al are formed, and the surfaces of these two layers are anodized. FIG. 1B shows this embodiment. That is, Ta
Each of the anodized films Ta ₂ O ₅ and Al ₂ O ₃ is formed on / Al. Instead of Ta / Al, Ti / Al may be used.

The scanning signal line or the video signal line GL or DL may be composed of Cr / Al, but since Cr melts when anodized,
Cr is not anodized.

In addition, electric corrosion does not occur at the terminal T, and highly reliable Ta, Ti,
It is formed of Ta / ITO or Ti / ITO.

 Further, the terminal T is formed of Cr or Cr / ITO.

 The terminal T is formed of the ITO1 layer.

Further, the scanning signal line or the video signal line GL or DL is formed of Al, the terminal T is formed of Cr, and as shown in FIG. I do.
Al ₂ O ₃ is formed on Al by anodization, and Cr
Above is formed ITO. The lower layer may be made of Cr and the upper layer may be made of Al at the connection between the two.

In this embodiment, the scanning signal line or the video signal line is GL or
Since Al is used for DL, the resistance can be reduced. Further, since the terminal T is made of highly reliable Ta, Ti, ITO, Ta / ITO, Ti / ITO, Cr, and Cr / ITO without using Al which causes electrolytic corrosion, the reliability of the terminal can be improved. . In addition, by providing the anodic oxide film on the surface, it is possible to prevent a short circuit from occurring with a conductive film (such as a storage capacitor element or a signal line) present thereon. In addition, anodization of Ta ₂ O ₅ , Al ₂ O ₃ etc.
Since the film is translucent, it is possible to prevent the aperture ratio of the liquid crystal from being adversely affected. In addition, if a part that is not anodized is left in a part of the anodized film, the resistance of the signal line can be reduced.

FIG. 11A is a cross-sectional view of an example of a terminal portion of a scanning signal line, and FIG. 11B is a plan view of an example of a terminal portion of a scanning signal line. SUB1 is a lower transparent glass substrate, GTM is a gate terminal, d1 is a conductive film made of Cr, TML is a top film made of ITO,
GI is a gate insulating film, g1 is a conductive film made of Cr, and g2 is Al-P
d, a conductive film made of Al-Si, Al-Si-Ti, Al-Si-Cu or the like, and PSV1 is a protective film. The shape of the gate terminal,
A variety of layer configurations and the like can be used, and the materials of the layers can be the same as those described above.

FIG. 12A is a cross-sectional view of an example of a terminal portion of a video signal line, and FIG. 11B is a plan view of an example of a terminal portion of a video signal line. DTM is a drain terminal, d1 is a conductive film made of Cr, TML is an uppermost film made of ITO, d2 is Al-Pd, Al-Si, Al
A conductive film made of -Si-Ti, Al-Si-Cu, etc .; d3 a conductive film made of ITO; and g1 a conductive film made of Cr. Note that various shapes, layer configurations, and the like of the drain terminal portion can be used, and the materials of the layers can be the same as those described above.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Of course.

For example, various materials, layer configurations, connection portions between signal lines and terminals, and the like of the scanning signal lines, video signal lines, and terminals can be used without departing from the scope of the claims of the present invention.

Further, in this embodiment, an inverted staggered structure of gate electrode formation → gate insulating film formation → semiconductor layer formation → source / drain electrode formation has been described. is there.

〔The invention's effect〕

As described above, according to the present invention, the resistance of the scanning signal line or the video signal line can be reduced, the reliability of the terminal portion can be improved, the characteristics of the liquid crystal display device can be improved, and the yield can be improved. .

[Brief description of the drawings]

FIG. 1A is a schematic plan view showing a scanning signal line or a video signal line and a terminal of the liquid crystal display device. FIG. 1B is a cross-sectional view of an example of the scanning signal line or the video signal line. FIG. 1C is a longitudinal sectional view of an example of a scanning signal line or a video signal line and a terminal, and FIG. 2A is a view of a liquid crystal display section of an active matrix type color liquid crystal display device according to Embodiment I of the present invention. FIG. 2B is a cross-sectional view of a portion cut along the IIB-IIB cutting line of FIG. 2A and a peripheral portion of the seal portion, and FIG. 2C is a IIC of FIG. 2A. 3 is a cross-sectional view taken along section line C of FIG. 2, FIG. 3 is a plan view of a main part of a liquid crystal display unit in which a plurality of the pixels shown in FIG. 2A are arranged, and FIGS. FIG. 7 is a plan view showing only a predetermined layer of FIG. 7, and FIG. 7 is a plan view of the pixel electrode layer and the color filter layer shown in FIG. FIG. 8 is an equivalent circuit diagram showing a liquid crystal display unit of an active matrix type color liquid crystal display device, FIG. 9 is an equivalent circuit diagram of a pixel shown in FIG. 2A, FIG. Is a time chart showing the driving voltage of the scanning signal line by the direct current canceling method, FIG. 11 (A) is a cross-sectional view of an example of a terminal portion of the scanning signal line, and FIG. FIG. 12 (A) is a plan view of an example of a terminal portion of a video signal line, and FIG. 12 (B) is a plan view of an example of a terminal portion of a video signal line. In the figure, SUB1, 2 ... transparent glass substrate, CT ... connection terminal, MT ... measurement terminal, SL ... sealing material, PSV1 ... protective film, GL ... scanning signal line, DL ... video signal Line, T: Terminal, GI: Insulating film, GT: Gate electrode, AS: i-type semiconductor layer, SD: Source or drain electrode, PSV: Protective film, LS: Light shielding film, LC: … Liquid crystal, TFT… thin film transistor, ITO… transparent electrode, g, d… conductive film, Cadd… storage capacitance element, Cgs… superposition capacity, Cpix… liquid crystal capacity Is omitted).

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuo Shirahashi 3300 Hayano Mobara-shi, Chiba Pref. In the Mobara Plant, Hitachi, Ltd. (56) References JP-A-61-13227 (JP, A) JP-A-1-35421 (JP, A) JP-A-59-91756 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/1343 G02F 1/1345 G02F 1/136

Claims (4)

(57) [Claims] A plurality of scanning signal lines extending in a horizontal direction on an insulating substrate; a plurality of video signal lines provided on the scanning signal lines and intersecting the scanning signal lines; A pixel which is disposed in an intersection area between the signal line and the two adjacent video signal lines, the pixel including a thin film transistor and a pixel electrode as one component, and the scanning signal line is a Ta
And a second conductive film made of Al laminated on the first conductive film. The surfaces of the first conductive film and the second conductive film are formed by oxidation of the respective conductive films. A liquid crystal display device characterized by being covered with a film. 2. The liquid crystal display device according to claim 1, wherein said scanning signal line has a width dimension of said second conductive film substantially smaller than a width dimension of said first conductive film. 3. A plurality of scanning signal lines extending in a horizontal direction on an insulating substrate; a plurality of video signal lines provided on the scanning signal lines and intersecting with the scanning signal lines; A pixel is disposed in an intersection area between a signal line and two adjacent video signal lines, the pixel including a thin film transistor and a pixel electrode as one component, and the scanning signal line is a Ti
And a second conductive film made of Al laminated on the first conductive film. The surfaces of the first conductive film and the second conductive film are formed by oxidation of the respective conductive films. A liquid crystal display device characterized by being covered with a film. 4. The liquid crystal display device according to claim 3, wherein said scanning signal line has a width dimension of said second conductive film substantially smaller than a width dimension of said first conductive film.