JPH02245738A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent a line defect and a point defect from occurring by making at least the width of the (i) type semiconductor layer of a source electrode part and a drain electrode part larger than that of a scanning signal line. CONSTITUTION:The (i) type semiconductor layer AS 1 and an insulating film GI are provided all over the surface of a liquid crystal display part and an electrode PL 11 which constitutes a retension volume element Cadd with a transparent picture element electrode ITO 1 is provided to protrude from an adjacent scanning signal line GL. Since the (i) type semiconductor layer AS 1 and the insulating film GI are provided all over the surface of the liquid crystal display part, surface leakage current is not caused from the edges of the scanning signal line GL and the gate electrode GT. The scanning signal line GL, the gate electrode GT, a source electrode SD 1 and the drain electrode SD 2 do not short-circuit, so that the line defect and the point defect are prevented from occurring. Thus, a liquid crystal display device where the line defect and the point defect are prevented from occurring is obtained.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a liquid crystal display device, and particularly to an active matrix type liquid crystal display device using thin film transistors and the like.

[Conventional technology]

Active matrix liquid crystal display devices are
A nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a grid shape. Theoretically, the liquid crystal in each pixel is constantly driven (duty ratio 1.0), so compared to the so-called simple matrix method that uses a time-division drive method, the active method has better co-contrast, especially in color. A thin film transistor (TPT) is a typical switching element that is becoming an indispensable technology. Figure 11 shows a conventional active matrix liquid crystal display device (Japan Display '86).
DISPLAY '86) Pages 332 and 333) A plan view showing a part of the liquid crystal display section, Figure 12 is A of Figure 11.
- A sectional view taken along the A cutting line, Figure 13 is B- in Figure 11.
In figure 0, which is a cross-sectional view along section line B, 5UBI
is a lower transparent glass substrate, dll is an ITo film (transparent conductive film), don is an N+ type semiconductor layer made of N+ type amorphous silicon, ASI is an i-type semiconductor layer made of i-type amorphous silicon, and GI is an i-type semiconductor layer made of i-type amorphous silicon. Insulating film used as gate insulating film,
gll is a conductive film made of aluminum, GL is a scanning signal line, GT is a gate electrode, DL is a video signal line, SDl is a source electrode, Sn2 is a drain electrode, and ITOI is a transparent pixel electrode. To manufacture this liquid crystal display device, ITOlldll,
An N+ type semiconductor layer do1 is provided, and ITOlldll, N+
By selectively etching the type semiconductor layer do1, the video signal line DL, source electrode SDI, drain electrode S
D2, after forming the transparent pixel electrode ITo1, the i-type semiconductor layer ASI, the insulating film GI, and the conductive film gll are provided, and the i-type semiconductor layer AS1, the insulating film GI, and the conductive film gll are selectively etched to perform scanning. Since it is only necessary to form the signal line GL and the gate electrode GT, it is possible to manufacture the device very easily.

[The problem that the invention attempts to solve]

However, in such a liquid crystal display device, surface leakage current from the edges of the scanning signal line GL and gate electrode GT short-circuits the scanning signal line GL and gate electrode GT with the source electrode SDI and drain electrode SD2, causing the line to become short-circuited. It becomes a defect, a point defect. In addition, the gate electrode GT and the source electrode SDI
Since a superimposed capacitance is formed by the drain voltage f&SD2, a DC component is added to the liquid crystal, and black spots and black unevenness defects may occur. The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a liquid crystal display device that is free from line defects, one-point defects, and a liquid crystal display device that is free from black spots and black unevenness defects. purpose.

[Means to solve the problem]

In order to achieve this object, in the present invention, a thin film transistor and a pixel electrode are used as constituent elements of a pixel, the pixel electrode, the video signal line, the source electrode, and the drain electrode are formed of the same transparent conductive film, and the thin film transistor and the pixel electrode are formed of the same transparent conductive film. An active matrix method in which an N+ type semiconductor layer is provided on the electrode and the drain electrode, a scanning signal line is formed on it, and an i-type semiconductor layer and an insulating film serving as a gate insulating film are provided below the scanning signal line. In the liquid crystal display device, the width of the i-type semiconductor layer at least in the source electrode portion and the drain electrode portion is made larger than the width of the scanning signal line. Moreover, in order to achieve the above object, in this invention,
The thin film transistor and the pixel electrode are considered as one component of the pixel, the pixel electrode, the video signal line, the source electrode, and the drain electrode are formed of the same transparent conductive film, and an N+ type semiconductor layer is formed on the source electrode and the drain electrode. A scanning signal line is formed thereon, and an i-type semiconductor layer and an insulating film serving as a gate insulating film are provided below the scanning signal line.
In a matrix type liquid crystal display device, an electrode is provided which together with the pixel electrode constitutes a storage capacitor element.

[Effect]

In this liquid crystal display device, since the width of the i-type semiconductor layer at least in the source electrode portion and the drain electrode portion is larger than the width of the scanning signal line, surface leakage current from the edges of the scanning signal line and the gate electrode is reduced. This does not occur, and the scanning signal line, gate electrode, source electrode, and drain electrode are never short-circuited. In addition, in the above-mentioned liquid crystal display device, since an electrode is provided which together with the pixel electrode constitutes a storage capacitance element, even if a superimposed capacitance is formed between the gate electrode and the source electrode, a direct current component does not flow into the liquid crystal. I never join.

【Example】

An active matrix color liquid crystal display device to which the present invention is applied will be described below. Note that in all the figures for explaining the liquid crystal display device, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. FIG. 2A is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross section taken along the nB-nB cutting line in FIG. 2A and a plan view of the display panel. 2C is a cross-sectional view taken along the nc-nc line in FIG. 2A; FIG. Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged. (Pixel Arrangement) As shown in Figure 2A, each pixel is connected to two adjacent scanning signal lines (gate signal line or horizontal signal line) OL and two adjacent video signal lines g (drain signal line or vertical signal line). Signal line)
Within the intersection area with DL (within the area surrounded by four signal lines)
It is located in Each pixel includes a thin film transistor TPT, a pixel electrode IT○1, and an additional capacitor Cadd. A plurality of scanning signal lines GL extend in one column direction and are arranged in plural lines in a row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. (Overall panel cross-sectional structure) As shown in FIG. 2B, a thin film transistor TPT and a transparent pixel electrode ITOI are formed on the lower transparent glass substrate 5UBI side with respect to the liquid crystal layer LC, and a color filter is formed on the upper transparent glass substrate 5UBZ side. FIL and a light-shielding black matrix pattern BM are formed. The lower transparent glass substrate 5UBl side is configured to have a thickness of, for example, about 1.1 cm. The central part of Figure 2B shows a cross section of one pixel,
The left side shows a cross section of the left edge portion of the transparent glass substrates 5UBI and 5UB2 where external lead wiring is present. The right side shows a cross section of the right edge portion of the transparent glass substrates 5UBI and 5UB2 where no external lead wiring is present. The sealing material SL shown on the left and right sides of FIG. 2B is configured to seal the liquid crystal LC, and is configured to seal the entire periphery of the transparent glass substrates 5UBI and 5UB2 except for the liquid crystal sealing opening (not shown). is formed along. The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate 5UB2 is connected to an external lead wiring formed on the side of the lower transparent glass substrate 5UBI with a silver paste material SIL at at least one place. This external lead wiring is formed in the same manufacturing process as each of the gate electrode GT, source electrode SDI, and drain electrode SD2 described above. Alignment films 0RII and 0RI2, transparent pixel electrode ITO,
Common transparent pixel electrode ITO1 protective film psv1 and PSV
2. Each layer of the insulating film GI is formed inside the sealing material SL. The polarizing plate POL has a lower transparent glass substrate 5
UBI is formed on each outer surface of the upper transparent glass substrate 5UB2. Liquid crystal LC has a lower alignment film ○R that sets the direction of liquid crystal molecules.
II and the upper alignment film 0RI2, and sealed by a sealing portion SL. The lower alignment film 0RII is formed on the protective film PSVI on the side of the lower transparent glass substrate 5UBI. On the inner surface (liquid crystal side) of the upper transparent glass substrate 5UB2, a light shielding film BM, a color filter FIL, and a protective film PSV are provided.
2. A common transparent pixel electrode (COM) ITO2 and an upper alignment film 0RI2 are sequentially laminated. This liquid crystal display device has a lower transparent glass substrate 5UBl side,
Each layer on the upper transparent glass substrate 5UB2 side is formed separately, and then the upper and lower transparent glass substrates 5UBI and 5
It is assembled by overlapping the UB2 and sealing the liquid crystal LC between them. (Thin film transistor TFT> The thin film transistor TPT operates so that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large.Thin film transistor of each pixel TPT is 3 within a pixel.
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFTI, TPT2, and TPT3. Each of the thin film transistors TPTI to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPTI to TFT3 mainly includes a gate electrode GT, a gate insulating film GI, an i-type (intrinsic, 1ntrins)
ic, an i-type semiconductor layer As made of amorphous silicon (Si) (not doped with conductivity type determining impurities), and a pair of source electrode SD1 and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in a single display device circuit, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. It is expressed by fixing the source and the other as the drain. (Gate Electrode GT) As shown in detail in FIG. 4 (a plan view depicting only the layers g1, g2, and As in FIG. 2A), the gate electrode GT is connected in a vertical direction from the scanning signal line GL (in FIG. 2A and It is constructed in a shape that protrudes upward (in FIG. 4) (branched into a T-shape). Gate electrode GT is thin film transistor TPTI~TFT
It is configured to protrude to each formation region of No. 3. The respective gate electrodes GT of the thin film transistors TPT1 to TFT3 are integrated (as a common gate electrode).
It is formed continuously with the scanning signal line GL. The gate electrode GT is formed of a single-layer first conductive film g1 so as not to form a large step in the formation region of the thin film transistor TPT. The first conductive film g1 is made of, for example, a chromium (Cr) film formed by sputtering.
It is formed with a film thickness of about 0 [person]. This gate electrode GT is shown in FIGS. 2A, 2B and 4.
As shown in the figure, it is formed to be thicker than the semiconductor layer AS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is installed below the substrate 5UBI, this opaque Cr gate electrode GT
becomes a shadow, and the semiconductor layer AS is not irradiated with backlight light, making it difficult for the conductive phenomenon caused by light irradiation, that is, deterioration of the off-characteristics of TPT, to occur. The original size of the gate electrode GT is the minimum width required to span between the source/drain electrodes SDI and SD2 (including the alignment margin between the gate electrode and the source/drain electrodes), and the channel width. The depth length that determines W is determined by the ratio to the distance 1 (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance gm. The size of the gate electrode in this embodiment is of course larger than the original size mentioned above. Considering only the gate and light shielding functions of the gate electrode GT, the gate electrode GT and the scanning signal line GL may be integrally formed in a single layer, and in this case, Si is contained as an opaque conductive material. AI, pure AI, A1 containing Pd, etc. can be selected. (Scanning Signal Line GL) The scanning signal IGL is composed of a composite film including a first conductive film g1 and a second conductive film g2 provided on the first conductive film g1. The first conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally. The second conductive film g2 is formed using, for example, an aluminum film formed by sputtering. It is formed with a film thickness of about 5,500 [people]. Second conductive film g
2 is configured to reduce the resistance value of the scanning signal line GL and increase the signal transmission speed (improve the writing characteristics of pixel information). Further, in the scanning signal line GL, the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL has a gradual step shape on its side wall. (Gate insulating film GI> The insulating film GI is used as a gate insulating film for each of the thin film transistors TPTI to TFT3. Insulating film GI
is formed in the upper layer of the gate electrode GT and the scanning signal line GL. The insulating film Gl is formed by, for example, plasma CVD.
A silicon nitride film formed using the above method is used to form a film with a thickness of about 3000 [layers]. (Semiconductor Layer As) As shown in FIG. 4, the i-type semiconductor layer AS is used as a channel forming region for each of the plurality of thin film transistors TPTI to TFT3. i-type semiconductor layer A
s is formed of an amorphous silicon film or a polycrystalline silicon film, and is formed to have a film thickness of about 1800 C. This i-type semiconductor layer AS is made of Si by changing the components of the supplied gas.
, N, are formed in the same plasma CVD apparatus following the formation of the gate insulating film GI, without being exposed to the outside from the apparatus. Also, P for ohmic contact
N+ layer d doped with . (Fig. 2B) is similarly formed continuously to a thickness of about 400 [people]. After that, the lower substrate 5UBI is taken out from the CvD device and processed by photo processing technology. The N+ layer do and one layer As are patterned into independent islands as shown in FIGS. 2A, 2B, and 4. As shown in detail in FIGS. 2A and 4, the i-type semiconductor layer As is also provided between the scanning signal line GL and the video signal line DL at an intersection (crossover section). The intersection i-type semiconductor layer AS is configured to reduce short circuits between the scanning signal line GL and the video signal line DL at the intersection. (Source/drain electrode SDI, 5D2) The source electrode SDI and drain electrode SD2 of each of the thin film transistors TPTI to TFT3 divided into a plurality of parts are shown in FIGS. 2A, 2B, and 5 (layers d1 to 5D2 in FIG. 2A). As shown in detail in the plan view (plan view depicting only d3), they are provided spaced apart from each other on the semiconductor layer As. Each of the source electrode SDI and drain electrode SD2 is
A first conductive film d1, a second conductive film d2, and a third conductive film d3 are sequentially stacked one on top of the other from the lower layer side in contact with the N+ type semiconductor layer do. First conductive film d of source electrode SDI
1. The second conductive film d2 and the third conductive film d3 are formed in the same manufacturing process as the drain electrode SD2. The first conductive film d1 is a chromium film formed by sputtering, and has a film thickness of 500 to 1000 [people] (in this example, 6
The film thickness is approximately 0.00 [person]. When forming a chromium film thicker, the stress increases, so 2000
Form the film within a range that does not exceed the thickness of a [person]. The chromium film has good contact with the N+ type semiconductor layer do. The chromium film constitutes a so-called barrier layer that prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer dO. In addition to the chromium film, the first conductive film d1 may include a refractory metal (Mo, Ti, Ta, W) film, a refractory metal silicide (
It may be formed using a MoSiz, TiSi, TaSi, WSi, etc. film. After patterning the first conductive film d1 by photo processing, the N+ layer do is removed using the same photo processing mask or using the first conductive film d1 as a mask. In other words, the portion of the N+ layer dO remaining on the i 1llA S except for the first conductive film d1 is removed by the self-alignment. At this time, since the N+ layer dO is etched to remove its entire thickness, the first As layer is also slightly etched on its surface, but the extent can be controlled by the etching time. Thereafter, the second conductive film d2 is formed by aluminum sputtering to a thickness of 3,000 to 5,500 [people] (in this example, a film thickness of about 3,500 [people]). The aluminum film has less stress than the chromium film, can be formed thicker, and is configured to reduce the resistance values of the source electrode SDI, drain electrode SD2, and video signal line DL. In addition to the aluminum film, the second conductive film d2 may be formed of an aluminum film containing silicon (Si) or copper (Cu) as an additive. After patterning the second conductive film d2 using a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Induim-T) formed by sputtering.
in-Oxide ITO: consists of 1
Film thickness of 000 to 2000 [people] (in this example, 12
It is formed with a film thickness of about 0.00 [person]. This third conductive film d3 constitutes the source electrode SDI, drain electrode SD2, and video signal line DL, and also forms the transparent pixel electrode ITO.
It is designed to constitute I. First conductive film d1 of source electrode SDI, drain electrode SD
Each of the two first conductive films d1 has an upper second conductive film d1.
The conductive film d2 and the third conductive film d3 extend further inward (into the channel region). In other words, the first conductive film d1 in these parts is configured to be able to define the gate length of the thin film transistor TPT independently of the layers d2 and d3. As described above, the source electrode SDI is connected to the transparent pixel electrode IT.
Connected to OI. The source electrode SDI has a step shape of the i-type semiconductor layer AS (the thickness of the first conductive film g1, the thickness of the N+ layer d
It is configured along a step corresponding to the sum of the film thickness of O and the film thickness of the i-type semiconductor layer AS. Specifically, the source voltage 15DI is connected to the first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and to the transparent pixel electrode ITOI above the first conductive film d1. A third conductive film d3 is connected to a second conductive film d1 whose side is smaller in size. The second conductive film d2 of the source electrode SDI is. Since the chromium film of the first conductive film d1 cannot be formed thickly due to increased stress and cannot overcome the stepped shape of the i-type semiconductor layer AS, the first conductive film d1 is configured to overcome the step shape of the i-type semiconductor layer AS. In other words, the step coverage is improved by forming the second conductive film d2 thickly. Since the second conductive film d2 can be formed thickly, it greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). Since the third conductive film d3 cannot overcome the step shape caused by the i-type semiconductor layer AS of the second conductive film d2, by reducing the size of the second conductive film d2, the exposed first conductive film d1 configured to connect. The first conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connecting portion between them, so that they can be reliably connected. (Pixel electrode I To 1> The transparent pixel electrode ITOI is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section.The transparent pixel electrode ITOI is a thin film transistor TPTI that is divided into a plurality of pixels. It is divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of ~TFT3. Each of the transparent pixel electrodes E1 to E3 is a thin film transistor TPT.
is connected to the source electrode SDI of. Each of the transparent pixel electrodes E1 to E3 is patterned to have substantially the same area. In this way, by dividing the thin film transistor TPT of one pixel into a plurality of thin film transistors TPT1 to TFT3, and connecting each of the plurality of divided transparent pixel electrodes E1 to E3 to each of the plurality of divided thin film transistors TPT1 to TFT3. Even if a divided portion (for example, TFT1) becomes a point defect, it is no longer a point defect when viewed as a whole in one pixel (TFT2 and TFT3 are not defective), so the probability of point defects can be reduced. , it can also make defects more difficult to see. Further, by configuring each of the divided transparent pixel electrodes E1 to E3 of the pixel to have substantially the same area, each of the transparent pixel electrodes E1 to E3 and the common transparent pixel electrode I
Each liquid crystal capacitor (Cpix
) can be made uniform. (Protective film PSVI> A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode TTOI. The protective film PSVI is mainly formed to protect the thin film transistor TPT from moisture etc. The protective film PSVI is made of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD.
Formed with a film thickness of about [a person]. (Light-shielding film BM> A shielding film BM is provided on the upper substrate 5UBZ side to prevent external light (light from above in FIG. 2B) from entering the i-type semiconductor layer As used as a channel formation region, The pattern is as shown by the hatching in Fig. 6. In addition, Fig. 6 shows the ITO film layer d3 in Fig. 2A,
FIG. 3 is a plan view depicting only a filter layer FIL and a light shielding film BM. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film that has a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300 mm. Therefore, the common semiconductor layer AS of TPTI~3 is sandwiched between the upper and lower light shielding films BM and the thick gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light shielding film BM is formed around the pixel as shown by the hatched area in FIG. There is. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM is
2. Light shielding for semiconductor layer As and black matrix
It has two functions. In addition, the backlight is attached to the 5UB2 side, and the 5UBI
can also be set as the observation side (externally exposed side). (Common electrode IT○2) The common transparent pixel electrode ITO2 is connected to the lower transparent glass substrate 5U.
Opposing the transparent pixel electrode ITOI provided for each pixel on the Bl side, the optical state of the liquid crystal changes in response to the potential difference (electric field) between each pixel electrode ITOI and the common electrode IrO2. This common transparent pixel electrode IT○2 has a common voltage Vco
m is applied. Common voltage Vc
om is a low level drive voltage V d win and a high level drive voltage V d w applied to the video signal line DL.
This is the intermediate potential between ax and ax. (Color Filter FIL) The color filter FIL is configured by coloring a dyed base material made of a resin material such as an acrylic resin with a dye. The color filter FIL is formed in a dot shape for each pixel at a position facing the pixel (FIG. 7), and is colored differently (FIG. 7 shows the third conductive film layer d3 and color filter J' in FIG. 3). 1 FIL is drawn, and each of the R, G, and H filters is 45° 135°, with a cross hatch), and the color filter FIL is connected to the pixel electrode ITOI (El~ The light shielding film BM is formed to be thick so as to cover all of the pixel electrode ITOI, and the light shielding film BM is formed inside the peripheral part of the pixel electrode ITOI so as to overlap with the color filter FIL and the edge part of the pixel electrode ITOI. The color filter FIL can be formed in a linear manner. First, a dyed base material is formed on the surface of the upper transparent glass substrate 5UB2, and the dyed base material other than the red filter forming area is removed using photolithography technology. Thereafter, the dyed base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R.The same process is then performed to sequentially form a green filter G and a blue filter B. (Protective Film PSV2) The protective film PSV2 is provided in order to prevent the dyes used to dye the color filters FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is, for example,
It is made of transparent resin material such as acrylic resin or epoxy resin. (Pixel Arrangement) As shown in FIGS. 3 and 7, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal line GL extends, and pixel columns Xi, X2°X3 ．． X4. ...
It consists of each of the following. Each pixel column Xi, X2. X3
．． X4. . . . have thin film transistors TFTI to TFT3 and transparent pixel electrodes E1 to E3 arranged in the same position. In other words, odd pixel row Xi
,X3. For each pixel, the thin film transistors TPTI to TFT3 are arranged on the left side, and the transparent pixel electrode E is placed on the left side.
1 to E3 are arranged on the right side. Odd pixel row Xi. X3. Each adjacent even-numbered pixel column X in the row direction
2. X4. Each pixel of ... is an odd pixel column X1
,X3. ... are connected to the video signal line DL.
It is composed of pixels that are symmetrical and upside down with respect to the direction in which it extends. That is, the pixel row X2°X4. ...
Each pixel of thin film transistors TPTI to TF
The arrangement position of T3 is arranged on the right side, and the arrangement position of transparent pixel electrodes E1 to E3 is arranged on the left side. Then, pixel row X2. X4. Each pixel in pixel rows Xi, X3 . For each pixel of...
They are shifted (shifted) by half a pixel interval in the column direction. In other words, each pixel interval of pixel row X is set to 1.0 (1,0
Pitch), the next pixel row X has a pixel interval of 1
．． 0, and is shifted by 0.5 pixel interval (0.5 pitch) in the column direction with respect to the previous pixel column X. The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X. As a result, as shown in FIG. 7, the pixels in the previous pixel row Pixels on which same-color filters are formed (for example, pixel row
4) are spaced apart by 1.5 pixel intervals (1.5 pitch), and the RGB color filters FIL are arranged in a triangle. Color filter F
The triangular arrangement structure of the IL ROBs can improve the mixing of each color, and therefore can improve the resolution of a color image. Further, since the video signal line DL extends in the column direction by only a half pixel interval between each pixel column X, it does not intersect with the adjacent video signal $1DL. Therefore, it is possible to eliminate the routing of the video signal line DL and reduce the area occupied by the video signal line DL, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. (Equivalent circuit of the entire display panel) An equivalent circuit of this liquid crystal display device is shown in FIG. X iG + X x + I G t... is a video signal line D connected to the pixel where the green filter G is formed.
It is L. XiB, Xi+IB, . . . are video signal lines DL connected to the pixels in which the blue filter B is formed. Xi+IR, Xi+2R, - are video signals @DL connected to the pixels in which the red filter R is formed. These video signal lines DL are selected by a video signal duplex circuit. Yi is a scanning signal line GL that selects the pixel column X1 shown in FIGS. 3 and 7. Similarly, Y i + 1, Y x + 2 y...
. . , each of the pixel rows X2 . X3. . . . is a scanning signal line GL that selects each of the following. These scanning signal lines GL are connected to a vertical scanning circuit. (Structure of additional capacitance Cadd) Each of the transparent pixel electrodes E1 to E3 is bent into an L-shape so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TPT. It is formed. As is clear from FIG. 2C, in this superposition, each of the transparent pixel electrodes E1 to E3 is used as one electrode PL2, and the adjacent scanning signal line GL is used as the other electrode P.
A holding capacitance element (capacitance element) Cadd is configured as LI. The dielectric film of this storage capacitor element Cadd is an insulating film GI used as a gate insulating film of the thin film transistor TPT.
It is composed of the same layer. As is clear from FIG. 4, the storage capacitor Cadd is formed in the widened portion of the first layer g1 of the gate line OL. Note that the portion of the layer g1 that intersects with the drain line DL is made thin in order to reduce the probability of short circuit with the drain line. Each of the transparent pixel electrodes E1 to E3 and the capacitor electrode line (gl
), similar to the source electrode SDI,
In order to prevent the transparent pixel electrode IT○1 from disconnecting when climbing over the stepped shape, the first conductive! l1dl and second conductive film d
An island area consisting of 2 is provided. This island region is configured to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITOI. (Equivalent circuit of additional capacitance Cadd and its operation) The equivalent circuit of the pixel shown in FIG. 2A is shown in FIG. 9. In FIG. 9, Cgs is the gate electrode GT of the thin film transistor TPT.
and a parasitic capacitance formed between source electrode SD1. The dielectric film of the parasitic capacitance Cgs is an insulating film GI*C
pix is a liquid crystal capacitance formed between the transparent pixel electrode ITOI (PIX) and the common transparent pixel electrode TO2 (COM). The dielectric film of the liquid crystal capacitor Cpix is the liquid crystal LC1 protective film PSV.
I and alignment films 0RII and 0RI2. vlc is the midpoint potential. The storage capacitor element Cadd works to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the TFT switches. This situation can be expressed by the formula ΔV lc = (Cgs/ ( Cgs+Cadd+C
pix) ) XΔVg. Here, ΔVlc is ΔV
This change ΔVl represents the change in midpoint potential due to g
c causes the DC component applied to the liquid crystal, but the holding capacity C
The larger add is, the smaller the value can be. In addition, the holding capacitor Cadd also has the effect of lengthening the discharge time, so that video information is stored for a long time after the TPT is turned off. The reduction of the DC component applied to the liquid crystal LC is
It is possible to improve the lifespan of C and reduce so-called burn-in, in which the previous image remains when switching liquid crystal display screens. As mentioned above, since the gate electrode GT is enlarged to completely cover the semiconductor layer AS, the overlapping area with the source/drain electrodes SDI and Sn2 increases, and therefore the parasitic capacitance Cgs increases, and the midpoint potential v1c increases. This has the opposite effect of becoming more susceptible to the influence of the gate (scanning) signal Vg. However, by providing the holding capacitor Cadd, this disadvantage can also be eliminated. The storage capacitance of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4・Cp
ix (Cadd<8・Cpix), 8 to 32 times the superposition capacitance Cgs (8・Cgs<Cadd
Set to a value of about <32 Cgs). (Connection method of additional capacitance Cadd electrode line) As shown in FIG. ) Connect to IrO2. As shown in FIG. 2B, the common transparent pixel electrode ITO2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Moreover, some of the conductive layers (gl and g2) of this external lead wiring are formed in the same manufacturing process as the scanning signal line GL. As a result, the capacitor electrode line GL at the final stage can be easily connected to the common transparent pixel electrode (2) T2. Alternatively, as shown by the dotted line in FIG. 8, the capacitor electrode line GL at the final stage (first stage) may be connected to the scanning signal line GL at the first stage (final stage). This can be done by wiring or external wiring. (DC component offset by additional capacitance Cadd scanning signal) This liquid crystal display device uses the DC offset method (DC
As shown in FIG. 10 (time chart), the DC component applied to the liquid crystal LC can be further reduced by controlling the drive voltage of the scanning signal line DL. In FIG. 10, Vi is the driving voltage of an arbitrary scanning signal line OL, Vi+1 is the driving voltage of the scanning signal line GL in the next stage, aV e is the driving voltage of the scanning signal line G
A low-level active voltage Vd+++in applied to L,
Vdd is a high-level drive voltage V d wax applied to the scanning signal line GL. Each time 1=11-t. The voltage change Δ of the midpoint potential Vlc (see Figure 9) at
V engineering~Δv4 is as follows. ΔV x = (Cgs / C) ・V 2ΔV,
= + (Cgs/C)・(V 1 + V 2 )
−(Cadd/C)・V2 ΔV3=−(Cgs/C)・Vl +(Cadd/C)(V1+V2) ΔV,= −(Cadd/C)・V Also, total capacitance of pixels: C= Cgs 10Cpix+Cadd Here, if the active voltage applied to the scanning signal line GL is sufficient (see below)

(See note), the DC voltage applied to the liquid crystal LC is Δv3+ΔV4= (Cadd-V 2- Cgs-V
1)/C, so + Cadd-■2 = C
When gs-V is 1, the DC voltage applied to the liquid crystal LC is O
become. [Note] At times t□ and t2, the change in the scanning line Vi affects the midpoint potential Vlc, but during the period from t2 to t, the midpoint potential Vlc is made the same potential as the video signal potential through the signal line Xi. (enough writing of video signal). The potential applied to the liquid crystal is almost determined by the potential immediately after the TPT is turned off (the TPT off period is overwhelmingly longer than the on period).Therefore, the calculation of the direct current applied to the liquid crystal is based on the period t1 to t. Almost negligible, the potential immediately after TPT is turned off,
That is, it is only necessary to consider the influence during the transient period at times t1 and t4. Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero. In other words, the DC cancellation method uses the drive voltage applied to the storage capacitor element Cadd and the next scanning signal line GL (capacitive electrode line) to push up the drop caused by the pull-in of the midpoint potential Vlc by the superimposed capacitor Cgs, and The DC component applied to the LC can be made extremely small. As a result, the life of the liquid crystal LC of the liquid crystal display device can be improved. Of course, if the gate GT is increased in size to improve the light shielding effect, the value of the storage capacitor Cadd may be increased accordingly. FIG. 1A is a plan view showing a part of the liquid crystal display section of the liquid crystal display device according to the present invention, and FIG. 1B is a view taken along line IB-IB of FIG. 1A. In this liquid crystal display device, the i-type semiconductor layer A
SI and an insulating film GI are provided on the entire surface of the liquid crystal display section, and a storage capacitor element Cadd is formed with the transparent pixel electrode ITOI.
The electrode PLII that constitutes the scanning signal line GL is provided to protrude from the adjacent scanning signal line GL. In this liquid crystal display device, since the i-type semiconductor layer AS1 and the insulating film GI are provided over the entire surface of the liquid crystal display section, surface leakage current from the edges of the scanning signal line GL and gate electrode GT does not occur. Since the scanning signal line GL, gate electrode GT, source electrode SDI, and drain electrode SD2 are never short-circuited, line defects and point defects do not occur. In addition, since the electrode PLII which should constitute the storage capacitance element Cadd with the transparent pixel electrode IT○ is provided, even if a superimposed capacitance is formed between the gate electrode GT, the source electrode SDI, and the drain electrode SD2, the liquid crystal LC Since no direct current component is added to the process, black stains and black unevenness defects will not occur. Next, a method for manufacturing the liquid crystal display device shown in FIGS. 1A and 1B will be described. First, a film thickness of 3 is applied to a lower transparent glass substrate 5UBI made of 7059 glass (product name).
00~1200 [human analogy 1f1200 [A] (7)
Amorphous TOwAd11 is provided by sputtering. Next, hydrogen gas and phosphine gas were introduced into the plasma CVD apparatus, and a film thickness of 400 [human amorphous N1
A mold silicon film do1 is provided. Next, a resist pattern for forming a transparent pixel electrode ITO1, a drain wiring DL, a drain terminal (not shown), a source electrode SDI, and a drain electrode SD2 is formed by photolithography, and then SF, CCQ4 is used as a dry etching gas. Use N
The +-type silicon film do1 is selectively etched, and a mixed acid of hydrochloric acid and nitric acid is used as an etching solution.
Selectively etch TOgId 11. next,
After removing the resist, silane gas and hydrogen gas are introduced into the plasma CVD equipment to achieve a film thickness of 400 to 3000 [
After forming an i-type semiconductor layer ASI on the entire surface of the liquid crystal display section by providing an amorphous i-type silicon film of
Ammonia gas, silane gas, and nitrogen gas are introduced into the VD apparatus, and a silicon nitride film with a film thickness of 3500 mm is provided to form an insulating film GI over the entire surface of the liquid crystal display section. Next, the film thickness is 1,000 to 2,500 [people], for example, 2,500 [people].
A conductive film Gll made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, etc. is provided by sputtering. Next, the conductive film d is etched using photolithography using a mixed acid of phosphoric acid, nitric acid, and acetic acid as an etching solution.
By selectively etching ll, a scanning signal line GL, a gate terminal (not shown), and an electrode PLII are formed. Next, ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a film thickness of 1 [l1m]. Next, the silicon nitride film is selectively etched by photolithography using SF as a dry etching gas to form a protective film (not shown) and expose the gate terminal and drain terminal. The invention made by the present inventor has been specifically explained based on the above embodiments, but this invention is as follows. It goes without saying that the invention is not limited to the embodiments described above, and that various changes can be made without departing from the spirit thereof. For example, in the above embodiment, the i-type semiconductor layer ASI
Although the insulating film GI is provided on the entire surface of the liquid crystal display section, at least the i-type semiconductor layer A of the source electrode section and the drain electrode section is provided.
The widths of SI and insulating film GI may be made larger than the width of scanning signal line GL.

【Effect of the invention】

As explained above, in the liquid crystal display device according to the present invention, at least the i
Since the width of the semiconductor layer is larger than the width of the scanning signal line, surface leakage current from the edges of the scanning signal line and gate electrode will not occur, and the width of the scanning signal line, gate electrode, source electrode, and drain electrode will not occur. Since there is no short circuit between the two, line defects and point defects do not occur. Further, in the liquid crystal display device according to the present invention, since the electrode is provided which should constitute a storage capacitor element with the pixel electrode, even if a superimposed capacitance is formed between the gate electrode and the source electrode, direct current is applied to the liquid crystal. Since no ingredients are added,
No black spots or black uneven defects occur. As described above, the effects of this invention are remarkable.

[Brief explanation of drawings]

FIG. 1A is a plan view showing a part of the liquid crystal display section of the liquid crystal display device according to the present invention, FIG. 1B is a diagram IB-IB of FIG. 1A, and FIG. 2A is an active matrix type to which the present invention is applied. FIG. 2B is a plan view of a main part showing one pixel of a liquid crystal display section of a color liquid crystal display device, and FIG. 2B is a plan view of IIB-nB of FIG. 2A.
Cross-sectional view of the part cut along the cutting line and the area around the seal part, No. 2C
The figure is a cross-sectional view taken along the nc-nc cutting line in figure 2A,
The figure is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2A are arranged, FIGS. 4 to 6 are plan views depicting only a predetermined layer of pixels shown in FIG. 2A, and FIG. FIG. 3 is a plan view of the main parts in a state where only the pixel electrode layer and the color filter layer are superimposed, FIG. 8 is an equivalent circuit diagram showing the liquid crystal display section of an active matrix color liquid crystal display device, Fig. 9 is an equivalent circuit diagram of the pixel shown in Fig. 2A, Fig. 10 is a time chart showing the drive voltage of the scanning signal line by the DC cancellation method, and Fig. 11 is a conventional active matrix liquid crystal display device. 12 is a sectional view taken along the line AA in FIG. 11, and FIG. 13 is a sectional view taken along the line BB in FIG. 11. SUB...Transparent glass substrate GL...Scanning signal line DL...Video signal line GI/1fiJll film GT...Gate electrode AS...I-type semiconductor layer SD...Source electrode or drain electrode psv...・・・
Protective film BM...Light shielding film LC...Liquid crystal TPT...Thin film transistor IT○...Transparent pixel electrode g+d...Conductive film Cadd...Holding capacitor element Cgs...Superimposed capacitance Cpix... Liquid crystal capacitance No. 1A Do L I' / Book 51 1 PLI + - 1 electrode 1B diagram ITO + - - - - - - 1 price day / month 1 yen 1 kasumi ne 1 dOI -
------N+ type calf 4 (ice layer dll ---1--I
TO membrane GL---L*I number, line GL------Kitai sacrificial PLII----one electrode (Ko gruel 9 figure Ll 12 tj t4

Claims (1)

[Claims] 1. A thin film transistor and a pixel electrode are used as constituent elements of a pixel, and the pixel electrode, the video signal line, the source electrode, and the drain electrode are formed of the same transparent conductive film, and the source electrode,
An active matrix method in which an N^+ type semiconductor layer is provided on the drain electrode, a scanning signal line is formed on it, and an i-type semiconductor layer and an insulating film serving as a gate insulating film are provided below the scanning signal line. 2. A liquid crystal display device according to claim 1, wherein the width of the i-type semiconductor layer of at least the source electrode portion and the drain electrode portion is made larger than the width of the scanning signal line. 2. The thin film transistor and the pixel electrode are used as constituent elements of a pixel, and the pixel electrode, the video signal line, the source electrode, and the drain electrode are formed of the same transparent conductive film, and the source electrode,
An active matrix method in which an N^+ type semiconductor layer is provided on the drain electrode, a scanning signal line is formed on it, and an i-type semiconductor layer and an insulating film serving as a gate insulating film are provided below the scanning signal line. 1. A liquid crystal display device according to claim 1, further comprising an electrode which together with the pixel electrode constitutes a storage capacitor element.