JP2791084B2 - Liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device such as an active matrix type color liquid crystal display device using a thin film transistor and a pixel electrode as one component of a pixel.

[Conventional technology]

In a conventional active matrix type liquid crystal display device, as disclosed in JP-A-61-151516,
The scanning signal line, the gate electrode, and the electrode film of the storage capacitor are formed of the same conductive film, and the width of the intersection of the conductive film and the video signal line is smaller than the width of the other portions.

In this liquid crystal display device, the width of the intersection of the scanning signal line, the gate electrode, and the video signal line of the conductive film forming the electrode film of the storage capacitor is smaller than the width of the other portions. Since the overlapping area between the scanning signal line and the video signal line at the intersection of the line and the video signal line is reduced, a short circuit between the scanning signal line and the video signal line is small, and the yield is good.

In the conventional active matrix type liquid crystal display device, in order to prevent the conductive film from being partially formed due to a scratch on the lower transparent substrate, a silicon film is formed on one side.
A lower transparent substrate provided with an O ₂ film and a lower transparent substrate whose surface is polished are used.

[Problems to be solved by the invention]

However, when the width of the intersection between the scanning signal line, the gate electrode, and the conductive film forming the electrode film of the storage capacitor element and the video signal line is smaller than the width of the other portions, the above conductive film is provided. If dust or the like is present at a portion corresponding to the intersection, the scanning signal line is disconnected. In addition, SiO ₂
When a lower transparent substrate provided with a film is used, the thickness of the conductive film provided by sputtering is not uniform because the lower transparent substrate is warped, so that the conductive film can serve as a scanning signal line, a gate electrode, and a storage capacitor. When the electrode film is formed, the scanning signal line may be disconnected. Furthermore, if there are sharp scratches on the surface of the lower transparent substrate, the sharp scratches cannot be removed by polishing, so that even if the lower transparent substrate whose surface is polished is used, the scanning signal lines may be broken.

The present invention has been made to solve the above-described problem, and has as its object to provide a liquid crystal display device in which a scanning signal line is not disconnected.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, there is provided a liquid crystal display device in which a plurality of scanning signal lines and a plurality of video signal lines intersect on a transparent substrate and have a matrix shape. A pixel is provided in a region surrounded by the plurality of video signal lines, and each pixel includes a thin film transistor in which a gate electrode is connected to the scanning line and a drain electrode is connected to the video signal line; A pixel electrode connected to a source, and an adjacent scanning signal line not connected to the gate electrode; and a storage capacitor connected to the pixel electrode. The storage capacitor branches the adjacent scanning signal line. A first electrode formed;
A second electrode integrated with the pixel electrode, and a dielectric provided between the first electrode and the second electrode formed so as to overlap with each other; a first electrode of a storage capacitor of one pixel; A thin line portion of the one pixel, which bypasses an intersection of the scanning signal line and the video signal line, between a direction in which the scanning signal line extends and a first electrode of a storage capacitor of an adjacent pixel. Is provided.

In order to achieve the above object, according to the present invention, a first electrode of a storage capacitor of the one pixel and a storage capacitor of a pixel adjacent to the one pixel in a direction in which the scanning signal line extends are provided. And a plurality of thin line portions that bypass the intersections of the scanning signal lines and the video signal lines.

Further, in order to achieve the above object, in the present invention, an SiO ₂ film is provided on both surfaces of the transparent substrate.

[Action]

When a plurality of fine line portions are provided at the intersections of the scanning signal lines and the video signal lines of the conductive film, the probability that dust or the like exists in portions corresponding to all the fine line portions when the conductive film is provided is small.

Further, when the SiO ₂ film is provided on both surfaces of the transparent substrate, the transparent substrate does not warp, and even if there is a sharp scratch on the surface of the transparent substrate, the sharp scratch can be covered with the SiO ₂ film.

〔Example〕

One pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device to which the present invention is applied is shown in FIG. 2 (plan view of a main part), and a cross section taken along the line II-II of FIG. Shown in FIG. FIG. 4 (plan view of a main part) shows a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 2 are arranged.

As shown in FIGS. 2 to 4, in the liquid crystal display device, a pixel having a thin film transistor TFT and a transparent pixel electrode ITO is formed on the inner surface (liquid crystal side) of a lower transparent glass substrate SUB1. The lower transparent glass substrate SUB1 is 1.
The thickness is about 1 mm.

Each pixel is located within an intersection area (4 lines) between two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines) DL. (In the area surrounded by the signal lines of FIG. 3).
As shown in FIGS. 2 and 4, the scanning signal lines GL extend in the column direction and are arranged in a plurality in the row direction. The video signal lines DL extend in the row direction and are arranged in a plurality in the column direction.

The thin film transistor TFT of each pixel has 3
It is divided into two (plurality), and is constituted by thin film transistors (divided thin film transistors) TFT1, TFT2 and TFT3.
Each of the thin film transistors TFT1 to TFT1 has substantially the same size (the same channel length and width). Each of the divided thin film transistors TFT1 to TFT3 mainly includes a gate electrode GT, an insulating film GI, an i-type (intrinsic, in
An i-type semiconductor layer AS made of silicon (Si) (trinsic, not doped with a conductivity type determining impurity), and a pair of source electrode SD1 and drain electrode SD2. In addition,
It is to be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of the liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are switched during the operation. However, also in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.

The gate electrode GT projects from the scanning signal line GL in the row direction (downward in FIGS. 2 and 5), as shown in detail in FIG. It has a character shape. (Branched into a T-shape). That is, the gate electrode GT is configured to extend substantially parallel to the video signal line DL. Gate electrode
The GT is configured to protrude to the respective formation regions of the thin film transistors TFT1 to TFT3. The gate electrodes GT of the thin film transistors TFT1 to TFT3 are integrally formed (as a common gate electrode), and are continuously formed on the same scanning signal line GL. The gate electrode GT is formed of a single-layer first conductive film g1 so that a large step is not formed as much as possible in the formation region of the thin film transistor TFT.
The first conductive film g1 is formed with a film thickness of about 1100 [Å] using, for example, a chromium (Cr) film formed by sputtering.

As shown in FIGS. 2, 3 and 6, the gate electrode GT is formed to be larger than that (as viewed from below) so as to completely cover the i-type semiconductor layer AS. Therefore, when a backlight such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the opaque chrome gate electrode GT is shadowed, and the i-type semiconductor layer AS is not exposed to backlight, The aforementioned conductive phenomenon due to light irradiation, that is, the deterioration of the off-characteristics of the thin film transistor TFT is less likely to occur. Note that the original size of the gate electrode GT has a minimum width (including a margin for alignment between the gate electrode and the source / drain electrode) that extends between the source / drain electrodes SD1 and SD2, and a channel width. The depth length that determines W is determined by the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W / L that determines the transconductance gm.

The size of the gate electrode in this liquid crystal display device is, of course, larger than the above-mentioned original size.

The gate electrode GT and its wiring GL may be integrally formed in a single layer only from the viewpoint of the gate of the gate electrode GT and the light shielding function, and in this case, aluminum containing silicon as an opaque conductive material ( Al), pure aluminum, aluminum containing palladium (Pd), silicon, aluminum containing titanium (Ti), silicon, aluminum containing copper (Cu), and the like can be selected.

The scanning signal line GL is composed of a composite film including a first conductive film g1 and a second conductive film g2 provided thereon. The first conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is integrally formed. The second conductive film g2 is, for example, an aluminum film formed by sputtering, and is 900 to 4000 [4000].
It is formed with a film thickness of about. The second conductive film g2 is connected to the scanning signal line GL.
, And the signal transmission speed can be increased (the writing characteristics of pixel information).

Further, the scanning signal line GL is configured such that the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL can be formed so that the step shape of the side wall thereof is gentle, so that the surface of the upper insulating film GI can be flattened.

The insulating film GI is used as a gate insulating film of each of the thin film transistors TFT1 to TFT3. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. The insulating film GI is formed with a thickness of about 3500 [CVD] using, for example, a silicon nitride film formed by plasma CVD. As described above, the surface of the insulating film GI is
The respective regions for forming T3 and the regions for forming the scanning signal lines GL are flattened.

The i-type semiconductor layer AS is used as a channel forming region of each of the divided thin film transistors TFT1 to TFT3, as shown in detail in FIG. 6 (a plan view of a main part in a predetermined manufacturing process). Each of the i-type semiconductor layers AS of the thin-film transistors TFT1 to TFT3 divided into a plurality is integrally formed in the pixel. That is, each of the plurality of thin-film transistors TFT1 to TFT3 obtained by dividing the pixel includes:
It is composed of an island region of one (common) i-type semiconductor layer AS. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of about 2000 [Å].

This i-type semiconductor layer AS is made of Si ₃ N
₄ and the same plasma CDV
The device is formed without being exposed to the outside from the device. Similarly, a P-doped N ⁺ type semiconductor layer d0 (FIG. 3) for ohmic contact is continuously formed by about 300 μm.
It is formed to a thickness of [Å]. Thereafter, the lower transparent glass substrate SUB1 is taken out of the CVD apparatus, and the N ⁺ -type semiconductor layer d0 and the i-type semiconductor layer AS
As shown in FIG. 3, FIG. 3 and FIG. 6, patterning is performed in an independent island shape.

As described above, by integrally configuring the respective i-type semiconductor layers AS of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels, the drain electrode SD2 common to each of the thin-film transistors TFT1 to TFT3 has the i-type semiconductor layer AS ( Actually, a step corresponding to a thickness obtained by adding the thickness of the first conductive film g1, the thickness of the N ⁺ -type semiconductor layer d0, and the thickness of the i-type semiconductor layer AS) to the i-type from the drain electrode SD2 side. Since it only gets over once toward the semiconductor layer AS side, the probability of disconnection of the drain electrode SD2 is reduced, and the probability of occurrence of point defects can be reduced. That is, in this liquid crystal display device, the point defect generated in the pixel when the drain electrode SD2 gets over the step of the i-type semiconductor layer AS can be reduced to one third.

Also, although different from the layout of this liquid crystal display device, i
In the case where the video signal line DL directly passes over the semiconductor layer AS and the video signal line DL in the portion over which the video signal line DL passes is configured as the drain electrode SD2, when the video signal line DL (drain electrode SD2) passes over the i-type semiconductor layer AS, It is possible to reduce the probability of occurrence of a line defect due to disconnection. That is, by integrally forming the respective i-type semiconductor layers AS of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels, the video signal line DL (drain electrode SD2) passes over the i-type semiconductor layer AS only once. There is no such thing (actually, twice at the start and end of the ride).

As shown in detail in FIGS. 2 and 6, the i-type semiconductor layer AS is provided so as to extend to both the intersections (crossover portions) between the scanning signal lines GL and the video signal lines DL. ing. The extended i-type semiconductor layer AS is configured to reduce a short circuit between the scanning signal line GL and the video signal line DL at the intersection.

Thin-film transistor TFT1 to TFT3 divided into multiple pixels
The source electrode SD1 and the drain electrode SD2 are formed on the i-type semiconductor layer AS, respectively, as shown in detail in FIGS. 2, 3, and 7 (plan views of main parts in a predetermined manufacturing process). They are provided separately. Each of the source electrode SD1 and the drain electrode SD2 is configured such that when the bias polarity of the circuit changes, the source and the drain are switched in operation. That is, the thin film transistor TFT is bidirectional, like the FET.

The source electrode SD1 and the drain electrode SD2 are respectively connected to the first conductive film d1 and the second conductive film d1 from the lower side in contact with the N ⁺ type semiconductor layer d0.
The conductive film d2 and the third conductive film d3 are sequentially overlapped. The first conductive film d1, the second conductive film d2, and the third conductive film d3 of the source electrode SD1 are formed in the same manufacturing process as that of each of the drain electrodes SD2.

The first conductive film d1 uses a chromium film formed by sputtering and has a thickness of 500 to 1000 [Å] (in this liquid crystal display device,
(Thickness of about 00 [Å]). The chromium film, when formed with a large thickness, increases the stress.
It is formed in a range that does not exceed a certain thickness. The chromium film is N ⁺
Good contact with the mold semiconductor layer d0. The chromium film forms a so-called barrier layer that prevents aluminum of a second conductive film d2 described later from diffusing into the N ⁺ -type semiconductor layer d0.
As the first conductive film d1, a high melting point metal (Mo, Ti, Ta, W) film, a high melting point metal silicide (MoS
i ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film.

After patterning the first conductive film d1 by photo processing, the N ⁺ type semiconductor layer d0 is removed using the same photo processing mask or using the first conductive film d1 as a mask. That is, the i-type semiconductor layer
The portion of the N ⁺ -type semiconductor layer d0 remaining on the AS other than the first conductive film d1 is removed by self-alignment. At this time, since the N ⁺ type semiconductor layer d0 is etched so as to remove all of its thickness, the i type semiconductor layer AS is also slightly etched at its surface, but the degree may be controlled by the etching time. .

Thereafter, the second conductive film d2 is formed to a thickness of 3000 to 5500 [Å] (about 3500 [Å] in this liquid crystal display device) by sputtering of aluminum. The aluminum film has less stress than the chromium film and can be formed with a large thickness, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. The second conductive film d2 is a thin film transistor TFT
And the signal transmission speed of the video signal line DL can be increased. That is, the second conductive film d2 can improve the writing characteristics of the pixel. The second conductive film d may be formed of an aluminum film containing silicon, palladium, titanium, copper, or the like as an additive, in addition to the aluminum film.

After patterning the second conductive film d2 by the photo processing technique,
A transparent conductive film (ITO:
And a film thickness of about 300 to 2400 [（] (in this liquid crystal display device, about 1200 [Å]). The third conductive film d3 forms the source electrode SD1, the drain electrode SD2, and the video signal line DL, and includes the transparent pixel electrode IT3.
O is configured.

Each of the first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 has a channel forming region side larger in size than the upper second conductive film d2 and the third conductive film d3. I have. That is, the first conductive film d1 is the first conductive film
Even if a mask misalignment occurs in the manufacturing process between d1 and the second conductive film d2 and the third conductive film d3, the size of the first conductive film d1 is larger than that of the second conductive film d2 and the third conductive film d3. ~
(Each channel forming region side of the third conductive film d3 may be on the line.) First conductive film d1 of source electrode SD1, first conductive film of drain electrode SD2
Each of d1 is configured to define the gate length L of the thin film transistor TFT.

As described above, in the thin film transistors TFT1 to TFT3 divided into a plurality of pixels, the source electrode SD1 and the drain electrode S
By configuring the channel forming region side of each first conductive film d1 of D2 with a size larger than the second conductive film d2 and the third conductive film d3, the source electrode SD1 and the drain electrode SD2 are formed.
The gate length L of the thin film transistor TFT can be defined by the dimension between the first conductive films d1. Since the separation dimension (gate length L) between the first conductive films d1 can be defined by processing accuracy (patterning accuracy), the gate length L of each of the thin film transistors TFT1 to TFT3 can be made uniform.

The source electrode SD1 is connected to the transparent pixel electrode ITO as described above. The source electrode SD1 corresponds to a stepped shape of the i-type semiconductor layer AS (the thickness obtained by adding the thickness of the first conductive film g1, the thickness of the N ⁺ -type semiconductor layer d0, and the thickness of the i-type semiconductor layer AS). (Step). Specifically, the source electrode SD1 is connected to a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and to a transparent pixel electrode ITO above the first conductive film d1. The second conductive film d2 has a small size on the side of the second conductive film d2 and the third conductive film d3 connected to the first conductive film d1 exposed from the second conductive film d2. The first conductive film d1 of the source electrode SD1 has good adhesion to the N ⁺ type semiconductor layer d0, and is mainly composed of the second conductive film d2.
It is configured as a barrier layer against diffused substances.
Since the second conductive film d2 of the source electrode SD1 cannot form a thick chrome film of the first conductive film d1 due to an increase in stress and cannot overcome the step of the i-type semiconductor layer AS, the second conductive film d2 is It is configured to get over. That is, the step coverage is improved by forming the second conductive film d2 to be thick. Since the second conductive film d2 can be formed thick, it greatly contributes to a reduction in the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).
Since the third conductive film d3 cannot overcome the stepped shape caused by the i-type semiconductor layer AS of the second conductive film d2, the first conductive film exposed by reducing the size of the second conductive film d2
It is configured to connect to d1. The first conductive film d1 and the third conductive film d3 not only have good adhesiveness, but also have a small step at the connection between them, so that they can be reliably connected.

Thus, the source electrode SD1 of the thin film transistor TFT
A first conductive film d1 as a barrier layer formed at least along the i-type semiconductor layer AS, and a specific resistance value formed on the first conductive film d1 and lower than the first conductive film d1. ,
And a second conductive film d2 smaller in size than the first conductive film d1.
And the first conductive film exposed from the second conductive film d2.
By connecting the third conductive film d3, which is a transparent pixel electrode ITO, to d1, the thin film transistor TFT and the transparent pixel electrode ITO can be reliably connected, so that point defects due to disconnection can be reduced. Moreover, the source electrode SD1
Since the second conductive film d2 (aluminum film) having a small resistance value can be used due to the barrier effect of the first conductive film d1, the resistance value can be reduced.

The drain electrode SD2 is formed integrally with the video signal line DL, and is formed in the same manufacturing process. Drain electrode
SD2 is formed in an L-shape protruding in the column direction intersecting with the video signal line DL. That is, the drain electrodes SD2 of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels are connected to the same video signal line DL.

The transparent pixel electrode ITO is provided for each pixel, and constitutes one of the pixel electrodes of the liquid crystal display unit. The transparent pixel electrode ITO is a thin film transistor T divided into a plurality of pixels.
It is divided into three transparent pixel electrodes (divided transparent pixel electrodes) ITO1, ITO2, and ITO3 corresponding to each of FT1 to TFT3. The transparent pixel electrode ITO1 is connected to the source electrode SD1 of the thin film transistor TFT1. Transparent pixel electrode ITO2
Is connected to the source electrode SD1 of the thin film transistor TFT2. The transparent pixel electrode ITO3 is connected to the source electrode SD1 of the thin film transistor TFT3.

Each of the transparent pixel electrodes ITO1 to ITO3 has substantially the same size as each of the thin film transistors TFT1 to TFT3. Since each of the transparent pixel electrodes ITO1 to ITO3 is formed integrally with the respective i-type semiconductor layer AS of the thin film transistors TFT1 to TFT3 (the divided thin film transistors TFT are intensively arranged in one place). , L-shape.

In this manner, the thin film transistor TFT of the pixel arranged in the intersection area between the two adjacent scanning signal lines GL and the two adjacent video signal lines DL is replaced with a plurality of thin film transistors TFT1 to TFT
FT3, and the thin-film transistor T
Transparent pixel electrode ITO divided into multiple parts for each of FT1 to TFT3
By connecting each of ~ ITO3, only a part of the divided pixel (for example, thin film transistor TFT1) becomes a point defect, and the pixel as a whole is not a point defect (thin film transistors TFT2 and TFT3 are not a point defect). In addition, it is possible to reduce point defects in the entire pixel.

Further, some of the point defects obtained by dividing the pixel are smaller than the entire area of the pixel (in the case of this liquid crystal display device,
(One-third the area of a pixel), making it difficult to see the point defects.

Further, the transparent pixel electrodes ITO1 to ITO3 obtained by dividing the pixels.
Are substantially the same size, the area of the point defect in the pixel can be made uniform.

Further, the transparent pixel electrodes ITO1 to ITO3 obtained by dividing the pixels.
Are configured to have substantially the same size, so that each of the liquid crystal capacitors (Cpix) constituted by each of the transparent pixel electrodes ITO1 to ITO3 and the common transparent pixel electrode ITO
In addition, the overlap capacitance (Cgs) generated by overlapping the transparent pixel electrodes ITO1 to ITO3 and the gate electrode GT added to each of the transparent pixel electrodes ITO1 to ITO3 can be made uniform. That is, since each of the transparent pixel electrodes ITO1 to ITO3 can make the liquid crystal capacitance and the overlap capacitance uniform, the DC component to be applied to the liquid crystal molecules of the liquid crystal LC caused by the overlap capacitance is made uniform. When the method of canceling out the direct current component is adopted, the variation of the direct current component applied to the liquid crystal of each pixel can be reduced.

On the thin film transistor TFT and the transparent pixel electrode ITO,
A protective film PSV1 is provided. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a thickness of 5000
Film thickness of ~ 11000 [膜厚] (in this liquid crystal display, 8000
[膜厚].

On top of the protective film PSV1 on the thin film transistor TFT, an i-type semiconductor layer where external light is used as a channel formation region
A shielding film LS is provided so as not to be incident on the AS.
As shown in FIG. 2, the shielding film LS is formed in a region surrounded by a dotted line. The shielding film LS is formed of, for example, an aluminum film or a chromium film having a high light shielding property, and is formed to a thickness of about 1000 [Å] by sputtering.

Therefore, the common semiconductor layer AS of the thin film transistors TFT1 to TFT3 has the light shielding film LS and the large gate electrode
It is sandwiched by the GT, and no external natural light or backlight light hits it. The light-shielding film LS and the gate electrode GT are larger than the semiconductor layer AS and are formed in a shape substantially similar to the semiconductor layer AS.
The sizes of the two are almost the same (in the figure, the gate electrode GT is drawn smaller than the light shielding film LS so that the boundary line can be seen).

In addition, the backlight can be attached to the upper transparent glass substrate SUB2 side, and the lower transparent glass substrate SUB1 can be the observation side (externally exposed side). In this case, the light shielding film LS is used for backlight light, and the gate electrode GT is used for natural light. Works as a light shield.

The thin film transistor TFT is configured such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases. That is, the thin film transistor TFT is configured to control the voltage applied to the transparent pixel electrode ITO.

The liquid crystal LC is defined and sealed in a lower alignment film ORI1 and an upper alignment film ORI2 for setting the direction of liquid crystal molecules in a space formed between the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2. .

The lower alignment film ORI1 is a protective film for the lower transparent glass substrate SUB1.
Formed on top of PSV1.

On the inner (liquid crystal side) surface of the upper transparent glass substrate SUB2, a color filter FIL, a protective film PSV2, a common transparent pixel electrode (COM) ITO, and the upper alignment film ORI2 are sequentially laminated.

The common transparent pixel electrode ITO has a lower transparent glass substrate SUB
One side faces the transparent pixel electrode ITO provided for each pixel, and is configured integrally with another adjacent common transparent pixel electrode ITO. The common transparent pixel electrode ITO is configured to be applied with a common voltage Vcom. The common voltage Vcom is
Low-level drive voltage Vd min applied to video signal line DL
And a high-level drive voltage Vdmax.

The color filter FIL is configured by coloring a dye on a dyed base material formed of a resin material such as an acrylic resin.
The color filter FIL is configured for each pixel at a position facing the pixel and is dyed separately. That is, the color filter FIL is formed in the intersection area between the two adjacent scanning signal lines GL and the two adjacent video signal lines DL at the same time as the pixels. Each pixel is divided into a plurality of parts in each predetermined color filter of the color filter FIL.

The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, by performing similar steps, a green filter G and a blue filter B are sequentially formed.

As described above, by forming each color filter of the color filter FIL in the intersection region facing each pixel, each of the scanning signal lines GL and the video signal lines DL exists between the color filters of the color filter FIL. To the extent corresponding to their existence, it is possible to secure a margin for alignment between each pixel and each color filter of the color filter FIL (enlarge the alignment margin). In addition, color filters
When forming each color filter of the FIL, it is possible to secure an alignment allowance between the different color filters.

That is, in this liquid crystal display device, a pixel is formed in an intersection area between two adjacent scanning signal lines GL and two adjacent video signal lines DL, and this pixel is divided into a plurality of pixels, and the pixel is opposed to the pixel. By forming each color filter of the color filter FIL at the position where the color filter FIL is formed, the above-mentioned point defects can be reduced, and a margin for alignment between each pixel and each color filter can be secured.

The protective film PSV2 is provided in order to prevent the dye obtained by dyeing the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin and an epoxy resin.

In this liquid crystal display device, the layers on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side are separately formed, and then the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, and the liquid crystal is interposed between the two. Assembled by enclosing LC.

As shown in FIG. 4, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal lines GL extend, and the pixel columns X ₁ , X ₂ , X ₃ , X ₄ ,. Each of which is configured.
Each pixel column _{X 1, X 2, X 3} , X 4, ... each pixel of constitutes a position of the thin film transistor TFT1~TFT3 and the transparent pixel electrode ITO1~ITO3 the same. That is, the pixel rows X ₁ , X ₃ ,.
In each pixel, the arrangement positions of the thin film transistors TFT1 to TFT3 are arranged on the left side, and the arrangement positions of the transparent pixel electrodes ITO1 to ITO3 are arranged on the right side. Each pixel of the next row of pixel columns X ₂ , X ₄ ,... In the row direction of each of the pixel columns X ₁ , X ₃ ,.
Each of the pixels X ₁ , X ₃ ,... Is composed of pixels arranged in line symmetry with respect to the video signal line DL. That is, each pixel in the pixel rows X ₂ , X ₄ ,.
The arrangement positions of T1 to TFT3 are configured on the right side, and the arrangement positions of the transparent pixel electrodes ITO1 to ITO3 are configured on the left side. Then, the pixel rows X ₂ , X ₄ ,
Are shifted (shifted) by a half pixel interval in the column direction with respect to each pixel of the pixel rows X ₁ , X ₃ ,.
Are located. That is, the pixel interval of the pixel row X is set to 1.0.
Assuming that (1.0 pitch), the pixel row X in the next stage has a pixel interval of 1.0 and is shifted by 0.5 pixel interval (0.5 pitch) in the column direction with respect to the preceding pixel row X. The video signal lines DL extending in the row direction between the pixels are configured to extend in the column direction by half pixel intervals (0.5 pitch) between the pixel columns X.

Thus, in the liquid crystal display unit, the thin film transistor
A plurality of pixels having the same arrangement positions of the TFT and the transparent pixel electrode ITO are arranged in the column direction to form a pixel row X, and the next pixel row X of the pixel row X and the pixel of the preceding pixel row X are image signals. FIG. 8 (pixels and color filters are overlapped) by forming pixels arranged in line symmetry with respect to the line DL and moving the next pixel row by a half pixel interval with respect to the preceding pixel row. as shown by the fragmentary plan view) in a state where combined, pixels predetermined color filters are formed of the preceding pixel row X (e.g., the next stage of the pixel and the red filter R is formed pixels) of the pixel row X ₃ Pixels in which the same color filter in column X is formed (for example,
And a pixel) the red filter R of the pixel column X ₄ are formed, 1.
It can be separated by 5 pixel intervals (1.5 pitch). In other words, the pixels of the previous pixel row X are always separated by 1.5 pixels from the nearest pixel row of the next pixel row on which the same color filter is formed.
FIL can be configured as an RGB triangle arrangement structure. The RGB triangular arrangement structure of the color filter FIL can improve the color mixture of each color, so that the resolution of a color image can be improved.

In addition, since the video signal lines DL extend in the column direction only by half pixel intervals between the pixel columns X, they do not cross adjacent video signal lines DL. Therefore, it is possible to eliminate the routing of the video signal lines DL and reduce the occupied area. In addition, the bypass of the video signal line DL can be eliminated, and the multilayer wiring structure can be eliminated.

FIG. 9 (equivalent circuit diagram of the liquid crystal display) shows a circuit configuration of the liquid crystal display. XiG, Xi + 1G,... Shown in FIG. 9 are video signal lines DL connected to the pixels on which the green filter G is formed. XiB, Xi + 1B, ...
This is a video signal line DL connected to the pixel on which the blue filter B is formed. Xi + 1R, Xi + 2R,... Are video signal lines DL connected to pixels on which the red filter R is formed. These video signal lines DL are selected by a video signal drive circuit. Yi
Is a scanning signal line GL for selecting the pixel column X ₁ shown in the FIG. 4 and FIG. 8. Similarly, each of Yi + 1, Yi + 2,... Is a scanning signal line GL for selecting each of the pixel columns X ₂ , X ₃ ,.
It is. These scanning signal lines GL are connected to a vertical scanning circuit.

The center part of FIG. 3 shows a cross section of one pixel portion, while the left side shows a cross section of a left edge portion of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 where an external lead-out wiring exists. . The right side shows a cross section of a portion on the right edge portion of the transparent glass substrates SUB1 and SUB2 where no external lead-out wiring exists.

The sealing material SL shown on each of the left and right sides of FIG.
The transparent glass substrates SUB1 and SU are configured to seal the liquid crystal LC, excluding the liquid crystal filling port (not shown).
It is formed along the entire periphery of the edge of B2. Seal material SL
Is formed of, for example, an epoxy resin.

The common transparent pixel electrode IT on the upper transparent glass substrate SUB2 side
O is connected to the external lead-out wiring formed on the lower transparent glass substrate SUB1 side by the silver paste material SIL at least at one place. This external lead-out wiring is formed in the same manufacturing process as each of the gate electrode GT, the source electrode SD1, and the drain electrode SD2 described above.

The respective layers of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO, the common transparent pixel electrode ITO, the protective films PSV1 and PSV2, and the insulating film GI are formed inside the sealing material SL. The polarizing plate POL is formed on the outer surface of each of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2.

FIG. 10 is a cross-sectional view of a main portion of a pixel of a liquid crystal display portion and a peripheral portion of a seal portion of another active matrix type color liquid crystal display device to which this transparency is applied, and FIG. 11 is a liquid crystal shown in FIG. FIG. 12 is a plan view showing one pixel of a liquid crystal display portion of a display device, FIG. 12 is a cross-sectional view taken along a line AA in FIG. 11, and FIG. 13 is a liquid crystal in which a plurality of pixels shown in FIG. 14 to 16 are plan views of main parts in a predetermined manufacturing process of the pixel shown in FIG. 11, and FIG. 17 is a diagram in which the pixel and the color filter shown in FIG. 13 are superimposed. It is a principal part top view in the state where it fell.

In this liquid crystal display device, it is possible to improve the aperture ratio of each pixel of the liquid crystal display unit, reduce the DC component applied to the liquid crystal, reduce point defects in the liquid crystal display unit, and reduce black unevenness. it can.

In this liquid crystal display device, as shown in FIG. 11, an i-type semiconductor layer AS in each pixel of a liquid crystal display portion is formed by a thin film transistor TFT1.
.About.TFT3. That is, each of the thin-film transistors TFT1 to TFT3 divided into a plurality of pixels is formed of an independent island region of the i-type semiconductor layer AS.

In addition, each of the transparent pixel electrodes ITO1 to ITO3 connected to each of the thin film transistors TFT1 to TFT3 overlaps the next-stage scanning signal line GL in the row direction on the side opposite to the side connected to the thin film transistors TFT1 to TFT3. Have been. This superimposition constitutes a storage capacitance element (capacitance element) Cadd in which each of the transparent pixel electrodes ITO1 to ITO3 is used as one electrode and the next-stage scanning signal line GL is used as the other electrode.
The dielectric film of the storage capacitor Cadd is a thin film transistor
It is composed of the same layer as the insulating film GI used as a TFT gate insulating film.

The gate electrode GT is formed to be larger than the i-type semiconductor layer AS, similarly to the liquid crystal display device shown in FIG. 2 and the like. In this liquid crystal display device, the thin film transistors TFT1 to TFT3 are provided for each independent i-type semiconductor layer AS. As a result, a large pattern is formed for each thin film transistor TFT.

In addition, since the black matrix pattern BM is provided in a portion corresponding to the scanning signal line GL, the video signal line DL, and the thin film transistor TFT of the upper transparent glass substrate SUB2, the contour of the pixel becomes clear, so that the contrast is improved. In addition, it is possible to prevent external natural light from hitting the thin film transistor TFT.

FIG. 18 (equivalent circuit diagram) shows an equivalent circuit of the pixel described in FIG. In FIG. 18, Cgs is the gate electrode GT and the source electrode S of the thin film transistor TFT as described above.
This is the overlap capacitance formed by D1. Superposition capacity Cgs
Is a dielectric film GI. Cpix is transparent pixel electrode ITO
(PIX) and the liquid crystal capacitance formed between the common transparent pixel electrode ITO (COM). The dielectric film of the liquid crystal capacitor Cpix is liquid crystal L
C, a protective film PSV1 and alignment films ORI1, ORI2. Vlc is the midpoint potential.

The storage capacitance element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vcl when the thin film transistor TFT switches. This situation is represented by the following equation.

ΔVlc = {(Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, ΔVlc represents a change in the midpoint potential due to ΔVg, and this change ΔVlc causes a DC component applied to the liquid crystal. The larger the capacitance, the smaller the value can be.The storage capacitor Cadd also has the effect of extending the discharge time, and stores video information after the thin film transistor TFT is turned off for a longer time. The reduced DC component improves the life of the liquid crystal LC, and reduces the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, the gate electrode GT is made large so as to completely cover the semiconductor layer AS, so that the source / drain electrode SD
1. The area of overlap with SD2 increases, so the parasitic capacitance Cgs increases, and the midpoint potential Vlc becomes the gate (scan) signal Vg
Has the opposite effect of being more susceptible to the effects of But,
By providing the storage capacitance element Cadd, this delimitation can be eliminated.

In a liquid crystal display device having a pixel in an intersection area between two scanning signal lines GL and two video signal lines DL, one of the two scanning signal lines GL is selected by one of the two scanning signal lines GL. The thin film transistor TFT of the pixel to be divided into a plurality of TFTs, and each of the divided thin film transistors TFT1 to TFT3 is divided into a plurality of transparent pixel electrodes ITO (ITO1 to ITO
3) Connect the divided transparent pixel electrodes ITO1 to ITO3
The pixel electrode ITO is used as one electrode for each of
By using the other scanning signal line GL of the scanning signal lines GL as the capacitor electrode line and forming the storage capacitor Cadd as the other electrode, as described above, the divided part of the pixel has a point defect. , The pixel as a whole is no longer a point defect, so that the point defect of the pixel can be reduced, and the DC component applied to the liquid crystal LC by the storage capacitor Cadd can be reduced. Life can be improved. In particular, by dividing the pixel, the gate electrode GT and the source electrode S of the thin film transistor TFT are
Point defects due to short circuit with D1 or drain electrode SD2 can be reduced, and transparent pixel electrodes ITO1 to IT
Point defects caused by a short circuit between each of O3 and the other electrode (capacitor electrode line) of the storage capacitor Cadd can be reduced. The point defect on the latter side is one third in the case of this liquid crystal display device.
become. As a result, some of the divided point defects of the pixel are smaller than the entire area of the pixel, so that it is difficult to see the point defect.

The storage capacitance of the storage capacitance element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4 · Cpix <Cadd) due to the writing characteristics of the pixel.
<8 · Cpix), 8 to 32 times (8
・ Set to a value of about Cgs <Cadd <32 · Cgs).

Further, the scanning signal line GL is connected to a first conductive film (chrome film) g1.
And a second conductive film (aluminum film) g2 is superposed on the composite film, and the other electrode of the storage capacitor Cadd, that is, the branched portion of the capacitor electrode line is connected to the first conductive film of one layer of the composite film. With the single-layer film composed of the film g1, the resistance value of the scanning signal line GL can be reduced, the writing characteristics can be improved, and along the step portion based on the other electrode of the storage capacitor Cadd. Since one electrode (transparent pixel electrode ITO) of the storage capacitor Cadd can be securely bonded onto the insulating film GI, disconnection of one electrode of the storage capacitor Cadd can be reduced.

Further, the other electrode of the storage capacitor Cadd is formed of the single-layer first conductive film g1 and the second conductive film g2 of the aluminum film is not formed, so that the other electrode of the storage capacitor Cadd due to the hillock of the aluminum film is formed. A short circuit between the electrode and one of the electrodes can be prevented.

A part between each of the transparent pixel electrodes ITO1 to ITO3 overlapped to form the storage capacitor element Cadd and a branched part of the capacitor electrode line is branched like the source electrode SD1. An island region composed of the first conductive film d1 and the second conductive film d2 is provided so that the transparent pixel electrode ITO is not disconnected when the vehicle passes over the stepped portion. This island area is the area (aperture ratio) of the transparent pixel electrode ITO.
Is designed to be as small as possible so as not to decrease.

As described above, the first conductive film d1 is located between one electrode of the storage capacitor Cadd and the insulating film GI used as a dielectric film thereof, as compared with the first conductive film d1 formed thereon. An underlayer composed of a second conductive film d2 having a small specific resistance and a small size is formed, and the one electrode (third conductive film d2) is formed.
3) is connected to the first conductive film d1 exposed from the second conductive film d2 of the underlying layer, thereby ensuring one of the storage capacitor elements Cadd along a step portion based on the other electrode of the storage capacitor element Cadd. Since the electrodes can be bonded, disconnection of one electrode of the storage capacitor Cadd can be reduced.

The liquid crystal display unit of the liquid crystal display device in which the storage capacitor Cadd is provided on the transparent pixel electrode ITO of the pixel is configured as shown in FIG. 20 (an equivalent circuit diagram showing the liquid crystal display unit). The liquid crystal display section is configured by repeating a unit basic pattern including pixels, scanning signal lines GL, and video signal lines DL. The final scanning signal line GL (or the first scanning signal line GL) used as the capacitor electrode line is connected to the common transparent pixel electrode (Vcom) ITO as shown in FIG. Common transparent pixel electrode ITO
As shown in FIG. 3, the peripheral portion of the liquid crystal display device is connected to an external lead-out wiring by a silver paste material SL. In addition, some of the conductive layers (g1
And g2) are formed in the same manufacturing process as the scanning signal line GL. As a result, the final scanning signal line GL (capacitance electrode line)
Can be easily connected to the common transparent pixel electrode ITO.

As described above, by connecting the last stage of the capacitor electrode line to the common transparent pixel electrode (Vcom) ITO of the pixel, the last stage capacitor electrode line is integrally formed with a part of the conductive layer of the external lead-out wiring. In addition, since the common transparent pixel electrode ITO is connected to the external lead-out line, the last stage capacitor electrode line can be connected to the common transparent pixel electrode ITO with a simple configuration.

In addition, the liquid crystal display device employs a direct current canceling method (D / A) described in Japanese Patent Application No. 62-95125 previously filed by the present applicant.
As shown in FIG. 19 (time chart), based on the C cancellation method, by controlling the drive voltage of the scanning signal line DL, the DC component applied to the liquid crystal LC can be further reduced. In FIG. 19, Vi is the drive voltage of an arbitrary scan signal line GL, and Vi + 1 is the drive voltage of the next scan signal line GL. Vee is a low-level driving voltage Vd min applied to the scanning signal line GL, and Vdd is a high-level driving voltage Vd max applied to the scanning signal line GL. Each time t = t ₁
Voltage change ΔV of midpoint potential Vlc (see FIG. 18) at t _{4
1 to} ΔV ₄ are the total capacity (Cgs + Cpix + Cadd) of pixels as C
Then, the following equation is obtained.

ΔV ₁ = − (Cgs / C) · V2 ΔV ₂ = + (Cgs / C) · (V1 + V2) − (Cadd / C) · V2 ΔV ₃ = − (Cgs / C) · V1 + (Cadd / C) · (V1 + V2) ΔV ₄ = − (Cadd / C) · V1 Here, if the driving voltage applied to the scanning signal line GL is sufficient (see [Note] below), the DC voltage applied to the liquid crystal LC is expressed by the following equation. It is represented by

ΔV ₃ + ΔV ₄ = (Cadd · V2−Cgs · V1) / C Therefore, if Cadd · V2 = Cgs · V1, the DC voltage applied to the liquid crystal LC becomes zero.

Note: the time t _1, the variation of the scanning line Vi at t ₂ is affects the mid-point potential Vlc, mid-point potential Vlc during the period t ₂ ~t ₃ signal line X
The potential is set to the same as the video signal potential through i (sufficient writing of the video signal). The potential applied to the liquid crystal LC is almost determined by the potential immediately after the thin film transistor TFT is turned off (the off period of the thin film transistor TFT is much longer than the on period). Therefore, the calculation of the DC component applied to the liquid crystal LC is
The periods t _{1 to} t ₃ can be almost ignored, and the potential immediately after the thin film transistor TFT is turned off, that is, the influence of the transition at times t ₃ and t ₄ can be considered. In addition, the video signal Vi is
Alternatively, the polarity is inverted for each line, and the DC component due to the video signal itself is set to zero.

In other words, the direct current canceling method uses the holding capacitance Cad
The DC component applied to the liquid crystal LC can be made extremely small by pushing up by the drive voltage applied to d and the scanning signal line GL (capacitance electrode line) of the next stage. As a result, the liquid crystal display device can improve the life of the liquid crystal LC. Of course, when the gate GT is increased to increase the light blocking effect, the storage capacitance of the storage capacitor Cadd may be increased accordingly.

As shown in FIG. 21 (equivalent circuit diagram showing a liquid crystal display unit), this direct current canceling method uses a first stage scanning signal line GL (or capacitance electrode line) and a last stage capacitance electrode line (or scanning signal line G).
L) can be adopted by connecting. No. 2
Although only four scanning signal lines GL are shown in FIG. 1 for convenience, about several hundred scanning signal lines GL are actually arranged. The connection between the first-stage scanning signal line GL and the last-stage capacitor electrode line is performed by an internal wiring or an external lead-out wiring in the liquid crystal display unit.

As described above, the liquid crystal display device connects the first-stage scanning signal line GL to the last-stage capacitance electrode line, thereby forming the scanning signal line GL.
All GL and capacitance electrode lines can be connected to the vertical scanning circuit, so DC cancellation method (DC cancellation method)
Can be adopted. As a result, the DC component applied to the liquid crystal LC can be reduced, so that the life of the liquid crystal LC can be improved.

FIG. 1 is a plan view of a liquid crystal display portion of an active matrix type color liquid crystal display device according to the present invention in a predetermined manufacturing process, and FIG. 22 is a sectional view showing a thin film transistor portion of the liquid crystal display device shown in FIG. It is. In the figure, DPI is S provided on both surfaces of the lower transparent glass substrate SUB1.
In the iO ₂ film, the SiO ₂ film DPI is provided by dipping. g11 is a conductive film made of chromium provided on the SiO ₂ film DPI, and the scanning signal line GL, the gate electrode GT,
An electrode film of the storage capacitor Cadd is formed. NLP is a plurality of thin line portions provided at intersections of the scanning signal lines GL and the video signal lines DL of the conductive film g11.

In this liquid crystal display device, since a plurality of fine line portions NLP are provided at the intersections of the scanning signal lines GL and the video signal lines DL of the conductive film g11, at the intersections of the scanning signal lines GL and the video signal lines DL. Since the overlapping area between the scanning signal line GL and the video signal line DL is reduced, a short circuit between the scanning signal line GL and the video signal line DL is small, and the yield is good. Further, since a plurality of thin line portions NLP are provided at the intersections of the scanning signal lines GL and the video signal lines DL of the conductive film g11, when the conductive film g11 is provided, dust is applied to portions corresponding to all the thin line portions NLP. Since the probability of the presence of the scanning signal line GL is small, it is possible to effectively prevent the scanning signal line GL from being disconnected. Also, as shown in FIG.
The thin line portion NLP is not only a portion where the scanning signal line GL and the video signal line DL intersect, but also a holding capacitance element branched from the scanning signal line GL.
Since it is also provided between the electrodes of Cadd, the width of the thin line portion NLP can be increased, and even if the intersection of the scanning signal line GL and the video signal line DL is broken, the wiring of the scanning signal line GL is The effect of sufficiently reducing the resistance is obtained.

Further, as shown in FIG. 1, the thin line portion NLP is connected to the scanning signal line GL.
Are provided between the electrodes of the storage capacitance element Cadd branched from, the wiring resistance of the scanning signal line GL can be extremely reduced without impairing the aperture ratio. Further, since the SiO ₂ film DPI is provided on both surfaces of the lower transparent glass substrate SUB1, the lower transparent glass substrate SUB1 does not warp, so that the film thickness of the conductive film g11 provided by sputtering becomes uniform, so that the scanning signal line Disconnection of the GL can be effectively prevented. Also, both sides of the lower transparent glass substrate SUB1
Since providing the O ₂ film DPI, even if there is a sharp scratches on the surface of the lower transparent glass substrate SUB1, it is possible to cover the sharp scratches SiO ₂ film DPI, effectively prevent the scanning signal line GL is to break can do. And the scanning signal line as described above
Since the disconnection of the GL can be effectively prevented, the scanning signal line GL can be constituted only by the conductive film g11. In this case, the manufacturing process can be shortened, thereby reducing the manufacturing cost. be able to.

Next, a method of manufacturing the liquid crystal display device shown in FIGS. 1 and 22 will be described. First, an SiO ₂ film DPI is provided on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dipping. The thickness of the SiO ₂ film DPI is 400
110000 [Å] (in this embodiment, 800 [実 施], which is thinner than the insulating film GI having a thickness of 3500 [Å]). Next, a conductive film g1 having a thickness of 1100 [Å] is formed on the lower transparent glass substrate SUB1.
1 is provided by sputtering. Next, the conductive film g11 is selectively etched by a photolithography technique using a ceric ammonium nitrate solution as an etchant to form the scanning signal line GL, the gate electrode GT, and the electrode film of the storage capacitor Cadd. . Next, remove the resist
After removal with S502 (trade name), phosphine gas, ammonia gas, and hydrogen gas are introduced into the plasma CVD device,
After a silicon nitride film having a thickness of 3500 [Å] is provided, an i-type amorphous silicon film having a thickness of 2100 [Å] is provided and a film thickness of 30
An N ⁺ type silicon film of 0 [Å] is provided. Next, the N ⁺ -type silicon film and the i-type amorphous silicon film are selectively etched by a photolithography technique using SF ₆ as a dry etching gas to form an i-type semiconductor layer AS. Next, after removing the resist, the resist is applied twice,
The insulating film GI is formed by selectively etching the silicon nitride film by a photolithography technique using SF ₆ as a dry etching gas. Next, after removing the resist, a first conductive film d1 made of chromium having a thickness of 600 [Å] is formed by sputtering. Next, by selectively etching the first conductive film d1 by a photolithography technique using a ceric ammonium nitrate solution as an etchant, the first layer of the video signal line DL, the source electrode SD1, and the drain electrode SD2 is formed. Form. Next, before the resist is removed, CCl ₄ and SF ₆ are introduced into a dry etching apparatus, and the N ⁺ -type silicon film is selectively etched to form an N ⁺ -type semiconductor layer d0. Next, after removing the resist, O ₂ asher is performed for 1 minute. Next, a second conductive film made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper or the like having a thickness of 3500 [Å]
d2 is provided by sputtering. Next, the second conductive film d2 is selectively etched by a photolithography technique using a mixed acid of hydrochloric acid, nitric acid, and phosphoric acid as an etchant, so that a video signal line DL, a source electrode SD1, and a drain electrode SD2 are formed.
Is formed. Next, after removing the resist, O ₂ asher is performed for 1 minute. Next, when the film thickness is 1200
[3] A third conductive film d3 made of an amorphous ITO film is provided by sputtering. Next, a third conductive film d3 is formed by photolithography using a mixed acid of hydrochloric acid and nitric acid as an etchant.
By selectively etching the video signal lines DL,
The third layer of the source electrode SD1, the drain electrode SD2, the uppermost layer of the gate terminal and the drain terminal, and the transparent pixel electrode ITO are formed. Next, after removing the resist, the plasma CD
Ammonia gas Hydrogen gas was introduced into the V device, and the film thickness became 1
A [μm] silicon nitride film is provided. Next, a resist is applied twice, by selectively etching the silicon nitride film by photolithography technique using SF ₆ as a dry etching gas to form a protective film PSV1.

As described above, since the resist is applied twice when forming the insulating film GI and the protective film PSV1, it is necessary to effectively prevent the transfer of the pinhole of the resist to the insulating film GI and the protective film PSV1. Can be. Further, since the uppermost layer of the gate terminal and the drain terminal is formed of the third conductive film d3, the connection between the gate terminal and the drain terminal and the TAB is good.

As described above, the present invention has been specifically described based on the above-described embodiment. However, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

For example, the present invention can be applied to a liquid crystal display device in which each pixel of a liquid crystal display section is divided into two or four. However, when the number of divisions of the pixel is too large, the aperture ratio is reduced. Therefore, as described above, about 2 to 4 divisions are appropriate. Further, the light-shielding effect can be obtained without dividing the pixel. Further, in the above-described embodiment, the inverted staggered structure of gate electrode formation → gate insulating film formation → semiconductor layer formation → source / drain electrode formation was described. It is valid.

〔The invention's effect〕

As described above, in the liquid crystal display device according to the present invention, since a plurality of fine line portions are provided at the intersections between the scanning signal lines and the video signal lines of the conductive film, all of the Since the probability that dust or the like exists in the portion corresponding to the thin line portion is small, it is possible to effectively prevent the scanning signal line from being disconnected.

In addition, since the thin line portion is provided not only at the portion where the scanning signal line and the video signal line intersect, but also between the electrodes of the storage capacitor element branched from the scanning signal line, the width of the thin line portion can be increased. Even if the intersection of the scanning signal line with the video signal line is broken, the effect of sufficiently reducing the wiring resistance of the scanning signal line can be obtained.

Further, since the thin line portion is provided between the electrodes of the storage capacitor element branched from the scanning signal line, even if a plurality of thin line portions are provided, the wiring ratio of the scanning signal line can be extremely reduced without impairing the aperture ratio.

Further, in the liquid crystal display device according to the present invention, since the SiO ₂ films are provided on both surfaces of the transparent substrate, the transparent substrate does not warp, so that the thickness of the conductive film becomes uniform, and thus the scanning signal line is disconnected. Can be effectively prevented, and even if there is a sharp flaw on the surface of the transparent substrate, the sharp flaw can be covered with the SiO ₂ film, thus effectively preventing the disconnection of the scanning signal line. be able to.

 Thus, the effect of the present invention is remarkable.

[Brief description of the drawings]

FIG. 1 is a plan view of a liquid crystal display portion of an active matrix type color liquid crystal display device according to the present invention in a predetermined manufacturing process, and FIG. 2 is a view of an active matrix type color liquid crystal display device to which the present invention is applied. FIG. 3 is a plan view of an essential part showing one pixel of the liquid crystal display portion, and FIG. 3 is a II-II of FIG.
FIG. 4 is a cross-sectional view of a portion cut by a cutting line and a peripheral portion of the seal portion, FIG. 4 is a plan view of a main part of a liquid crystal display portion in which a plurality of pixels shown in FIG. 2 are arranged, and FIGS. FIG. 8 is a plan view of a main part in a predetermined manufacturing process of a pixel shown in FIG. 8, FIG. 8 is a plan view of a main part in a state where the pixel shown in FIG. 4 and a color filter are superimposed, and FIG. Equivalent circuit diagram showing the liquid crystal display section of the liquid crystal display device, FIG.
FIG. 11 is a cross-sectional view of a main part of a pixel of a liquid crystal display portion and a peripheral portion of a seal portion of another active matrix type color liquid crystal display device to which the present invention is applied. FIG. 11 is a liquid crystal display device shown in FIG. Plan view showing one pixel of a liquid crystal display portion of FIG.
FIG. 12 is a cross-sectional view taken along the line AA of FIG. 11, and FIG.
13 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 11 are arranged, FIGS. 14 to 16 are plan views of a main part in a predetermined manufacturing process of the pixel shown in FIG. 11, and FIG. Is a plan view of a main part in a state where the pixel and the color filter shown in FIG. 13 are overlapped, FIG. 18 is an equivalent circuit diagram of the pixel described in FIG. 11,
FIG. 19 is a time chart showing the driving voltage of the scanning signal line by the DC offset method, and FIGS. 20 and 21 are equivalent diagrams showing the liquid crystal display portion of the active matrix type color liquid crystal display device shown in FIG. 13 respectively. FIG. 22 is a cross-sectional view showing a thin film transistor portion of the liquid crystal display device shown in FIG. SUB: Transparent glass substrate GL: Scan signal line DL: Video signal line GI: Insulating film GT: Gate electrode AS: i-type semiconductor layer SD: Source or drain electrode PSV: Protective film LS: ... Light-shielding film LC ... Liquid crystal TFT ... Thin film transistor ITO (COM) ... Transparent pixel electrode g, d ... Conducting film Cadd ... Capacitance element Cgs ... Superposition capacitance Cpix ... Liquid crystal capacitance BM ... Black matrix pattern DPI ...... SiO ₂ film NLP ...... thin line portion

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-88985 (JP, A) JP-A-61-151516 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/136 500

Claims (3)

(57) [Claims] 1. A liquid crystal display device in which a plurality of scanning signal lines and a plurality of video signal lines intersect on a transparent substrate and have a matrix shape, wherein the plurality of scanning signal lines and the plurality of video signal lines are provided. Each pixel is provided in a region surrounded by a circle, and each pixel includes a thin film transistor having a gate electrode connected to the scanning line, a drain electrode connected to the video signal line, and a pixel electrode connected to a source of the thin film transistor. And a storage capacitor connected to an adjacent scanning signal line not connected to the gate electrode and the pixel electrode, wherein the storage capacitor is a first electrode formed by branching the adjacent scanning signal line; A second electrode integrated with the pixel electrode and a dielectric provided between the first electrode and the second electrode are formed so as to overlap with each other; a first electrode of a storage capacitor of one pixel; The above one A thin line portion that bypasses the intersection of the scanning signal line and the video signal line is provided between the pixel and the first electrode of the storage capacitor of an adjacent pixel in the direction in which the scanning signal line extends. A liquid crystal display device characterized by the above-mentioned. 2. A first electrode of a storage capacitor of the one pixel,
In the direction in which the scanning signal line of the one pixel extends,
2. The device according to claim 1, wherein a plurality of thin line portions are provided between the first electrode of the storage capacitor of an adjacent pixel and the thin line portion to bypass an intersection of the scanning signal line and the video signal line. Liquid crystal display device. 3. The liquid crystal display device according to claim ₂ , wherein SiO ₂ films are provided on both surfaces of said transparent substrate.