JPH02234133A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent burning from occurring by making the width of the part of a gate electrode which is outside both side parts of a source electrode same as the width of the part which is superposed on the source electrode and making the width of the part of the source electrode which is outside both side parts of the gate electrode same as the width of the part which is superposed on the gate electrode. CONSTITUTION:The width of the part of the gate electrode GT which is outside both side parts of the source electrode SD 1 is made same as the width of the part which is superposed on the source electrode SD 1, and the width of the part of the source electrode SD 1 which is outside both side part of the gate electrode GT is made same as the width of the part which is superposed on the gate electrode GT. Since the superposed area of the gate electrode GT and the source electrode SD 1 is not changed even if misalignment occurs between the gate electrode GT and the source electrode SD 1, the superposition capacity obtained by superposing the gate electrode GT and the source electrode SD 1 is prevented from becoming ununiform and also DC voltage component impressed on a protective film and an orientation film is prevented from becoming ununiform. Thus, the burning does not occur.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a liquid crystal display device such as an active matrix color liquid crystal display device in which a pixel includes a thin film transistor and a pixel electrode. [Conventional technology] Figure 24 shows a conventional active matrix type liquid crystal display device I! (Japanese Unexamined Patent Publication No. 60-68326) is a plan view of a main part showing one pixel of a liquid crystal display section. In the figure, GL is a scanning signal line, DL is a video signal line, SDI is a source electrode, and ITO is a transparent pixel electrode. [Problems to be Solved by the Invention] However, in such a liquid crystal display device, as shown in FIG. 25, when misalignment occurs between the scanning signal line OL and the source electrode SDI, the scanning/signal line OL and Since the overlapping area with the source electrode SDI changes, the overlapping capacitance Cgs caused by overlapping the scanning signal line GL and the source electrode SDI becomes uneven, so the DC voltage applied to the protective film and the alignment film This causes so-called burn-in, where the previous image remains when switching between display screens. This invention was made to solve the above-mentioned problems, and its purpose is to provide a liquid crystal display device that does not cause burn-in. (Means for Solving the Problems) In order to achieve the above object, in the present invention, in an active matrix type liquid crystal display device in which a thin film transistor and a pixel electrode are constituent elements of a pixel, the source electrode of the gate electrode is The width of the part of the source electrode outside of both sides of the gate electrode is the same as the width of the part of the source electrode that is overlapped with the source electrode, and the width of the part of the source electrode that is outside of both sides of the gate electrode is the width of the part of the source electrode that is overlapped with the gate electrode. In addition, in order to achieve the above object, in this invention,
In an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode are constituent elements of a pixel, the width of a portion of the pixel electrode outside both sides of the electrode of the storage capacitor element is overlapped with the electrode of the storage capacitor element. The width of the portion of the electrode of the storage capacitor element outside both sides of the pixel electrode is made the same as the width of the portion overlapped with the pixel electrode. [Function] In this liquid crystal display device, the width of the portion of the gate electrode outside both sides of the source electrode is the same as the width of the portion overlapping with the source electrode, and the width of the portion of the source electrode outside of both sides of the gate electrode Since the width of the part is the same as the width of the part overlapped with the gate electrode, even if there is a seven-alignment misalignment between the gate electrode and the source electrode, the overlap area of the gate electrode and the source electrode will not change. The superposition capacitance Cgs caused by the superposition of the gate electrode and the source electrode does not become non-uniform. Furthermore, the width of the part of the pixel electrode outside both sides of the electrode of the storage capacitor element is the same as the width of the part overlapped with the electrode of the storage capacitor element, and the width of the part of the pixel electrode outside of both sides of the electrode of the storage capacitor element is Since the width of the portion overlapped with the pixel electrode is the same as the width of the portion overlapped with the pixel electrode, even if misalignment occurs between the pixel electrode and the electrode of the storage capacitor element, the overlap between the pixel electrode and the electrode of the storage capacitor element will not occur. Since the area does not change, the storage capacity C
add will not be uneven. [Example] A screen chart of the liquid crystal display section of an active matrix type color liquid crystal display device to which this invention is applied is shown in FIG. The cut section is shown in Figure 3. Furthermore, FIG. 4 (plan view of main part) shows the main part of the liquid crystal display section in which a plurality of pixels shown in FIG. 2 are arranged. As shown in FIGS. 2 to 4, the liquid crystal display device includes pixels having thin film transistors TPT and transparent pixel bridges ITO on the inner surface (liquid crystal side) of a lower transparent glass substrate SUBI. Lower transparent glass substrate SUBI
For example, the thickness is about 1.1 [am]. Each pixel is connected to two adjacent scanning signal lines (gate signal lines or horizontal signal lines) OL and two adjacent video signal lines (
(drain signal line or vertical signal line) DL (in a region surrounded by four signal lines). As shown in FIGS. 2 and 4, the scanning signal line OL is
They extend in the column direction, and a plurality of them are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. The thin film transistor TPT of each pixel has three
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFTI, TFT2, and TFT3. Each of the thin film transistors TPTI to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPT1 to TFT3 mainly has a gate electrode G.
T, insulation 1lIG engineering, i type (intrinsic,
．． Silicon (not doped with conductivity type determining impurities)
an i-type semiconductor layer AS made of Si), a pair of source electrodes S
It is composed of DI and a drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following explanation as well, for convenience, one side is fixed as a source and the other side is fixed as a drain. As shown in detail in FIG. 5 (a plan view of the main part in a predetermined manufacturing process), the gate electrode GT has a T-shape that projects from the scanning line GL in the row direction (downward in FIGS. 2 and 5). It is composed of shapes (branched into a T-shape). That is, the gate electrode GT is configured to extend substantially parallel to the video signal line DL, and the gate g1 pole GT is configured to protrude to the formation region of each of the thin film transistors TPTI to TFT3. There is. Thin film transistor T F T 1. The gate electrodes GT of the TFTs 3 are integrally formed (as a common gate electrode) and are continuously formed on the same scanning signal line GL. Gate fl! The pole GT is formed of a single-layer first conductive film g1 so as to avoid creating a large step as much as possible in the region where the thin film transistor TPT is formed. The first conductive film g1 is formed using, for example, chromium (Cr) IFJ formed by sputtering, and has a film thickness of approximately 1100 mm. This gate electrode GT. As shown in FIGS. 2, 3, and 6, it is formed to be thicker than the i-type semiconductor RAS so as to completely cover it (as viewed from below). Therefore, if a pack light such as a fluorescent lamp is attached below the lower transparent glass substrate SUBI, the gate electrode GT made of opaque chromium will cast a shadow on the i-type semiconductor layer A.
s is not illuminated by backlight light, and the conductive phenomenon described above due to light irradiation, that is, deterioration of the off-characteristics of the thin film transistor TPT, is less likely to occur. The original size of the gate electrode GT is the minimum width required to span the source/drain voltage exposure SD1 and SDZ (including the alignment margin between the gate electrode and the source/drain poles). Its depth, which determines the channel tOW, is determined by the ratio of the distance between the source and drain electrodes (channel-jt) to L, that is, the factor W/L that determines the mutual conductance gm. The size of the gate [f=m in this liquid crystal display device is of course made larger than the original size mentioned above. Game! ~ Considering only from the functional aspects of the gate and light shielding of the electrode GT, the gate electrode GT and its wiring GL may be integrally formed in a single layer, and in this case, silicon may be contained as an opaque conductive material. Aluminum (Al).
Pure aluminum, aluminum containing palladium (Pd), silicon, aluminum containing titanium (Ti), silicon, aluminum containing copper (Cu), etc. can be selected. The scanning signal line OL is the first conductor 1! It is composed of a composite film consisting of a film g1 and a second conductive film g2 provided on top of the film g1. The first conductive film g1 of this scanning signal line GL is
It is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally. Second conductive film g2
For example, an aluminum film formed by sputtering is used, and the film thickness is about 900 to 4000 [layers]. Second
The conductive film g2 is configured to reduce the resistance value of the scanning signal line GL and increase the signal transmission speed (writing characteristics of pixel information). The convergence dimension of the second conductive film g2 is made smaller than the width dimension of the first conductive film g1.In other words, since the scanning signal iGL can have a gentle stepped shape on its side wall, Upper row insulation film G
It is constructed so that the surface of 1 can be flattened. #I! 1 recording film GI is thin film transistor TPTI~TF
Used as the gate insulating film for each T3. The insulating film GI is formed on the upper wall of the gate electrode GT and the scanning signal line GL. For example, the insulating film Or is plasma CV
Using silicon nitride film formed by D, 3500r people]
Form the film with a thickness of approximately As described above, the surface of the #@edge film GI is flattened in the formation regions of the ゜'a film 1, transistors TFTI to TFT3, and the formation region of the scanning signal line OL. The i-type semiconductor layer AS is used as a channel formation region for each of the thin film transistors TPTI to TFT3 divided into a plurality of parts, as shown in detail in FIG. 6 (a plan view of a main part in a predetermined manufacturing process). The i-type semiconductor layer As of each of the plurality of divided thin film transistors TPT1 to TFT3 is integrally formed within the pixel. In other words, a plurality of thin film transistors TPT into which a pixel is divided
Each of TFTs 1 to 3 is composed of an island region of one (common) i-type semiconductor layer As. i-type semiconductor layer AS
is formed with a non-quality silicon film or a polycrystalline silicon film, and is formed with a film thickness of about 2000 μm. This i-type semiconductor layer AS is made of Si by changing the components of the supplied gas.
Subsequently to the formation of the insulating film GI consisting of 3N, it is formed in the same plasma CVD apparatus without being exposed to the outside from the apparatus. Further, a P-doped N+ type semiconductor layer do (FIG. 3) for ohmic contact is similarly formed continuously to a thickness of about 300 [layers]. Thereafter, the lower transparent glass substrate SUBI is taken out from the CVD apparatus, and an N+ type semiconductor 11d is formed using photo processing technology.
The O and i-type semiconductor layers AS are shown in FIGS. 2, 3, and 6.
As shown in the figure, it is patterned into independent islands. In this way, each of the i-type semiconductors 111AS of the thin film transistors TPTI to TFT3 divided into a plurality of pixels
By integrally configuring the thin film transistor TPT
The drain electrode SD2 common to each of I to TFT3 is connected to the i-type semiconductor layer AS (actually, the thickness of the first conductive film g1,
A step corresponding to the sum of the thickness of the N1 type semiconductor ldO and the thickness of the i type semiconductor layer
Since the drain electrode SD2 is only broken once from the D2 side toward the i-type semiconductor layer AS side, the probability that the drain electrode SD2 breaks is reduced, and the probability that point defects occur can be reduced.
In other words, in this liquid crystal display device, the point defects that occur within the pixel when the drain electrode SD2 crosses the step of the i-type semiconductor layer AS can be reduced to one-third. Although the layout of this liquid crystal display device is different, when the video signal IDL directly crosses over the i-type semiconductor layer AS and the video signal line DL in this overpassed portion is configured as the drain electrode SD2, the video signal lines D, L It is possible to reduce the probability that a line defect will occur due to a disconnection when the (drain electrode SD2) crosses the i-type semiconductor layer AS. In other words, the thin film transistor TP divided into a plurality of pixels
This is because by integrally configuring the i-type semiconductor layers AS of each of T1 to TFT3, the video signal line DL (drain electrode SD2) crosses the i-type semiconductor layer As only once (actually, (twice at the beginning and end of the ride). As shown in detail in FIGS. 2 and 6, the i-type semiconductor layer AS is provided to extend between the intersection (crossover section) between the scanning signal line GL and the video signal lIDL. There is. This extended i-type semiconductor layer As is configured to reduce short circuits between the scanning signal line GL and the video signal IDL at the intersection. Thin film transistors TPT1-T divided into a plurality of pixels
Each source electrode SDI and drain electrode S of FT3
D2 is shown in Figure 2. As shown in detail in FIGS. 3 and 7 (plan views of main parts in predetermined manufacturing steps), they are provided separately on the i-type semiconductor layer AS. Each of the source electrode SDI and drain electrode SD2 is configured such that when the bias polarity of the circuit changes, the source and drain are interchanged in operation. In other words, the thin film transistor TPT is bidirectional like the FET. Source electrode 5D1. Each of the drain electrodes SD2 is configured by sequentially overlapping a first conductive film d1, a second conductive film d2, and a third conductive film d3 from the lower layer side in contact with the N+ type semiconductor layer dO. The first conductive film d1, second conductive film d2, and third conductive film d3 of the source electrode SDI are formed in the same manufacturing process as each of the drain electrode SD2. The first conductive film d1 is a chromium film formed by sputtering, and has a film thickness of 500-1. The film thickness is approximately 0.600 cm (in this liquid crystal display device). When the chromium film is formed thickly, the stress becomes large, so the chromium film is formed to a thickness not exceeding about 2000[:person]. The chromium film has good contact with the N+ type semiconductor 1do, and constitutes a so-called barrier layer that prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer dO. As the first conductive film d1, in addition to the chromium film, high melting point gold JX (Mo.Ti.T
a, W) film, high melting point metal silicide (MoSi, Ti
Si. , TaSi2, WSi. , ) may be formed from a film. After patterning the first conductive film d1 by photo processing, the N+ type semiconductor layer dO is removed using the same photo processing mask or using the first conductive film d1 as a mask. In other words, the N+ type semiconductor layer dO remaining on the i type semiconductor layer AS is
Portions other than the conductive film d1 are removed by self-alignment. At this time, since the N+ type semiconductor ldo is etched so that its entire thickness is removed, the i type semiconductor layer AS is also slightly etched at its surface, but the extent can be controlled by the etching time. Thereafter, the second conductive film d2 is formed by aluminum sputtering to a thickness of 3,000 to 5,500 mm (in this liquid crystal display device, the film thickness is about 3,500 mm). The aluminum film has less stress than the chromium film and can be formed to a thick film thickness, making it suitable for the source electrode SD.
The first configuration is such that the resistance values of the I, D1 and D1 noise electrodes SD2 and the video signal line DL are reduced. Second conductive film d2
is configured to increase the operating speed of the thin film transistor TPT and the signal transmission speed of the video signal line DL. In other words, the second conductive film d2 can improve the write characteristics of the pixel. In addition to the aluminum film, the second conductive film d2 may be formed of an aluminum film containing silicon, palladium, titanium, copper, or the like as an additive. After battering the second conductive film d2 using photo processing technology,
The third conductive film d3 is a transparent conductive film (r
To: Nesa film), the film thickness is 300 to 2400 [people] (in this liquid crystal display device, the film thickness is about 1200 [people]).
is formed. This third conductive film d3 is connected to the source electrode SD
I, the drain electrode SD2 and the video signal line DL, and the transparent pixel electrode IT○. First conductive film d1 of source electrode SD1, drain electrode SD
Each of the two first conductive films d1 has an upper second conductive film d1.
The channel forming region side is configured to have a larger size than the second and third conductive films d3. That is, the first conductive film d1
Even if mask misalignment occurs in the manufacturing process between the first conductive film d1, the second conductive film d2, and the third conductive film d3, the size is larger than that of the second conductive film d2 and the third conductive film d3. (The channel forming region side of each of the first to third conductive films d1 to d3 may be on-the-line). The first conductive film d1 of the source electrode SDI and the first conductive film d1 of the drain electrode SD2 are each configured to define the gate length L of the thin film transistor TPT. In this way, in the thin film transistors TPTI to TFT3 divided into a plurality of pixels, the source electrodes SDI. By configuring the channel formation region side of each first conductive film d1 of the drain electrode SD2 to have a larger size than the second conductive film d2 and the third conductive film d3, the source electrode S
DI, the first conductivity lld of each of the drain electrode SD2
The gate length L of the thin film transistor TPT can be defined by the dimension between l. Separation dimension between the first conductive films d1 (
The gate length) can be defined by processing accuracy (patterning accuracy), so thin film transistors TPT1~
The gate length L of each TFT 3 can be made uniform. As described above, the source electrode SDI is connected to the transparent pixel electrode IT.
Connected to O. The source electrode SD1 has a step shape of the i-type semiconductor layer As (a step corresponding to the sum of the film thickness of the first conductive film g1, the film thickness of the N+ type semiconductor layer dO, and the film thickness of the i-type semiconductor counterfeit AS). ). Specifically, the source electrode SDI includes a first conductive film 111dl formed along the step shape of the i-type semiconductor layer AS, and a transparent pixel electrode IT formed above the first conductive film d1.
a second conductive film d2 formed with a smaller size on the side connected to o, and a first conductive film d exposed from this second conductive film d2.
1, and a third conductive film d3 connected to 1. The first conductive film d1 of the source electrode SD1 includes an N+ type semiconductor layer d
It has good adhesion with O and is mainly configured as a barrier layer against diffused substances from the second conductive film d2. The second conductive film d2 of the source electrode SDI cannot be formed thickly because the chromium film of the first conductive film d1 increases stress and cannot overcome the step shape of the i-type semiconductor layer AS.
It is configured to overcome the type semiconductor layer As. In other words, the second conductive film d2 improves the stepping force barrier by forming it thickly. Since the second conductive film d2 can be formed thickly, it greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). The third conductive film d3 is the second conductive film d2
Since the step shape caused by the i-type semiconductor layer AS cannot be overcome, the second conductive film d2 is configured to be connected to the exposed first conductive film d1 by reducing its size. The first conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connecting portion between them, so that they can be reliably connected. In this way, the source electrode SD of the thin film transistor TPT
I, a first conductive film d1 as a barrier layer formed along at least the i-type semiconductor layer AS, and this first conductive film d
A second conductive film d2 is formed on top of the first conductive film d2 and has a smaller specific resistance value than the first conductive film d1 and a smaller size than the first conductive film d1. A third transparent pixel electrode made of ITO is formed on the exposed first conductive film d1.
By connecting the conductive film d3, the thin film transistor T
Since the PT and the transparent pixel electrode ITO can be reliably connected, point defects caused by disconnections can be reduced. Moreover, the second conductive film d2 (aluminum film) having a low resistance value can be used for the source electrode SD1 due to the barrier effect of the first conductive film d1, so that the resistance value can be reduced. The drain electrode SD2 is configured integrally with the video signal line DL, and is formed in the same manufacturing process. The drain electrode SD2 has an L-shape that protrudes in the column direction intersecting the video signal line DL. That is, the respective drain electrodes SD2 of the thin film transistors TPTI to TFT3 divided into a plurality of pixels are connected to the same video signal line DL. The transparent pixel electrode ITO is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode ITO includes three transparent pixel electrodes (divided transparent pixel electrodes) ITOI. It is divided into ITO2 and ITO3. Transparent pixel electrode IT
OI is the source electrode SDI of the thin film transistor TFTI
It is connected to the. The transparent pixel electrode ITO2 is connected to the source electrode SDI of the thin film transistor TPT2. The transparent pixel electrode ITO3 is a thin film transistor TFT3.
is connected to the source electrode SDI of. Each of the transparent pixel electrodes ITOI to ITO3 has substantially the same size as each of the thin film transistors TPTI to TFT3. Each of the transparent pixel electrodes ITOI to ITO3 has the respective i-type semiconductor layers AS of the thin film transistors TPTI to TFT3 integrally configured (the divided thin film transistors TPT are arranged in a concentrated manner). , it is constructed in an L-shape. In this way, the thin film transistor TPT of the pixel arranged in the intersection area of two adjacent scanning signal lines GL and two adjacent video signal lines DL is
By dividing the pixel into FT1 to TFT3 and connecting each of the divided transparent pixel electrodes ITOI to ITO3 to each of the divided thin film transistors TPT1 to TFT3, a divided part of the pixel (for example, thin film transistor TFTI) is formed. becomes a point defect,
Since the pixel as a whole is no longer a point defect (thin film transistors TFT2 and TFT3 are not point defects), it is possible to reduce point defects in the pixel as a whole. Further, since some of the point defects in which the pixel is divided are smaller than the entire area of the pixel (in the case of this liquid crystal display device, the area is one-third of the pixel), the point defects can be made difficult to see. Can be done. Also. Divided transparent pixel electrodes IT01 to I of the pixel
By configuring each TO3 to have substantially the same size, the area of point defects within a pixel can be made uniform. Further, the divided transparent pixel electrodes IT○1 to I of the pixel
By configuring each of the TO3 to have substantially the same size, the respective liquid crystal capacitances (Cpix) constituted by each of the transparent pixel electrodes T'I'01 to ITO3 and the common transparent pixel electrode TO, and this Transparent pixel electrode I
It is possible to make uniform the overlap capacitance (Cgs) caused by the overlap between the transparent pixel electrodes ITOI-ITO3 added to each of TOI-ITO3 and the gate electrode GT. In other words, since each of the transparent pixel electrodes ITOI to ITO3 can have a uniform liquid crystal capacitance and a superimposed capacitance, the DC component that is to be applied to the liquid crystal molecules of the liquid crystal Lc due to this superimposed capacitance can be made uniform. If this method of canceling the DC component is adopted, it is possible to reduce variations in the DC component applied to the liquid crystal of each pixel. A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode ITO. IfllvAPSV1ha, main ni l wA}-ra:/
It is formed to protect the screen TFT from moisture, etc., and a material with high transparency and good moisture resistance is used. The protective film PSVI is formed of a silicon oxide film or a silicon nitride film formed by plasma CVD, for example.
000~II. The film thickness is approximately .000 [person] (in this liquid crystal display device, the film thickness is about .aoooc [person]). A shielding film LS is provided above the protective film PSVI on the thin film transistor TFT to prevent external light from entering the i-type semiconductor layer AS used as a channel formation region. As shown in FIG. 2, the shielding film LS is configured within a region surrounded by a dotted line. The shielding film LS is formed of, for example, an aluminum film or a chromium film that has a high light shielding property, and is formed to a thickness of about 1000 r by sputtering. Therefore, the common semiconductor layer AS of the thin film transistors TPT1 to TFT3 is sandwiched between the upper and lower light shielding films LS and the thick gate electrode mGT, so that it is not exposed to external natural light or backlight.6 The light shielding film LS and the gate electrode GT is thicker than the semiconductor layer As and is formed in a similar shape to it, and the sizes of the two are considered to be approximately the same (
In the figure, the gate electrode GT is drawn smaller than the light shielding film LS so that the boundary line can be seen). Note that it is also possible to attach the backlight to the upper transparent glass substrate SUB2 side and set the lower transparent glass substrate SUBI to the observation side (externally exposed side). In this case, the light shielding film LS is used for backlight light, and the gate electrode GT is used for natural light. Acts as a light shield. The thin film transistor TPT is configured such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large. That is, the thin film transistor TPT is configured to control the voltage applied to the transparent pixel electrode ITO. The liquid crystal LC is defined and enclosed by a lower alignment film ORII and an upper alignment film ○RI2 that set the orientation of liquid crystal molecules in a space formed between a lower transparent glass substrate StJB1 and an upper transparent glass substrate SUB2. There is. The lower alignment film ○RII is formed on the protective film PSVI on the lower transparent glass substrate SUBI side. On the inner surface (liquid crystal side) of the upper transparent glass substrate SUB2, a color filter F L, a protective film PSv2, a common transparent pixel electrode (COM.) ITO, and the upper alignment film OR are disposed.
I2 are sequentially stacked. The common transparent pixel electrode ITO is connected to the lower transparent glass substrate S.
It faces the transparent pixel electrode IT○ provided for each pixel on the UBI side, and is configured integrally with another adjacent common transparent pixel electrode ITO. A common voltage V corn is applied to this common transparent pixel electrode ITO. The common voltage vcoII1 is an intermediate potential between the low-level driving voltage V d min and the high-level drive voltage V d n+ax applied to the video signal line DL. The color filter FIL is configured by coloring a dyed base material made of a resin material such as acrylic resin with a dye. The color filter FIL is arranged for each pixel at a position facing the pixel, and is colored differently. That is, the color filter FIL, like the pixel, is configured within the intersection area of two adjacent scanning signal lines OL and two adjacent video signal lines DL. Each pixel has a color filter F
Each predetermined color filter of IL is divided into a plurality of filters. Color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter formation area is removed using photolithography technology. After this, the dyed base material is dyed with red dye, fixed treatment is applied, and red filter R
form. Next, a green filter G and a blue filter B are sequentially formed by performing similar steps. In this way, by forming each color filter of the color filter FIL in the intersection area facing each pixel, the scanning signal line GL and the video signal line DL are present between each color filter of the color filter FIL, so that Corresponding to their existence, it is possible to secure an alignment margin between each pixel and each color filter of the color filter FIL (enlarge the alignment margin). Furthermore, when forming each color filter of the color filter FIL, it is possible to ensure alignment margin between different color filters. That is, in this liquid crystal display device, a pixel is formed within the intersection area of two adjacent scanning signal lines OL and two adjacent video signal lines DL, and this pixel is divided into a plurality of parts, and the pixel is divided into a plurality of parts. By forming each color filter of the color filter FIL in the position where the color filter FIL is located, it is possible to reduce the above-mentioned point defects and to secure alignment margin between each pixel and each color filter. The protective film PSV2 is provided to prevent the dyes used to dye the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of a transparent resin material such as acrylic resin or epoxy resin. This liquid crystal display device has a lower transparent glass substrate SUBl side,
It is assembled by forming each layer on the upper transparent glass substrate SUBZ side separately, then overlapping the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, and sealing the liquid crystal LC between them. As shown in FIG. 4, each pixel of the liquid crystal display section is arranged in the same column direction as the direction in which the scanning signal $1GL extends. A plurality of them are arranged and constitute each of the pixel columns X1, X,, X3, X4, . . . Each pixel column X1,X,,X,,
Each pixel of X4,... is a thin film transistor T
FTI~TFT3 and transparent pixel electrode IT01~ITO
3 are arranged in the same position. That is, pixel columns X1, X. , . . . , the thin film transistors TPTI to TFT3 are arranged on the left side, and the transparent pixel electrodes ITOI to ITO3 are arranged on the right side. Each pixel in the next pixel column X2, x, . . . in the row direction of each pixel column Xi, X, . . . It is composed of pixels arranged line-symmetrically with respect to the video signal line DL, that is, pixel columns X,, X,,...
Each pixel includes thin film transistors TPT1 to TF.
The arrangement position of T3 is on the right side, transparent pixel electrode ITOI ~ ITO
3 is arranged on the left side. And pixel row X
, I, x4, . . . are both pixel columns X■,
Each pixel of X,... is shifted (shifted) by half a pixel in the column direction. In other words,
If each pixel interval of pixel row 5 pixel interval (0.5
pitch) is off. The video signal line DL, which extends in the row direction between each pixel, is connected by a half pixel interval (
0.5 pitch) is configured to extend in the column direction. In this way, in the liquid crystal display section, the thin film transistor T
A plurality of pixels with the same PT and transparent pixel electrode ITO are arranged in the column direction to form a pixel column X, and the next pixel column X of the pixel column X and the pixels of the previous pixel column By configuring pixels arranged symmetrically with respect to line DL, and moving the next pixel column by half a pixel with respect to the previous pixel column, it is possible to As shown in the main part plan view in the combined state), the pixel in the previous pixel row The pixel in which the same color filter of X is formed (for example, the pixel in which the red filter R of pixel row X is formed) can be separated by 1.5 pixel intervals (1.5 pitch). In other words, the pixels in the previous pixel column
The color filter FIL can have an RGB triangular arrangement structure. RG of color filter FIL
The triangular arrangement structure B can improve the mixing of each color, and therefore can improve the resolution of a color image. Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, it is possible to eliminate the routing of the video signal line DL and reduce the area occupied by the video signal line DL, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. The circuit configuration of this liquid crystal display section is shown in FIG. 9 (equivalent circuit diagram of the liquid crystal display section). X i G , X i + I G , shown in FIG.
−= Ha, green color? The video signal line DL is connected to the pixel in which the router G is formed. X i B , X i
+ I B , - are video signal lines DL connected to the pixels in which the blue filter B is formed. X i + I
R, X i + 2 R, . . . are video signals MDL connected to the pixels in which the red filter R is formed.6 These video signals 11ADL are selected by the video signal drive circuit. Yi is a scanning signal line OL that selects the pixel column X shown in FIGS. 4 and 8. Similarly, Y
Each of i+1-, Yx+2+... is a scanning signal line GL that selects each of the pixel columns X2tX3,.... These scanning signal lines OL are connected to a vertical scanning circuit. The center part of FIG. 3 shows the cross section of one pixel part, while the left side shows the cross section of the left edge part of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 where external lead wiring exists. . The right side shows a cross section of the right edge portion of the transparent glass substrates SUBI and SUB2 where no external lead wiring is present. The sealing materials SL shown on the left and right sides of FIG. 3 are as follows:
It is configured to seal the liquid crystal LC, and is formed along the entire edges of the transparent glass substrates SUBI and SUB2 except for the liquid crystal sealing opening (not shown). The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode ITO on the side of the upper transparent glass substrate SUB2 is coated with silver paste material S at least in one place.
The IL is connected to an external lead wiring formed on the side of the lower transparent glass substrate SUBI. This external lead wiring is formed in the same manufacturing process as each of the aforementioned gate electrode GT, source electrode SDI, and drain electrode SD2. The alignment films ORII and ORI2, transparent pixel electrode IT
O, common transparent pixel electrode iTO, protective film PSv1 and P
The respective layers of S V 2 and the insulating film GI are formed inside the sealing material SL. The polarizing plate POL is formed on the outer surface of each of the lower transparent glass substrate SUBI and the upper transparent glass substrate SUB2. FIG. 10 is a cross-sectional view of the main part of the pixel and the periphery of the seal part of the liquid crystal display part of another active matrix color liquid crystal display device to which the present invention is applied, and FIG.
0 is a plan view showing one pixel of the liquid crystal display section of the liquid crystal display device shown in FIG. 14 to 16 are plan views of main parts of a liquid crystal display section in which a plurality of pixels are arranged. FIGS. 14 to 16 are plan views of main parts of the pixel shown in FIG. FIG. 3 is a plan view of main parts in a state in which color filters are superimposed. In this liquid crystal display device, it is possible to improve the aperture ratio of each pixel in the liquid crystal display section, reduce the direct current component applied to the liquid crystal, reduce point defects in the liquid crystal display section, and reduce black unevenness. can. In this liquid crystal display device, as shown in FIG. 11, the i-type semiconductor layer AS in each pixel of the liquid crystal display section is replaced by a thin film transistor T
It is divided into FTI to TFT3. In other words, the thin film transistors TPT1 to TPT1 divided into a plurality of pixels
Each of the TFTs 3 is composed of an independent island region of an i-type semiconductor layer AS. Also. Each of the transparent pixel electrodes IT'01 to TO3 connected to each of the thin film transistors TPT1 to TFT3 is connected to the scanning signal line GL of the next stage in the row direction on the side opposite to the side connected to the thin film transistors TPTI to TFT3. They are superimposed. This superposition constitutes a storage capacitor element (electrostatic capacitor element) Cadd in which each of the transparent pixel electrodes ITOI to ITO3 is used as one electrode and the next stage scanning signal line GL is used as the other electrode. The dielectric film of this storage capacitance element C add is a thin film transistor TP
It is composed of the same layer as the insulating film GI used as the gate insulating film of T. The gate electrode GT is formed to be thicker than the i-type semiconductor 11IAs, as in the liquid crystal display device shown in FIG.
In this liquid crystal display device, thin film transistors TPTI to TF
Since T3 is formed for each independent i-type semiconductor JilA$, a thick pattern is formed for each thin film transistor TFT. In addition, the scanning signal line GL of the upper transparent glass substrate SUB2,
Video signal line DL. Since the black matrix pattern BM is provided in the part corresponding to the thin film transistor TPT, the outline of the pixel becomes clear, the contrast is improved, and external natural light is directed to the thin film transistor T.
This will prevent you from hitting the PT. The equivalent circuit of the pixel shown in Fig. 11 is shown in Fig. 18 (equivalent circuit diagram). In FIG. 18, as before, C
gs is a superimposed capacitance formed by the gate electrode GT and source electrode SDI of the thin film transistor TPT. The dielectric film of the superposed capacitance Cgs is an insulating film GI a C
pix is the transparent pixel electrode ITO (PIX) and the common transparent pixel electrode [! This is a liquid crystal capacitor formed between ITO (COM). The dielectric film of the liquid crystal capacitor C pix is the liquid crystal LC.
Protective film psv1 and alignment film ORI 1. OR! 2* Vie is the midpoint potential. The storage capacitance element C add is a thin film transistor TP
When T switches, the midpoint potential (pixel electrode potential)
It moves to reduce the influence of gate potential change ΔVg on vlc. This situation can be expressed as the following formula. ΔV lc= ((Cgs/(Cgs+Cadd+Cp
ix))X ΔVg Here, ΔVlc represents the change in midpoint potential due to ΔVg. This change Δv1c causes a DC component applied to the liquid crystal, but the storage capacitance element C a
The larger the storage capacity of dd, the smaller its value can be. Further, the storage capacitor element C add also has the effect of lengthening the discharge time, so that video information is stored for a long time after the thin film transistor TPT is turned off. Reduction of the DC component applied to the liquid crystal LC. It is possible to improve the lifespan of the liquid crystal LC and reduce so-called burn-in, where the previous image remains when switching between liquid crystal display screens. As described above, since the gate electrode GT is made large enough to completely cover the semiconductor layer AS, the overlapping area with the source/drain electrodes SDI and SD2 increases, and therefore the parasitic capacitance Cgs increases and the midpoint potential V' The opposite effect occurs that lc becomes more susceptible to the influence of gate (scanning) signal Vg. However, this disadvantage can also be eliminated by providing the storage capacitor element C add. Further, in a liquid crystal display device having pixels in an intersection area of two scanning signals @GL and two video signal lines DL, one scanning signal line GL of the two scanning signal lines OL
The thin film transistor TPT of the pixel selected in is divided into a plurality of parts, and the divided thin film transistors TPT1 to TF
A transparent pixel electrode ITO divided into a plurality of parts (ITOI to ITO3) is connected to each of T3, and this pixel electrode ITO is used as one electrode to each of the divided transparent pixel electrodes IT○1 to ITO3. The other scanning signal line GT of the two scanning signal lines GL. , is used as a capacitive electrode line and the other electrode is a storage capacitive element C.
By configuring add, as described above, only a divided part of the pixel becomes a point defect, and the pixel as a whole is not a point defect, so it is possible to reduce the point defect of the pixel, and also Since the DC component applied to the liquid crystal LC can be reduced by the storage capacitor element C add,
The lifespan of the liquid crystal LC can be improved. In particular, by dividing the pixel, the gate electrode GT and source electrode SDI or drain electrode SD of the thin film transistor TPT can be separated.
It is possible to reduce point defects caused by short circuits between the transparent pixel electrodes IT○1 to TO3 and the other electrode (capacitance electrode line) of the storage capacitor element Cadd. Defects can be reduced. In this liquid crystal display device, the number of point defects on the latter side is one third. As a result, some of the point defects into which the pixel is divided are smaller than the entire area of the pixel, making it difficult to see the point defects. The storage capacitance of the storage capacitance element C add is determined by the liquid crystal capacitance Cpj. from the writing characteristics of the pixel. 4 to 8 times (4
・CpLx(Cadd<8・Cpix). 8 to 32 times the superposition capacitance Cgs (8 ・C gs<
Set to a value of approximately C add < 32・Cgs). Further, the scanning signal line GL is connected to a first conductive film (chromium film) g.
The other electrode of the storage capacitor element Cadd, that is, the branched portion of the capacitor electrode wire is formed of a composite film in which a second conductive film (aluminum film) g2 is superimposed on a second conductive film (aluminum film) g2. By configuring the single-layer film made of the conductive film g1, the resistance value of the scanning signal line GL can be reduced and the writing characteristics can be improved, and the storage capacitor element C ad
Since one electrode (transparent pixel electrode IT○) of the storage capacitor element C add can be reliably bonded onto the insulating film GI along the step portion based on the other electrode of d, one electrode of the storage capacitor element C add It is possible to reduce disconnection of the electrodes. Further, by configuring the other electrode of the storage capacitor element Cadd with the single-layer first conductive film g1 and not comprising the second conductive film g2 which is an aluminum film, the other electrode of the storage capacitor element Cadd is formed by hillocks of the aluminum film. Short circuit between one electrode and the other electrode can be prevented. The source electrode SD is provided in a portion between each of the transparent pixel electrodes IT○1 to IT○3 that are overlapped to form the storage capacitor element Cadd and the capacitor electrode line.
Similarly to I, the first conductive wA is used to prevent the transparent pixel electrode I
d. An island region composed of the first and second conductive films d2 is provided. This island region is configured to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITO. In this way, compared to the first conductive film d1 and the first conductive film d1 formed thereon, between one electrode of the storage capacitor element Cadd and the insulating film Gl used as its dielectric film, Second conductive film d having a small specific resistance value and small size
2, and by connecting the one electrode (third conductive film d3) to the first conductive film d1 exposed from the second conductive film d2 of the base layer, a storage capacitor element is formed. Since one electrode of the storage capacitor element C add can be reliably bonded along the stepped portion based on the other electrode of the storage capacitor element C add, disconnection of one electrode of the storage capacitor element C add can be reduced. A storage capacitor element C ad is attached to the transparent pixel electrode IT○ of the pixel.
The liquid crystal display section of the liquid crystal display device provided with d is constructed as shown in FIG. 20 (equivalent circuit diagram showing the liquid crystal display section). The liquid crystal display section is composed of repeating unit basic patterns including pixels, scanning signal lines OL, and video signal lines DL. As shown in FIG. 20, the final stage scanning signal line GL (or first stage scanning signal line GL) used as a capacitor electrode line is connected to a common transparent pixel electrode (Vcom) I To
Connect to. As shown in FIG. 3, the common transparent pixel electrode ITO is connected to an external lead wire by a silver paste material SL at the peripheral edge of the liquid crystal display device. Moreover, some conductive layers (gl and g2) of this external lead wiring
is constructed in the same manufacturing process as the scanning signal aGL. As a result, the final stage scanning signal line OL (capacitive electrode line) can be easily connected to the common transparent pixel electrode ITO.
In this way, by connecting the final stage of the capacitive electrode line to the common transparent pixel electrode (Vcom) I To of the pixel, the final stage of the capacitive electrode line is integrated with a part of the conductive layer of the external wiring. Moreover, since the common transparent pixel electrode ITO is connected to the external lead wiring, the final stage capacitor electrode line can be connected to the common transparent pixel electrode ITO with a simple configuration.
You can connect to. In addition, the liquid crystal display device is based on the DC cancellation method (DC cancellation method) described in Japanese Patent Application No. 62-95125 previously filed by the applicant of the present application, as shown in FIG. 19 (time chart). By controlling the fluctuation voltage of the scanning signal line DL, it is possible to further reduce the DC component applied to the liquid crystal LC. In FIG. 19, Vi
is the drive voltage of an arbitrary scanning signal line GL, and Vi+1 is the drive voltage of the scanning signal line OL at the next stage. Vee is a low-level drive voltage Vdn+i applied to the scanning signal line GL.
n. Vd d is a high-level fluctuation voltage Vdmax applied to the scanning signal line GL. Each time t=t1~t
4, the voltage change amount Δv1 to ΔV.4 of the midpoint potential vIC (see FIG. 18). is the total capacitance of pixels (Cgs+C
pix+Cadd) as C, the following equation is obtained. ΔVx= (Cgs/C)・V2 ΔV2=+(Cgs/C)−(V1+V2)−(Cad
d/C)・V 2 ΔV3= (Cgs/C)・V1 + (Cadd/C) {V1+V2) ΔV,=-(Cadd/C)・V 1 Here, the drive voltage applied to the scanning signal line GL is sufficient (see below)

[Note 1: At times t1 and t2, the change in the collective voltage Vi affects the midpoint potential Vlc, but during the period from t2 to t3, the midpoint potential Via is made the same potential as the video signal potential through the signal line Xi. (Enough writing of video signal). The potential applied to the liquid crystal LC is almost determined by the potential immediately after the thin film transistor TPT is turned off (the off period of the thin film transistor TPT is overwhelmingly longer than the on period). Therefore, when calculating the DC component applied to the liquid crystal LC, the period te to t3 can be almost ignored, and it is only necessary to consider the potential immediately after the thin film transistor TPT is turned off, that is, the influence of the transient at times t, t4. Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero. In other words, in the DC cancellation method, the drop caused by the pull in of the midpoint potential Vlc by the superimposed capacitance Cgs is boosted by the rotating voltage applied to the storage capacitor element Cadd and the next stage scanning signal line OL (capacitive electrode line). , the DC component applied to the liquid crystal LC can be made extremely small. As a result, the life of the liquid crystal LC of the liquid crystal display device can be improved. Of course, if the gate electrode GT is increased in size in order to increase the light shielding effect, the storage capacitance of the storage capacitance element Cadd may be increased accordingly. In this DC cancellation method, as shown in FIG. 21 (equivalent circuit diagram showing a liquid crystal display section), the first stage scanning signal line OL (or capacitive electrode line) is connected to the final stage capacitive electrode line (or scanning signal line GL). It can be adopted by connecting to. Although four scanning signal lines GLL are not shown in FIG. 21 for convenience, several hundred scanning signal lines OL are actually arranged. The first-stage scanning signal line GL and the final-stage capacitor electrode line are connected by internal wiring within the liquid crystal display section or external lead wiring. In this way, in the liquid crystal display device, by connecting the first-stage scanning signal line GL to the last-stage capacitive electrode line, all of the scanning signal, iptOL, and capacitive electrode line can be connected to the vertical scanning circuit. Therefore, a DC cancellation method can be adopted. As a result, it is possible to reduce the direct current component applied to the liquid crystal LC, thereby improving the life of the liquid crystal LC. FIG. 1 is a plan view of a main part showing one pixel of a liquid crystal display section of an active matrix type color liquid crystal display device according to the present invention, and FIG. 22 is a partially sectional view of the same.7 In this liquid crystal display device, The width of the portion GT-A of the gate electrode GT that is outside both sides of the source electrode SDI is the same as the width of the portion GT-H that is overlapped with the source electrode SDI, and the width of the portion GT-A that is outside of both sides of the source electrode SDI is the same as the width of the portion GT-H that is overlapped with the source electrode SDI. Since the width of the outer portion SDI-A is the same as the width of the portion SDI-B overlapped with the gate electrode GT, even if misalignment occurs between the gate electrode GT and the source electrode SDI, the gate electrode GT and the source electrode Since the overlapping area with the electrode SDi does not change, the overlapping capacitance Cgs caused by overlapping the gate electrode GT and the source electrode SD1 does not become non-uniform. Further, the width of the portion ITO-A of the transparent pixel electrode ITO which is outside both sides of the electrode CaddT of the storage capacitor element Cadd is the same as the width of the portion ITO-B which is overlapped with the electrode CaddT. Since the width of the portion CaddT-A outside both sides of the transparent pixel electrode IT○ is the same as the width of the portion CaddT-H overlapping with the transparent pixel electrode IT○, the transparent pixel electrode ITO and the electrode CaddT Even if misalignment occurs, the overlapping area of the transparent pixel electrode ITO and the electrode CaddT does not change, so the storage capacitance Cadd will not become non-uniform. In this way, the superposition capacitance Cgs does not become non-uniform, and the holding capacitance Cadd does not become non-uniform, so the DC voltage applied to the protective film PSv1 and the alignment film ORrl becomes non-uniform. Therefore, so-called burn-in, in which the previous image remains when switching the display screen, does not occur. Next, a method for manufacturing the liquid crystal display device shown in FIGS. 1 and 22 will be described. first. A first conductive film g1 made of chromium and having a film thickness of 1100 μm is provided on a lower transparent glass substrate SUBI made of 7059 glass (trade name) by sputtering. Next, the first layer of the scanning signal line GL, the gate electrode GT, and the storage capacitor element C are selectively etched by photolithography using a ceric ammonium nitrate solution as an etching solution. Add electrode C add T is formed. Next, after removing the resist with stripping liquid S502 (trade name), 02 ashing is performed for 2 minutes. Next, a second conductive film g2 made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, etc. and having a film thickness of iooc is provided by sputtering. Next, the second layer of the scanning signal line GL is formed by selectively etching the second conductive film g2 by photolithography using a mixed acid of phosphoric acid, nitric acid, and acetic acid as an etchant. Next, SF and gas are introduced into a dry etching apparatus to remove residues such as silicon, and then the resist is removed. Next, ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD apparatus to form a silicon nitride film with a film thickness of 3,500 mm, and silane gas and hydrogen gas were introduced into the plasma CVD apparatus to form a silicon nitride film with a film thickness of 2,200 mm. [After forming an I-type non-quality silicon film, hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus to form an N+ type silicon film with a film thickness of 400 [m]. Next, the N" type silicon film and the i type amorphous silicon film are selectively etched by photolithography using SF as a dry etching gas, thereby forming an i type semiconductor layer AS. ? Next, after removing the resist, the silicon nitride film is selectively etched by photolithography using SF as a dry etching gas, thereby forming an insulating film GI. Next, after removing the resist, a first conductive film d1 made of chromium and having a thickness of 600 [layers] is formed by sputtering. Next, the first layer of the video signal line DL, source electrode SDI, and drain electrode SD2 is formed by selectively etching the first conductive film d1 using photolithography. Next, before removing the resist, ccn4 and slF are introduced into a dry etching apparatus to selectively etch the N+ type silicon film, thereby forming a groove for the N+ type semiconductor layer do. Next, after removing the resist, perform 0■ ashing for 1 minute. Next, a second conductive film d2 having a thickness of 3,500 mm and made of anoleminium-palladium, anoleminium-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, etc. is provided by sputtering. Next, the second conductive film d2 is selectively etched using photolithography to form a second layer of the video signal line DL, source electrode SDI, and drain electrode SD2. Next, after removing the resist, 02 ashing is performed for 2 minutes. Next, a third conductive film d3 made of an ITO film having a thickness of 1200 [layers] is provided by sputtering. Next, the video signal line DL, source electrode SDI. The third layer of the drain electrode SD2, the gate terminal, the uppermost layer of the drain terminal, and the transparent pixel electrode ITO are formed. Next, after removing the resist, ammonia gas, silane gas, and nitrogen gas were introduced into plasma CVDMI to form a silicon nitride film with a film thickness of 1 [AIIa]. Next, a protective film PSVI is formed by selectively etching the silicon nitride film by photolithography using SF as a dry etching gas. FIG. 23 is a sectional view showing a part of another liquid crystal display device according to the present invention. In the figure, d11 is a first conductive film made of an ITO film, d12 is a second conductive film made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, etc. The second conductive film dl2 constitutes the video signal 11DL, the source electrode SDI, and the drain electrode SD2, and the first conductive film dll constitutes the transparent pixel electrode ITO. Although this invention has been specifically explained above based on the above-mentioned embodiments, this invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention. For example, the present invention can be applied to a liquid crystal display device in which each pixel of the liquid crystal display section is divided into two or four parts. However, if the number of pixel divisions becomes too large, the aperture ratio will decrease, so as mentioned above, about 2 to 4 divisions is appropriate. Further, in the above embodiment, an inverted staggered structure is shown in which gate electrode formation→gate insulating film formation→semiconductor layer formation→source/drain electrode formation, but the present invention can also be applied to a staggered structure in which the vertical relationship or the order of formation is reversed. It is valid. 〔Effect of the invention〕

As explained above, in the liquid crystal display device according to the present invention, the width of the portion of the gate electrode outside the both sides of the source electrode is the same as the width of the portion overlapped with the source electrode, and Since the width of the outer side of both sides is the same as the width of the overlapped part with the gate electrode, even if there is misalignment between the gate electrode and the source electrode, the overlap area of the gate electrode and the source electrode is does not change, so the superposition capacitance Cgs caused by the superposition of the gate electrode and source electrode does not become non-uniform, and the DC voltage applied to the protective film and alignment film does not become non-uniform. , so-called burn-in, where the previous image remains when switching between display screens, does not occur. Furthermore, the width of the part of the pixel electrode outside the rain side of the electrode of the storage capacitor element is the same as the width of the part overlapped with the electrode of the storage capacitor element, and Since the edge of the outer part is the same as the cap of the part overlapped with the pixel electrode, even if there is a misalignment between the pixel electrode and the electrode of the storage capacitor element, the overlap between the pixel electrode and the electrode of the storage capacitor element will be maintained. Since the combined area does not change, the holding capacitance C add becomes uneven.
Since the DC voltage applied to the protective film and the alignment film does not become non-uniform, so-called burn-in, in which the previous image remains when the display screen is switched, does not occur. In this way, the effects of this invention are remarkable.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a main part showing one pixel of the liquid crystal display of an active matrix color liquid crystal display device according to the present invention, and FIG. 2 is an active matrix color liquid crystal display device to which the present invention is applied. 3 is a sectional view of the section taken along the line nn in FIG. 2 and the area around the sealing part. FIG.
A plan view of the main parts of a liquid crystal display section in which a plurality of pixels are arranged as shown in the figure,
5 to 7 are plan views of the main parts of the pixel shown in FIG. 2 in a predetermined manufacturing process, FIG. 8 is a plan view of the main parts in a state where the pixel shown in FIG. 4 and the color filter are superimposed, 9th
The figure is an equivalent circuit diagram showing the liquid crystal display section of the above-mentioned active matrix color liquid crystal display device, and FIG. 10 is the liquid crystal display section of another active matrix color liquid crystal display device to which the present invention is applied. 11 is a plan view showing one pixel of the liquid crystal display section of the liquid crystal display device shown in FIG. 10, and FIG. 12 is a cross-sectional view taken along A-A in FIG. 11. 13 is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 11 are arranged, and FIGS. 17 is a plan view of the main part in a state where the pixel shown in FIG. 13 and the color filter are superimposed, FIG. 18 is an equivalent circuit diagram of the pixel described in FIG. 11, Figure 19 is a time chart showing the fluctuation voltage of the scanning signal line using the DC cancellation method;
Figures 21 and 21 respectively show the active mode shown in Figure 13.
An equivalent circuit diagram showing a liquid crystal display section of a matrix type color liquid crystal display device, FIG. 22 is a sectional view showing a part of the liquid crystal display device shown in FIG. 1, and FIG. 23 is a diagram showing another liquid crystal display according to the present invention. FIGS. 24 and 25 are cross-sectional views showing a part of the device, and are plan views of essential parts showing one pixel of a liquid crystal display section of a conventional liquid crystal display device. SUB...Transparent glass substrate GL...Scanning signal line DL...Video signal line GI...Insulating film GT...Gate electrode AS...I-type semiconductor layer SD...Source electrode or drain electrode psv...
Protective film LS...Light shielding film LC...Liquid crystal TPT...Thin film transistor ITO (COM.)...Transparent pixel electrode g. d...Conductive film C add...Holding capacitance element Cgs...Superposition capacitance C pix...Liquid crystal capacitance BM...Black matrix pattern No. 1 Figure GT-----One piece, one} electrode Codd T--One electrode Otoku Fig. 16 Fig. 18 VLc t] t2 t3 t4 Fig. 22 As Fig. 23

Claims (1)

[Scope of Claims] 1. In an active matrix type liquid crystal display device in which a thin film transistor and a pixel electrode are one component of a pixel, the width of the portion of the gate electrode outside the both sides of the source electrode is equal to the width of the source electrode. A liquid crystal display device characterized in that the width of the overlapping portion is the same as the width of the overlapping portion, and the width of the portion of the source electrode outside both sides of the gate electrode is the same as the width of the overlapping portion with the gate electrode. 2. In an active matrix type liquid crystal display device in which a thin film transistor and a pixel electrode constitute one component of a pixel, the width of the portion of the pixel electrode outside both sides of the electrode of the storage capacitor element is defined as the electrode of the storage capacitor element. The width of the portion of the electrode of the storage capacitor element outside both sides of the pixel electrode is the same as the width of the portion overlapped with the pixel electrode. LCD display device.