JPH02234116A - Production of flat display device - Google Patents

Abstract

PURPOSE:To obtain a flat display device in which misalignment quantity is small by utilizing a real element provided on a substrate as an alignment mark. CONSTITUTION:A scanning signal line GL which is the real element provided on the lower transparent glass substrate SUB 1 is utilized as the alignment mark. The alignment mark AM1 is provided in an effective pattern on the lower transparent glass substrate SUB 1 and the alignment mark AM2 is provided in an effective pattern on a photomask for forming an (i) type semiconductor layer pattern. Therefore, a distance between the alignment mark and the end part of the effective pattern becomes short. Thus, the misalignment quantity of an (i) type semiconductor layer AS on the end part of the effective pattern becomes small and the positional deviation quantity of the (i) type semiconductor AS from a gate electrode GT is made small.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a method for manufacturing a flat display device such as an active matrix color liquid crystal display device or a plasma display device in which a thin film transistor and a pixel electrode are used as constituent elements of a pixel. It is. [Prior Art] In a conventional method for manufacturing an active matrix type liquid crystal display device, as shown in Japanese Patent Laid-Open No. 62-183518, when aligning a substrate and a photomask, the substrate, Alignment marks are provided around the effective pattern of the photomask. [Problem to be Solved by the Invention] However, in this method of manufacturing a liquid crystal display device, the distance between the alignment mark and the end of the effective pattern increases, so the amount of misalignment at the end of the effective pattern becomes large. Therefore, the manufacturing yield is low. This invention was made to solve the above-mentioned problems, and its purpose is to provide a method for manufacturing a flat display device with a small amount of misalignment. [Means for Solving the Problems] In order to achieve the above object, in the present invention, a real element provided on a substrate is used as an alignment mark in a method of manufacturing a flat display device. Moreover, in order to achieve the above object, in this invention,
In a method for manufacturing flat display devices, actual device patterns provided on a photomask are used as alignment marks. Further, to achieve the above object, in the present invention, in a method for manufacturing a flat display device, an alignment mark is provided in an effective pattern of at least one of a substrate and a photomask. [Function] In this method of manufacturing a flat display device,
The actual element provided on the substrate is used as an alignment mark, the actual element pattern provided on the photomask is used as an alignment mark, and the alignment mark is provided within the effective pattern of at least one of the substrate and the photomask. , the distance between the alignment mark and the end of the effective pattern becomes smaller. [Example] One pixel of the liquid crystal display section of an active matrix color liquid crystal display device to which this invention is applied is shown in FIG. Fig. 3 shows a cross section. Further, FIG. 4 (a plan view of a main part) shows a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2 are arranged. As shown in FIGS. 2 to 4, the liquid crystal display device includes a pixel having a thin film transistor TPT and a transparent pixel electrode ITO on the inner surface (liquid crystal side) of a lower transparent glass substrate SUBI. Lower transparent glass substrate SUBI
For example, the thickness is about 1.1 [mm]. Each pixel is connected to two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (
(drain signal line or vertical signal line) DL (in a region surrounded by four signal lines). As shown in FIGS. 2 and 4, the scanning signal line GL is
They extend in the column direction and are arranged in multiple rows. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. The thin film transistor TPT of each pixel has three
It is divided into multiple thin film transistors (divided thin film transistors) TFTI, TPT2, and TFT3. Each of the thin film transistors TPTI to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPT1 to TFT3 mainly has a gate electrode G.
T, insulating film GI. i-type (intrinsic, not doped with conductivity determining impurities) silicon (Si
), a pair of source electrodes SDI
and a drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following explanation as well, for convenience, one side is fixed as a source and the other side is fixed as a drain. As shown in detail in FIG. 5 (a plan view of the main part in a predetermined manufacturing process), the gate electrode GT has a T-shape that protrudes from the scanning signal line OL in the row direction (downward in FIGS. 2 and 5). It is composed of shapes (branched into a T-shape). That is, the gate electrode GT is configured to extend substantially parallel to the video signal line DL. The gate electrode GT is configured to protrude to the formation region of each of the thin film transistors TPT1 to TFT3.
The respective gate electrodes GT of the thin film transistors TPTI to TFT3 are integrally formed (as a common gate electrode) and are continuously formed on the same scanning signal line GL. The gate electrode GT is formed in such a way that a large step is not formed as much as possible in the formation region of the thin film transistor TPT.
It is composed of a single-layer first conductive layer g1. The first conductive film g1 is
For example, a chromium (Cr) film formed by sputtering is used to form a film with a thickness of about 1IQO [man]. This game 1・
As shown in FIGS. 2, 3, and 6, the electrode GT is formed to be thicker than the i-type semiconductor layer AS (as viewed from below) so as to completely cover the i-type semiconductor layer AS. Therefore, when a backlight such as a fluorescent lamp is attached below the lower transparent glass substrate SUBI, the gate electrode GT made of opaque chromium forms a shadow, and the backlight light does not shine on the i-type semiconductor layer AS. The aforementioned conduction phenomenon due to light irradiation, that is, the deterioration of the off-characteristics of the thin film transistor TPT is less likely to occur. The original size of the gate electric bottle GT is
It has the minimum width (including the alignment margin between the gate electrode and the source/drain electrode) to span between the source/drain electrodes SD1 and SDZ, and the channel III
The depth length that determines W is determined by the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance gm6. The size of the electrode is of course larger than the original size mentioned above. Considering only the function of the gate and light shielding of the gate electrode GT, the gate electrode GT and its wiring GL may be integrally formed in a single layer. In this case, aluminum containing silicon is used as an opaque conductive material. Al), pure aluminum, aluminum containing palladium (Pd), silicon, aluminum containing titanium (T i ), silicon, aluminum containing copper (Cu), etc. can be selected. The scanning signal line OL is constituted by a composite film consisting of a first conductive film g]- and a second conductive film g2 provided on top of the first conductive film g. The first conductive film g1 of the scanning signal MOL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally with the first conductive film g1. The second conductive film g2 is, for example, an aluminum film formed by sputtering,
It is formed with a film thickness of about 900 to 4000 [people]. Second guide 1! The film g2 is configured to reduce the resistance value of the scanning signal MGL and increase the signal transmission speed (writing characteristics of pixel information). Further, in the scanning signal line GL, the width of the second conductive film g2 is configured to be smaller than the width of the second IR electrical film g1. That is, the scanning signal IGL is configured so that the step shape of the side wall thereof can be made gentle, so that the surface of the upper layer insulating film GI can be flattened. The insulating film Gl is used as a gate insulating film for each of the thin film transistors TPTI to TFT3. Insulating film GI
is formed in the upper layer of the gate electrode GT and the scanning signal line OL. The amorphous film G process is formed using, for example, a silicon nitride film formed by plasma CVD, and has a thickness of about 3500 [layers]. As mentioned above, the surface of the insulating film GI is
The regions where the thin film transistors TPT1 to TFT3 are formed and the scanning signal line OL are formed are flattened. i-type semiconductor, II! As shown in detail in FIG. 6 (a plan view of a main part in a predetermined manufacturing process), AS is used as a channel forming region for each of thin film transistors TPT1 to TFT3 divided into a plurality of parts. The i-type semiconductor layer AS of each of the plurality of divided thin film transistors TPTI to TFT3 is integrally formed within the pixel. That is, each of the plurality of divided thin film transistors TPT1 to TFT3 of a pixel has a (common)
It is composed of an island region of a j, type semiconductor layer AS. The i-type semiconductor MAs is formed of a non-quality silicon film or a polycrystalline silicon film, and is formed to have a thickness of about 2000 [layers]. This i-type semiconductor WJAs can be produced by changing the composition of the supplied gas.
Subsequently to the formation of the insulating film GI made of N4, the insulating film GI is formed using the same plasma CVD apparatus without being exposed to the outside from the apparatus. Further, a P-doped N+ type semiconductor layer do (FIG. 3) for ohmic contact is similarly formed continuously to a thickness of about 300 [layers]. Thereafter, the lower transparent glass substrate SUBI is taken out from the CVD apparatus, and an N+ type semiconductor layer d is formed using photo processing technology.
The O and i-type semiconductor layers AS are shown in FIGS. 2, 3, and 6.
As shown in the figure, it is patterned into independent islands. In this way, by integrally configuring the respective i-type semiconductor layers As of the thin film transistors TPTI to TFT3 divided into a plurality of pixels, the thin film transistors TPT1 to TFT3 are integrated.
The drain electrode SD2 common to each of the TFTs 3 is connected to the i-type semiconductor layer AS (actually, the thickness of the first conductive film g1, N
Drain electrode SD
Since the drain electrode SD2 only crosses over once from the 2 side toward the i-type semiconductor layer AS side, the probability that the drain electrode SD2 is disconnected becomes low, and the probability that a point defect occurs can be reduced. That is, in this liquid crystal display device, the drain electrode SD2 is
Point defects that occur within a pixel when climbing over a step in the type semiconductor layer AS can be reduced to one-third. Although the layout of this liquid crystal display device is different, when the video signal line DL directly crosses over the i-type semiconductor layer AS and the video signal line DL in this overpassed portion is configured as the drain electrode SD2, the video signal line DL (drain Electrode SD
2) It is possible to reduce the probability of line defects occurring due to disconnection when the wire crosses the i-type semiconductor layer As. In other words, the thin film transistor TPTI divided into a plurality of pixels
~By integrally configuring each i-type semiconductor layer As of TFT3, the video signal line DL (drain electrode SD2
) crosses the i-type semiconductor layer AS only once (actually twice, at the beginning and end of the ride). As shown in detail in FIGS. 2 and 6, the i-type semiconductor layer AS is provided so as to extend between the scanning signal line GL and the video signal line DL (crossover section). ing. This extended i-type semiconductor layer AS is configured to reduce short circuits between the scanning signal line GL and the video signal line DL at the intersection. Thin film transistors TPT1-T divided into a plurality of pixels
Each source electrode SDI and drain electrode S of FT3
D2 are provided separately on the i-type semiconductor layer AS, as shown in detail in FIGS. 2, 3, and 7 (plan views of main parts in predetermined manufacturing steps). Each of the source electrode SDI and drain electrode SD2 is configured such that when the bias polarity of the circuit changes, the source and drain are interchanged in operation. In other words, the thin film transistor TPT is bidirectional like a FET. Each of the source electrode SDI and drain electrode SD2 is
A first conductive film d1, a second conductive film d2, and a third conductive film d3 are sequentially stacked one on top of the other from the lower layer side in contact with the N1 type semiconductor layer dO. First conductive film d of source electrode SDI
1. The second conductive film d2 and the third conductive film d3 are formed in the same manufacturing process as the drain electrode SD2. The first conductive film d1 is a chromium film formed by sputtering,
The chromium film is formed with a film thickness of 500 to 1000 [people] (in this liquid crystal display device, a film thickness of about 600 [people]).
As the thickness of the film increases, the stress increases, so 2
The film should be formed within a range that does not exceed a film thickness of about 0.000 [in]. The chromium film has good contact with the N+ type semiconductor layer do. The chromium film constitutes a so-called barrier layer that prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer dO. In addition to the chromium film, the first conductive film d1 includes a high melting point metal (Mo.Ti, Ta.W) film,
Refractory metal silicide (MoSi., TiSi2, T
aS i @. It may be formed using a W S x z) film. After patterning the first conductive film d1 by photoprocessing, the N+ type semiconductor layer do is removed using the same photoprocessing mask or using the first conductive film d1 as a mask. In other words, the portion of the N◆-type semiconductor layer do remaining on the i-type semiconductor layer AS except for the first conductive film d1 is removed by the self-alignment line. At this time, since the N+ type semiconductor layer do is etched so that its entire thickness is removed, the i type semiconductor layer AS is also slightly etched at its surface, but the extent can be controlled by the etching time. Thereafter, the second conductive film d2 is formed by aluminum sputtering to a thickness of 3000 to 5500 mm (in this liquid crystal display device, the thickness is approximately 3500 mm). The aluminum film has less stress than the chromium film and can be formed to a thick film thickness, making it suitable for the source electrode SDI.
, is configured to reduce the resistance values of the drain electrode SD2 and the video signal line DL. The second conductive film d2 is configured to increase the operating speed of the thin film 1 to the transistor TFT and the signal transmission speed of the video signal line DL. In other words, the second conductor @Gd2 can improve the writing characteristics of the pixel. Second conductive film d2
Alternatively, in addition to the aluminum film, an aluminum film containing silicon, palladium, titanium, copper, etc. as an additive may be used. After patterning the second conductive film d2 using photo processing technology,
The third conductive film d3 is a transparent conductive film vA (
1TO: Nesa vA) is used, and is formed with a film thickness of 300 to 2400 [people] (in this liquid crystal display device, the film thickness is about 1200 [people]). This third conductive film d3 constitutes the source electrode SDI, drain electrode SD2, and video signal line DL, and also constitutes the transparent pixel electrode ITO. Each of the first conductive film d1 of the source electrode SDI and the first conductive film d1 of the drain electrode SD2 has a larger size on the channel formation region side than the second conductive film WAd2 and the third conductive film d3 in the upper layer. . In other words,
The first conductive film d1 can be fixed to the second conductive film d2 and the third conductive film d even if mask misalignment occurs in the manufacturing process between the first conductive film d1, the second conductive film d2, and the third conductive film d3.
3 (the channel forming region side of each of the first to third conductive films d1 to d3 may be on-the-line). Source electrode SD
The first conductive film d1 of I and the first conductive film d1 of drain electrode SD2 are each configured to define the gate length L of the thin film transistor TPT. In this way, in the thin film transistors TFTI to TFT3 divided into a plurality of pixels, the source electrode SDI.
, each of the drain electrodes SD2. The channel forming region side of the conductive film d1 is connected to the second conductive film d2 and the third conductive film 1.
By configuring it with a larger size than 1id3,
The gate length L of the thin film transistor TPT can be defined by the dimension between the first conductive films d1 of the source electrode SDI and the drain electrode SD2. First conductive film dllJ
Since the separation dimension (gate length) of j can be defined by processing accuracy (patterning accuracy), the gate lengths L of each of the thin film transistors TPTI to TFT3 can be made uniform. As mentioned above, the source electrode SDI is the transparent pixel electrode 1'
Connected to TO. The source electrode SDI has a step shape of the i-type semiconductor RAS (a step corresponding to the sum of the film thickness of the first conductive film g1, the film thickness of the N" type semiconductor NdO, and the film thickness of the i-type semiconductor IAs). Specifically, the source electrode SDI includes a first conductive film d1 formed along the step shape of the J-type semiconductor layer As, and a layer formed on the top of the first conductive film d1 compared to the first conductive film d1. Transparent pixel electrode TO
a second conductive film d formed with a smaller size on the side connected to
2 and the first conductive film d1 exposed from the second conductive film d2.
and a third conductive film d3 connected to the third conductive film d3. The first conductive film di of the source electrode SDI is N+. type semiconductor layer d
It has good adhesion with O and is mainly configured as a barrier layer against diffused substances from the second conductive t film d2. The second conductive film d2 of the source electrode SDI is the first conductive film 111c.
l. Since the chromium film of No. 1 cannot be formed thickly due to increased stress and cannot overcome the stepped shape of the i-type semiconductor layer AS, the chromium film is configured to overcome the step shape of the i-type semiconductor layer AS. In other words, the second conductive 1t film d2 improves the stepping force barrier by forming it thickly. second conductivity md2
can be formed thickly, so the resistance value of the source electrode SDI (
The same applies to the drain electrode SD2 and video signal IDL)
The third conductive film d3, which greatly contributes to the reduction of
Guide gl. Since the step shape caused by the i-type semiconductor layer AS of the film d2 cannot be overcome, the second conductive film d2 is configured to be connected to the exposed first conductive film d1 by reducing its size. The first conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connection between them, so that they can be connected reliably. In this way, the source electrode SD of the thin film transistor TPT
1, a first conductive film d1 as a barrier formed at least along the i-type semiconductor layer As, and this first conductive film d
The second conductive film 11! is formed on top of the first conductive film d1, has a smaller specific resistance value than the first conductive film d1, and has a smaller size than the first conductive film d1! d2, and by connecting the third conductive film d3, which is a transparent pixel electrode ITO, to the first conductive film d1 exposed from the second conductive film d2, the thin film transistor TPT and the transparent pixel electrode ITO are reliably connected. Therefore, point defects caused by wire breaks can be reduced. Moreover, the source electrode SDI has a first conductivity vAd
Due to the barrier effect caused by i, the second conductive film d2 has a small resistance value.
(aluminum film), the resistance value can be reduced. The drain electrode SD2 receives a video signal, i! It is integrated with the DL and is formed in the same manufacturing process. The drain electrode SD2 has an L-shape that protrudes in the column direction intersecting the video signal line DL. In other words, the respective drain electrodes SD2 of the thin film transistors TPTI to TFT3 divided into a plurality of pixels are connected to the same video signal line DL.
It is connected to the. The transparent pixel electrode ITO is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode IT○ is divided into three transparent pixel electrodes (divided transparent pixel electrodes) ITOI, ITO2, and IT○3 corresponding to each of the plurality of divided thin film transistors TPTI to TFT3 of the pixel. The transparent pixel electrode iTO1 is
It is connected to the source electrode SDI of the thin film transistor TFTI. The transparent pixel electrode ITO2 is connected to the source electrode SDI of the thin film transistor TPT2. The transparent pixel electrode ITO3 is connected to the source electrode SDI of the thin film transistor TFT3. Transparent pixel electrode ITOI~
Each of ITO3 is a thin film transistor TPTI~T
Like each of FT3, each of the transparent pixel electrodes ITOI to ITO3, which are configured with substantially the same size, is configured with the i-type semiconductor layer As of each of the thin film transistors TPTI to TFT3 (not divided). (Thin film transistors TPT are concentrated in one place), so the structure is L-shaped. In this way, the thin film transistor TPT of the pixel arranged in the intersection area of two adjacent scanning signal lines GL and two adjacent video signal lines DL is
By dividing the pixel into PT1 to TFT3 and connecting each of the plurality of divided transparent pixel electrodes ITOI to ITO3 to each of the plurality of divided thin film transistors TPTI to TFT3, a divided part of the pixel (for example, thin film transistor TFTI) is formed. becomes only a point defect,
Since the pixel as a whole is no longer a point defect (the thin film transistors TFT2 and TFT3 are not point defects), it is possible to reduce point defects in the pixel as a whole. Further, since some of the point defects in which the pixel is divided are smaller than the entire area of the pixel (in the case of this liquid crystal display device, the area is one-third of the pixel), the point defects can be made difficult to see. Can be done. Furthermore, the divided transparent pixel electrodes IT01 to I of the pixel are
By configuring each TO3 to have substantially the same size, the area of point defects within a pixel can be made uniform. Furthermore, the divided transparent pixel electrodes IT01 to I of the pixel are
By configuring each of the TO3 to have substantially the same size, each liquid crystal capacitor (Cpix) constituted by each of the transparent pixel electrodes ITOI to ITO3 and the common transparent pixel electrode IT○ and the transparent pixel electrodes ITOI to IT
Transparent pixel electrodes ITOI-I added to each of O3
The superposition capacitance (C gs) caused by superposition of TO3 and gate electrode GT can be made uniform. In other words, each of the transparent pixel electrodes ITOI to ITO3 can have a uniform liquid crystal capacitance and superimposed capacitance, so that the DC component that is to be applied to the liquid crystal molecules of the liquid crystal LC due to this superposed capacitance can be made uniform. If this method of canceling the DC component is adopted, the variation in the DC component applied to the liquid crystal of each pixel can be reduced. An i-preserving film PSVi is provided over the thin film transistor TPT and the transparent pixel electrode ITo. Protective film PSVI
is formed mainly to protect the thin film transistor TPT from moisture, etc., and a material with high transparency and good moisture resistance is used. The protective film PSVI is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a film thickness of sooo to 11,000 [people].
In this liquid crystal display device, the film thickness is approximately the same as that of a goooc human eye. Protective film PSV on thin film transistor rFT
A shielding film L is provided above I to prevent external light from entering the i-type semiconductor layer AS used as a channel formation region.
S is provided. As shown in FIG. 2, the shielding film LS
is configured within the area surrounded by the dotted line. Shielding film L
S is made of a material that has a high shielding property against light, such as an aluminum film or a chromium film.
Form to a film thickness of about [ON]. Therefore, the common semiconductor layer As of the thin film transistors TPT1 to TFT3 is sandwiched between the upper and lower light shielding films LS and the thick gate electrode GT, and is not exposed to external natural light or bank light. The light shielding film LS and the gate electrode GT are formed to be thicker than the semiconductor layer AS and have a similar shape, and the sizes of the two are considered to be approximately the same (
In the figure, the gate electrode GT is drawn smaller than the light shielding film LS so that the boundary line can be seen). Note that the backlight is attached to the upper transparent glass substrate SUBz side. The lower transparent glass substrate SUBI can also be used as the It detection side (externally exposed side), in which case the light shielding WALS
acts as a light shield for backlight light, and gate electrode GT acts as a light shield for natural light. The thin film transistor TPT is configured such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large. That is, the thin film transistor TPT is configured to control the voltage applied to the transparent pixel electrode IT○. In the liquid crystal LC, a lower alignment film ORII and an upper alignment film OR. I 2 is specified and enclosed. The lower alignment film ORII is formed on the protective film PSVI on the lower transparent glass substrate SUBI side. On the inner surface (liquid crystal side) of the upper transparent glass substrate SUB2, a color filter FIL, a color filter FIL, a common transparent pixel electrode (CO
M) ITO and the upper alignment film ORI2 are sequentially stacked. The common transparent pixel electrode ITO is connected to the lower transparent glass substrate S.
It faces the transparent pixel electrode ITO provided for each pixel on the UBI side and is configured integrally with another adjacent common transparent pixel ft pole TTo. A common voltage Vcom is applied to this common transparent pixel electrode IT○. The common voltage Vcom is an intermediate potential between the low-level drive voltage Vdmin and the high-level drive voltage Vdl1ax applied to the video signal line DL. The color filter FIL is constructed by coloring a dyed base material made of a resin material such as acrylic resin with a dye.
The color filter FIL is arranged for each pixel at a position facing the pixel, and is colored differently. That is, like a pixel, the color filter FIL is configured within the intersection area of two adjacent scanning signals #IGL and two adjacent video signals 11DL. Each pixel is divided into a plurality of parts within each predetermined color filter of the color filter FIL. The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming area is removed using photolithography technology. After this, the dyed base material is dyed with red dye, fixed treatment is applied, and red filter R
form. Next, a green filter G and a blue filter B are sequentially formed by performing similar steps. In this way, by forming each color filter of the color filter FIL in the intersection area facing each pixel, each of the scanning signal line GL and the video signal line DL exists between each color filter of the color filter FIL. Corresponding to their existence, it is possible to secure an alignment margin between each pixel and each color filter of the color filter FIL (enlarge the alignment margin). Furthermore, when forming each color filter of the color filter FIL, it is possible to secure alignment margin dimensions between different color filters. That is, in this liquid crystal display device, a pixel is formed within the intersection area of two adjacent scanning signals i11GL and two adjacent video signal lines DL, and this pixel is divided into a plurality of parts, each of which is opposite to this pixel. By forming each color filter of the color filter FIL at the position, the above-mentioned point defects can be reduced, and alignment margin dimensions between each pixel and each color filter can be secured. The protective film PSV2 is provided to prevent the dyes used to dye the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of a transparent resin material such as acrylic resin or epoxy resin. This liquid crystal display device has a lower transparent glass substrate SUBl side,
Each layer on the upper transparent glass substrate SUB2 side is formed separately, and then the lower transparent glass substrate SUBI and the upper transparent glass substrate SUB2 are stacked on top of each other, and the liquid crystal LC is sealed between them, thereby assembling. As shown in FIG. 4, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal line GL extends, and are arranged in pixel columns X,, X,, X,, X4, -. It consists of each of the following. Each pixel column X,,X2,X,,X
Each pixel of 4,... is a thin film transistor TF.
TI~TFT3 and transparent pixel electrodes ITo1~ITO3
The layout positions are the same. In other words, each pixel in pixel rows XE, X3,...
TOI to ITO3 are arranged on the right side. Each pixel in the pixel columns x2, X4, . . . next to the pixel columns X, X, . . . . each pixel is arranged line-symmetrically with respect to the video signal line DL. That is, in each pixel of the pixel columns X2, X4, . . . , the thin film transistors TPTI to TFT3 are arranged on the right side, and the transparent pixel electrodes ITOI to ITO3 are arranged on the left side. Then, the pixel rows X,,x,,...
Each pixel of .
They are arranged (staggered). In other words, if each pixel interval of pixel row X is 1.0 (1.0 pitch), then the next pixel row They are shifted by 0.5 pixel intervals (0.5 pitch). The video signal line DL extending in the row direction between each pixel is a half pixel interval (0.5 pitch) between each pixel column X.
It is configured to extend in the column direction. In this way, in the liquid crystal display section, the thin film transistor T
A plurality of pixels with the same PT and transparent pixel electrode ITO are arranged in the column direction to form a pixel column X, and the next pixel column X of the pixel column By configuring pixels arranged symmetrically with respect to line DL, and moving the next pixel column by half a pixel interval relative to the previous pixel column, it is possible to As shown in the main part plan view in the combined state), a pixel on which a predetermined color filter is formed in the previous pixel row The pixels in column X in which the same color filters are formed (for example, the pixels in pixel column x4 in which red filters R are formed) can be separated by 1.5 pixel intervals (1.5 pitch). In other words, the pixels in the previous pixel column
The color filter FIL can have an RGB triangular arrangement structure. RG of color filter FIL
Triangle arrangement i of B! ! The structure can improve the color mixing of each color, thereby improving the resolution of a color image. Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. The circuit configuration of this liquid crystal display section is shown in FIG. 9 (equivalent circuit diagram of the liquid crystal display section). XiG, Xi+IG, . . . shown in FIG. 9 are video signal lines DL connected to the pixels in which the green filter G is formed. XiB, Xi+IB,... is blue filter B
A video signal connected to the pixel where is formed? It is MDL.
X i + I R , X i + 2 R ,・
... is a video signal line DL connected to the pixel in which the red filter R is formed. These video signal lines DL are selected by a video signal drive circuit. Yi is a scanning signal l1iA for selecting the pixel column X shown in FIGS. 4 and 8.
G L ttb le. Similarly, Yi+1. ,Yi+2,
. . . are scanning signal lines OL that select each of the pixel columns X, , X, . These scanning signal lines GL are connected to a vertical scanning circuit. The center part of FIG. 3 shows the cross section of one pixel part, while the left side shows the cross section of the left edge part of the lower transparent glass substrate SUBI and the upper transparent glass substrate SUB2 where external lead wiring exists. . The right side shows a cross section of the right green part of the transparent glass substrates SUBI and SUB2 where no external lead wiring is present. The sealing materials SL shown on the left and right sides of FIG. 3 are as follows:
It is configured to seal the liquid crystal LC, and is formed along the entire edges of the transparent glass substrates SUBI and SUB2 except for the liquid crystal sealing opening (not shown). The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode ITO on the side of the upper transparent glass substrate SUBZ is coated with silver paste material S at at least one location.
The IL is connected to an external lead wiring formed on the side of the lower transparent glass substrate SUBI. This external lead wiring includes the gate electrode GT, source electrode SDI.
It is formed in the same manufacturing process as each of the drain electrodes SD2. The alignment films ORII and ORI2, transparent pixel electrode IT
O, common transparent pixel electrode ITO, protective film PSVI and P
Each layer of SV2 and insulating film GI is formed inside the sealing material SL. The polarizing plate POL is formed on the outer surface of each of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2. FIG. 10 is a cross-sectional view of the main part of the pixel and the periphery of the seal part of the liquid crystal display part of another active matrix color liquid crystal display device to which the present invention is applied, and FIG.
0 is a plan view showing one pixel of the liquid crystal display section of the liquid crystal display device shown in FIG. A plan view of a main part of a liquid crystal display section in which a plurality of pixels are arranged, FIGS. 14 to 16 are plan views of main parts in a predetermined manufacturing process of the pixel shown in FIG. 11, and FIG. This is a plan view of the main parts in a state in which color filters are superimposed. In this liquid crystal display device, it is possible to improve the aperture ratio of each pixel in the liquid crystal display section, reduce the direct current component applied to the liquid crystal, reduce point defects in the liquid crystal display section, and reduce black unevenness. can. As shown in FIG. 171, this liquid crystal display device is constructed by dividing the i-type semiconductor layer As in each pixel of the liquid crystal display section into thin film transistors TFT1 to TFT3. In other words, the thin film transistor TPTI divided into a plurality of pixels
~Each of TFT3 is an independent l-type semiconductor/IAS
It consists of an island area. Further, each of the transparent pixel electrodes ITOI to ITO3 connected to each of the thin film transistors TPTI to TFT3 is connected to the scanning signal line OL of the next stage in the row direction on the side opposite to the side connected to the thin film transistors TPT1 to TFT3. They are superimposed. This superposition constitutes a storage capacitance element (electrostatic capacitance element) Cadd in which each of the transparent pixel electrodes ITOI to ITO3 is used as one electrode and the next stage scanning signal lIAGL is used as the other electrode. The dielectric film of this storage capacitor element C add is a thin film transistor T
The gate electrode GT is made of the same layer as the absolute film (3I) used as the gate insulating film of the PT. The gate electrode GT is thicker than the i-type semiconductor layer AS, as in the liquid crystal display device shown in FIG. However, in this liquid crystal display device, thin film transistors TPTI to TFT3
is formed for each independent i-type semiconductor layer AS, so a thick pattern is formed for each thin film transistor TPT. In addition, the scanning signal line OL, video signal line DL, thin film transistor TFT of the upper transparent glass substrate SUB2
Since the black matrix pattern BM is provided in the portion corresponding to the pixel, the outline of the pixel becomes clear, the contrast is improved, and external natural light can be prevented from hitting the thin film transistor TPT. The equivalent circuit of the pixel shown in Fig. 11 is shown in Fig. 18 (equivalent circuit diagram). In FIG. 18, as before, C
gs is a superimposed capacitance formed by the gate electrode GT and source electrode SDI of the thin film transistor TPT. The dielectric film of the superposed capacitance Cgs is an insulating film GI. Cp
ix is a liquid crystal capacitance formed between the transparent pixel electrode ITO (PIX) and the common transparent pixel electrode ITO (COM). The dielectric film of the liquid crystal capacitor C pix is the liquid crystal LC. protective film p
sv1, alignment film ORII, and ○RI2. Vlc
is the midpoint potential. The storage capacitance element C add is a thin film transistor TP
When T switches, the midpoint potential (pixel electrode potential)
It works to reduce the influence of gate potential change ΔVg on v1c. This situation can be expressed as the following formula. ΔV lc = ((Cgs/ (Cgs+Cadd+
Cpix) ) XΔVg Here, ΔVlc represents the change in midpoint potential due to ΔVg. This change Δvlc causes a DC component applied to the liquid crystal, but the storage capacitance element C
The larger the storage capacity of add, the smaller its value can be. In addition, the storage capacitance element C add has the effect of lengthening the discharge time, and the thin film transistor TP
To store video information for a long time after T is turned off. Reducing the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching between liquid crystal display screens. As mentioned above, since the gate electrode GT is made large enough to completely cover the semiconductor layer AS, the overlapping area with the source/drain electrodes SD1 and SD2 increases, and therefore the parasitic capacitance Cgs increases, and the midpoint potential Vlc decreases. This has the opposite effect of becoming more susceptible to the influence of the gate (scanning) signal Vg. However, by providing the storage capacitor element Cadd, this disadvantage can also be eliminated. Further, in a liquid crystal display device having pixels in an intersection area of two scanning signal lines GL and two video signal lines DL, one scanning signal line OL of the two scanning signal lines GL
The thin film transistor TPT of the pixel selected by is divided into a plurality of parts, and the divided thin film transistors TPTI to TF
A transparent pixel electrode ITO divided into a plurality of parts (ITOI to ITO3) is connected to each of T3, and this pixel electrode ITO is used as one electrode for each of the divided transparent pixel electrodes IT01 to ITO3, and the two scanning electrodes are connected to each other. signal g
By using the other scanning signal line GL of the GL as a capacitor electrode line to configure the storage capacitor element Cadd, which uses the other electrode as the other electrode, only a part of the divided pixel becomes a point defect, as described above. Therefore, since the pixel as a whole is not a point defect, it is possible to reduce the point defect of the pixel, and it is also possible to reduce the DC component applied to the liquid crystal LC by the storage capacitor element C add, thereby extending the life of the liquid crystal LC. can be improved. In particular, by dividing the pixel, the gate electrode GT and the source electrode SD ]. Alternatively, point defects caused by a short circuit with the drain electrode SD2 can be reduced, and point defects caused by a short circuit between each of the transparent pixel electrodes TTOI to T○3 and the other electrode (capacitance electrode 4fI) of the storage capacitor element Cadd can be reduced. Point defects can be reduced. In this liquid crystal display device, the number of point defects on the latter side is one third. As a result, some of the point defects into which the pixel is divided are smaller than the entire area of the pixel, making it difficult to see the point defects. The storage capacitance of the storage capacitance element C add is 4 to 8 times (4
・Cpix<Cadd< 8 ・Cpix) . 8 to 32 times the superposition capacitance Cgs (8 ・C gs<
Set to a value of approximately C add < 32・Cgs). Further, the scanning signal aGL is applied to a first conductive film (chromium film) g.
It is composed of a composite film in which a second conductive film (aluminum film) g2 is superimposed on a second conductive film (aluminum film) g2. By using a single-layer film made of the first conductive film g1, it is possible to reduce the resistance value of the scanning signal line GL and improve the IF-included characteristics, as well as to
Since one electrode (transparent pixel electrode ITo) of the storage capacitor element C add can be bonded onto the insulating film GI, the storage capacitor element C add It is possible to reduce disconnection of one of the electrodes. Moreover, by configuring the other electrode of the storage capacitor element C add with the single-layer first conductive film g1 and not comprising the second conductive film g2 which is an aluminum film, the retention capacitor element C a +j due to hillocks of the aluminum film is formed. It is possible to prevent a short circuit between the other electrode of d and one electrode. A portion between each of the transparent pixel electrodes ITOI and IT○3 and the capacitor electrode line, which are overlapped to form the storage capacitor element C add, is provided with the source 1! Similar to the polar SDI, an island region made up of a first conductive film d1 and a second conductive film d2 is provided to prevent the transparent pixel electrode IT◯ from being disconnected when crossing the step shape of the capacitive electrode line. This island region is the area of the transparent pixel electrode ITO (
The structure should be made as bulky as possible so as not to reduce the aperture ratio. In this way, the first conductive film d1 and the first conductive film d1 formed thereon are disposed between one electrode of the storage capacitance element C add and the MA edge film G1 used as its dielectric film.
A base layer is formed with a second conductive film d2 having a smaller specific resistance value and smaller size than that of the base layer, and the one electrode (third conductive film d3) is formed from the second conductive film d2 of the base layer. By connecting to the exposed first conductive film d1, storage capacitor element Ca. Since one electrode of the storage capacitor element C add can be bonded, disconnection of one electrode of the storage capacitor element C add can be reduced. A storage capacitor element C ad is provided on the transparent pixel electrode ITO of the pixel.
The liquid crystal display section of the liquid crystal display device provided with d is constructed as shown in FIG. 20 (equivalent circuit diagram showing the liquid crystal display section). The liquid crystal display section is composed of repeating unit basic patterns including pixels, scanning signal lines GL, and video signal lines DL. As shown in FIG. 20, the final stage scanning signal line OL (or first stage scanning signal line OL) used as a capacitor electrode line is a common transparent pixel electrode (Vcom) I To
Connect to. Common transparent pixel f! As shown in FIG. 3, the pole ITO is connected to the external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Moreover, some of the conductive rows (gl and g2) of this external lead wiring are constructed in the same manufacturing process as the scanning signal line GL. As a result, the final stage scanning signal line OL (capacitance electrode line)
can be easily connected to the common transparent pixel electrode ITO. In this way, by connecting the final stage of the capacitive electrode line to the common transparent pixel electrode (Vco@) I To of the pixel, the final stage of the capacitive electrode line is integrated with a part of the conductive layer of the external wiring. Moreover, since the common transparent pixel electrode 11'0 is connected to the external lead wiring, the final stage capacitor electrode line can be connected to the common transparent pixel electrode ITO with a simple structure. In addition, the liquid crystal display device is based on the DC cancellation method described in Japanese Patent Application No. 62-95125 previously filed by the applicant of the present invention, as shown in FIG. 19 (time chart). By controlling the drive voltage of the scanning signal line DL, it is possible to further reduce the DC component applied to the liquid crystal LC. In FIG. 19, Vi is the drive voltage of an arbitrary scanning signal line OL, and Vi+1 is the drive voltage of the scanning signal line GL at the next stage. Vee is a low-level dynamic voltage Vdmin applied to the scanning signal line GL.
, Vd d is the high-level driving voltage Vdmax applied to the scanning signal @ (3 L d. At each time t=j,
The voltage change ΔVyu~Δv4 of the midpoint potential Vlc (see FIG. 18) at ~t4 is the total capacitance of the pixel (Cgs+
If Cpix+Cadd) is C, then the following equation is obtained. ΔVz= = (Cgs/C)・V2 Δvs=+(Cgs/C)・(v1+v2)− (C
add/C)・V2 ΔV3=−(Cgs/C)・v1+(Cadd/C){V1+V2)Δv,=1(C
add/C)·v1 Here, if the fluctuating voltage applied to the scanning signal line GL is sufficient (see Note below), the DC voltage applied to the liquid crystal LC is expressed by the following equation. ΔV, +ΔV4= (Cadd−V 2 − Cgs−
V 1 )/C Therefore, Cadd-v2=Cgs-
If v1, the DC voltage applied to the liquid crystal LC becomes 0.

〔Effect of the invention〕

As explained above, in the method for manufacturing a flat display device according to the present invention, a real element provided on a substrate is used as an alignment mark, and a real element pattern provided on a photomask is used as an alignment mark. Furthermore, since the alignment mark is provided within the effective pattern of at least one of the substrate and the photomask, the distance between the alignment mark and the end of the effective pattern becomes smaller, so the amount of alignment deviation at the end of the effective pattern becomes smaller. High manufacturing yield. As described above, the effects of this invention are remarkable.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a method for manufacturing an active matrix color liquid crystal display device according to the present invention, and FIG. 2 is a pixel of a liquid crystal display section of an active matrix color liquid crystal display device to which the present invention is applied. Figure 3 is a cross-sectional view of the area taken along the cutting line 1 in Figure 2 and the area around the seal, Figure 4 is a liquid crystal display section with a plurality of pixels arranged as shown in Figure 2. FIGS. 5 to 7 are plan views of main parts in a predetermined manufacturing process of the pixel shown in FIG.
FIG. 8 is a plan view of main parts in a state where the pixels and color filters shown in FIG. 4 are superimposed, FIG. 9 is an equivalent circuit diagram showing the liquid crystal display section of the above active matrix type color liquid crystal display device, FIG. 10 is a sectional view of the main part of the pixel and the periphery of the seal part of the liquid crystal display part of another active matrix type color liquid crystal display device to which the present invention is applied, and FIG. 11 is a sectional view of the liquid crystal display shown in FIG. 10. A plan view showing one pixel of the liquid crystal display section of the display device, Figure 12 is A of Figure 11.
13 is a plan view of the main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 11 are arranged, and FIGS. 17 is a plan view of the main part in a predetermined manufacturing process, FIG. 17 is a plan view of the main part in a state where the pixel shown in FIG. 13 and the color filter are superimposed, and FIG. 18 is an equivalent circuit of the pixel shown in FIG. 11. Figure 19 is a time chart showing the inductive voltage of the scanning signal line using the DC cancellation method, and Figures 20 and 21 are the liquid crystal display section of the active matrix color liquid crystal display device shown in Figure 13. Show. Equivalent circuit diagram, 2nd
2 and 23 are explanatory diagrams of other methods of manufacturing a liquid crystal display device according to the present invention, respectively. StJB...Transparent glass substrate GL...Scanning signal line DL...Video signal line GI...Insulating film GT...Gate electrode AS...I-type semiconductor layer SD...Source electrode or drain electrode psv...
Protective film LS...Light shielding film LC...Liquid crystal TPT...Thin film transistor ITO (COM)...Transparent pixel electrode g. d... Conductive film C add... Holding capacitance element Cgs... Superposition capacitance Cpix... Liquid crystal capacitance BM... Black matrix pattern AM... Alignment mark ASP... I-type semiconductor Layer pattern DLP...Video signal line pattern SDIP...Source electrode pattern A+ A2 C C2 B GL-----Scanning A blind shoulder κ AM----
-Alignment mark-7ASP--・I-type cow guide plate 2nd grade 13th figure 16th figure 112-18th figure C

Claims (1)

[Claims] 1. A method for manufacturing a flat display device, characterized in that a real element provided on a substrate is used as an alignment mark. 2. A method for manufacturing a flat display device, characterized in that a pattern for a real element provided on a photomask is used as an alignment mark. 3. A method for manufacturing a flat display device, which comprises providing an alignment mark within an effective pattern of at least one of a substrate and a photomask.