JP5217469B2 - Display device - Google Patents

Description

  In the present invention, pixel circuits (also referred to as pixels) each including a current-driven electro-optical element (also referred to as a display element or a light-emitting element) whose luminance changes depending on the magnitude of a driving signal are arranged in a matrix. The present invention relates to an active matrix display device that includes a display panel portion having a pixel array portion as a main portion, has an active element for each pixel circuit, and performs display driving in units of pixels by the active element.

  In recent years, in the field of display devices, panel-type display devices have become mainstream in place of conventional CRT (Cathode Ray Tube) display devices because they have features such as thinness, light weight, and high definition.

  Among panel-type display devices, there is a display device that uses an electro-optical element whose luminance changes depending on an applied voltage or a flowing current as a display element of a pixel. For example, a liquid crystal display element is a typical example of a voltage-driven electro-optic element whose luminance changes depending on an applied voltage, and an organic electroluminescence ( Organic electro luminescence, organic EL, organic light emitting diode, OLED (hereinafter referred to as organic EL) element is a typical example. The organic EL display device using the latter organic EL element is a so-called self-luminous display device using an electro-optic element which is a self-luminous element as a pixel display element.

  In a panel type display device, a pixel array unit in which elements constituting a pixel circuit such as a TFT or an electro-optical element are arranged in a matrix, a scanning line arranged around the pixel array unit and driving each pixel, and A control unit mainly including a connected scanning unit (horizontal drive unit or vertical drive unit), and a drive signal generation unit and a video signal processing unit that generate various signals for operating the control unit. In general, the entire apparatus is constructed. A scanning circuit in which a scanning line, a power supply line, and the like are extended between the pixel array unit and a scanning circuit other than the pixel array unit, and a power supply voltage and a signal are input to a thin film transistor and an electro-optical element that form the pixel circuit. The form which supplies a signal from is taken.

  At this time, various methods have been considered for arranging circuits other than the pixel array section. As an example, circuits other than the pixel array section are arranged outside the panel, and the panel edge section is arranged. A scanning line (for example, a writing scanning line, a power supply line, and a video signal line) is extended to the terminal area of the pixel, and a power supply voltage and a signal are supplied from a scanning circuit or a power supply circuit to a thin film transistor or an electro-optical element constituting the pixel circuit. May be adopted (see Patent Document 1).

Japanese Patent Laid-Open No. 2007-041561

  Here, the current-driven electro-optical element has a laminated structure sandwiched between a light emitting layer and two electrodes (referred to as a lower electrode and an upper electrode). For example, an organic EL element has an organic thin film (organic layer) formed by laminating an organic hole transport layer or an organic light emitting layer between a lower electrode and an upper electrode, and emits light when an electric field is applied to the organic thin film. The color gradation is obtained by controlling the current value flowing through the organic EL element. Display is performed by extracting light from one electrode (upper electrode) side.

  For this reason, the upper electrode on the light transmitting side (referred to as the display surface side) has a light transmitting property, and the electrode resistance tends to increase. As a mechanism for alleviating this problem, a mechanism is considered in which auxiliary wiring is provided in the same layer as the other lower electrode layer (see Patent Document 2).

JP 2004-207217 A

  In the mechanism described in Patent Document 2, auxiliary wiring is formed in a lattice shape so as to surround pixel circuits arranged in a two-dimensional matrix in the pixel array portion, and further, auxiliary wiring is provided so as to surround the outer periphery of the pixel array portion. Forming. The contact resistance is lowered by establishing electrical connection with the upper electrode over the entire outer periphery.

  By the way, in order to drive each pixel circuit of the pixel array unit, a vertical scanning line or a horizontal scanning line drawn from each pixel circuit arranged in a two-dimensional matrix in the pixel array unit must be connected to the driving circuit side. Don't be. As in the mechanism described in Patent Document 2, if the auxiliary wiring and the upper electrode are electrically connected over the entire outer periphery of the pixel array portion, the circuit is connected to a circuit outside the pixel array portion. The lead-out scanning lines (in particular, distinguished from the wiring in the pixel array section are also referred to as leading wirings) become long. If an additional circuit (details will be described later) such as an electrostatic protection circuit or a test switch circuit is provided, the wiring length is further increased.

  Here, the wiring outside the pixel array section for connection (lead-out wiring) needs to be laid out within a limited area outside the pixel array section. Generally, it is formed with a minimum line width. However, if the wiring width is narrow, disconnection is easy. When the lead wiring is disconnected, a signal for driving the pixel circuit is not transmitted to the transistor, so that proper display cannot be performed. Furthermore, this problem is caused by forming auxiliary wiring so as to surround the outer periphery of the pixel array portion as in the mechanism described in Patent Document 2, or providing additional circuits such as an electrostatic protection circuit and a test switch circuit. The longer the length, the greater the chance of occurrence (because the number of disconnection target points increases by the longer length).

  In order to solve such a problem, it is conceivable to increase the wiring width. However, as described above, it is necessary to lay out within a limited area outside the pixel array portion, which is difficult to employ. .

  The present invention has been made in view of the above circumstances, and prevents a display defect caused by disconnection of a scanning line (a lead wiring outside the pixel array section) that supplies a signal to each pixel circuit of the pixel array section. The purpose is to provide a mechanism that can do this.

  In one embodiment of the display device according to the present invention, a pixel circuit including an electro-optical element that performs display according to a signal amplitude and a pixel array section in which scanning lines are arranged in a matrix, and each scanning line of the pixel array section are drawn out. And a lead-out wiring that is a wiring for transmitting various signals for driving the pixel circuit.

  The lead-out wiring supplies the scanning line with a test signal input from a scanning circuit having a semiconductor element arranged in the periphery of the pixel array portion and supplying a signal to the scanning line, or an inspection apparatus for manufacturing inspection. And a test switch circuit having a switching element or a peripheral circuit portion including an electrostatic protection circuit having a protection element for protecting against electrostatic breakdown due to static electricity applied to the scanning line.

  In addition, the lead-out wiring is formed in a plurality of wiring layers, and contacts for electrical connection of the lead-out wiring in each wiring layer are formed in at least two places in the longitudinal direction of the lead-out wiring.

  By arranging the lead-out wiring in a plurality of wiring layers, that is, by making the lead-out wiring in multiple layers, even if the lead-out wiring of one of the wiring layers breaks between the contacts, the lead-out wiring of the other wiring layer The presence maintains the electrical connection between the contacts.

  According to one aspect of the present invention, even if the lead wiring of one wiring layer is disconnected between the contacts, the electrical connection between the contacts is maintained due to the presence of the lead wiring of the other wiring layer. Occurrence of display defects due to the is prevented.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Overview of display device>
1 and 1A are block diagrams showing an outline of the configuration of an active matrix display device which is an embodiment of a display device according to the present invention. Here, FIG. 1 shows a case of a COG mounting configuration in which a semiconductor chip for a control unit is directly mounted on a glass substrate on which a pixel array unit is mounted by COG mounting technology (details will be described later), and FIG. 1A shows a display panel. The pixel array portion is mounted on the part, and the peripheral circuit panel outside arrangement configuration in which the control unit is mounted on another substrate (for example, a flexible substrate) is shown.

  In the configuration example shown here, for example, an organic EL element that is a current-driven element is used as a display element (electro-optical element, light-emitting element) of a pixel, and a thin film transistor (TFT) is used as an active element. A case where the present invention is applied to an active matrix type organic EL display (hereinafter referred to as “organic EL display device”) in which an organic EL element is formed on a semiconductor substrate on which the substrate is formed will be described as an example.

  The thin film transistors can be broadly classified into, for example, an amorphous silicon TFT made of amorphous silicon, a microcrystalline silicon TFT made of microcrystalline silicon (nanocrystalline silicon), a multi-layer, depending on the type of semiconductor constituting the channel layer which is an active region. There are low-temperature polysilicon TFTs (non-alkali glass substrates) or high-temperature polysilicon TFTs (quartz glass substrates) made of crystalline silicon, and a mechanism for making the channel layer into a two-layer structure by combining these is also considered (reference) References 1-4). Depending on the type, for example, there are differences in element characteristics such as threshold voltage Vth, mobility μ, element variation, and stability over time. In this embodiment, the pixel array unit 102 and all its peripheral parts The semiconductor composing the channel layer is a microcrystalline silicon TFT that has relatively good variations in threshold voltage Vth (in-plane uniformity) and stability over time, and can provide a higher mobility than an amorphous silicon TFT. An example of applying a bottom gate structure in which the gate electrode is disposed on the substrate side will be described.

Reference 1: Japanese Patent Application Laid-Open No. 10-242052 Reference 2: Japanese Patent Application Laid-open No. 2007-5508 Reference 3: Japanese Patent Application Laid-Open No. 2007-35964 Reference 4: Ikuhiro Ikukai, “All about Thin Film Transistor Technology—Structure, Characteristics, From manufacturing process to next generation TFT- ", first edition, Japan, Industrial Research Committee, October 25, 2007, especially p74-88

  The display device 1 is a mobile terminal device such as a portable music player, a digital camera, a notebook personal computer, or a mobile phone using various electronic devices, for example, a recording medium such as a semiconductor memory, a mini disk (MD), or a cassette tape. In addition, video signals input to electronic devices such as video cameras and video signals generated in the electronic devices can be used in display units of electronic devices in various fields that display still images and moving images (videos).

  In the following description of the overall configuration, an organic EL element is specifically described as an example of a pixel display element. However, this is merely an example, and the target display element is not limited to an organic EL element. In general, all the embodiments described later can be applied to all electro-optical elements that emit light by current drive, and not only current drive but also all electro-optical elements that emit light by voltage drive. The embodiments of the present invention can be similarly applied.

  As shown in FIGS. 1 and 1A, a display device 1 has an aspect ratio in which a pixel circuit (also referred to as a pixel) P having an organic EL element (not shown) as a plurality of display elements is a display aspect ratio. Display panel unit 100 having a pixel array unit 102 arranged to form an effective video area of X: Y (for example, 9:16) as a main part, and various pulse signals for driving and controlling the display panel unit 100 A drive signal generation unit (so-called timing generator) 200 that is an example of a panel control unit that emits a video signal and a video signal processing unit 220 are provided. The drive signal generation unit 200 and the video signal processing unit 220 are built in a one-chip IC (Integrated Circuit), and are arranged outside the display panel unit 100 in this example.

  In the case of the COG mounting configuration shown in FIG. 1, the display panel unit 100 includes a pixel array unit 102 in which pixel circuits P are arranged in a matrix of n rows × m columns on a substrate 101. A vertical drive unit 103 that scans the pixel circuit P in the vertical direction and a horizontal drive unit 106 (also referred to as a horizontal selector or a data line drive unit) that scans the pixel circuit P in the horizontal direction are mounted by COG mounting technology, and for external connection The terminal portion (pad portion) 108 is disposed at the end of one side of the display panel portion 100. If necessary, an interface (IF) unit that interfaces each of the drive units 103 and 106 with an external circuit may be mounted by a COG mounting technique.

  The vertical drive unit 103 includes, for example, a write scan unit (write scanner WS; Write Scan) 104 and a drive scan unit (drive scanner DS; Drive Scan) 105 that functions as a power supply scanner having power supply capability. For example, the pixel array unit 102 is driven by the writing scanning unit 104 and the driving scanning unit 105 from one side or both sides in the horizontal direction shown in the figure, and driven by the horizontal driving unit 106 from one side or both sides in the vertical direction shown in the figure. It has come to be.

  The vertical driving unit 103 (the writing scanning unit 104 and the driving scanning unit 105) and the horizontal driving unit 106 control writing of the signal potential to the holding capacitor, threshold correction operation, mobility correction operation, and bootstrap operation. The control unit 109 is configured to function as a drive circuit that drives the pixel circuit P of the pixel array unit 102.

  The configuration of the illustrated vertical drive unit 103 and the corresponding scanning line is shown in conformity with the case where the pixel circuit P has a 2TR configuration of the present embodiment described later. However, depending on the configuration of the pixel circuit P, other configurations may be used. A scanning unit and a scanning line may be provided.

  Further, a protection circuit 142 and a test switch circuit 144 can be mounted on the display panel unit 100 as an example of the peripheral circuit unit 140 for each of the vertical driving unit 103 and the horizontal driving unit 106. The protection circuit 142 and the test switch circuit 144 are collectively referred to as an additional circuit 148. As the protection circuit 142, a protection circuit 142V for the vertical drive unit 103 and a protection circuit 142H for the horizontal drive unit 106 are provided for each scanning line, and as the test switch circuit 144, a test switch circuit 144V for the vertical drive unit 103 is provided. A test switch circuit 144H for the horizontal driving unit 106 is provided for each scanning line.

  The protection circuits 142V and 140H and the test switch circuits 144V and 142H are not formed by the COG mounting technology, but by a mechanism (TFT integrated configuration) that simultaneously generates each TFT in the process of generating the TFT of the pixel array unit 102. Yes. In the present embodiment, it is not essential to provide the protection circuits 142V (for the vertical drive unit 103) and 140H (for the horizontal drive unit 106) because of the relationship with the invention.

  Here, the significance of providing the protection circuit 142 and the test switch circuit 144 as the additional circuit 148 will be described as follows. First, as a product form, the display panel unit 100 in which the pixel array unit 102 and the control unit 109 are mounted on the same glass substrate, the drive signal generation unit 200, and the video signal processing unit 220 are separated (on the panel). The display panel unit 100 is mounted with a pixel array unit 102, and the control unit 109, the drive signal generation unit 200, the video signal processing unit 220, and the like are on a separate substrate (for example, a flexible substrate). A configuration in which a circuit is mounted (referred to as a peripheral circuit panel outside arrangement configuration) can be considered.

  Further, in the case where the pixel array unit 102 and the control unit 109 are mounted on the same glass substrate (substrate 101) and the display panel unit 100 is configured to be disposed on the panel, the process of generating the TFT of the pixel array unit 102 is performed. At the same time, the pixel is generated by a mechanism (referred to as a TFT integrated configuration) for generating each TFT for the control unit 109 (and the drive signal generation unit 200 and the video signal processing unit 220 as necessary) and COG (Chip On Glass) mounting technology. A mechanism (referred to as a COG mounting configuration) in which a semiconductor chip for the control unit 109 (and the drive signal generation unit 200 and the video signal processing unit 220 as necessary) is directly mounted on the substrate 101 on which the array unit 102 is mounted is considered. It is done.

  In the configuration outside the peripheral circuit panel and the COG mounting configuration (also collectively referred to as a control unit retrofit configuration), there is a point in time when the pixel array unit 102 and the control unit 109 are separate. Since the image display cannot be performed unless the pixel array unit 102 and the control unit 109 are connected, a defect of each pixel in the pixel array unit 102 (TFT short circuit or open) or a scan line defect (disconnection or adjacent scanning). Inspection such as contact with wire) cannot be performed.

  For this reason, when the control unit retrofit configuration is adopted, the purpose is to inspect each pixel and scanning line of the pixel array unit 102 in the peripheral portion of the pixel array unit 102 without connecting the control unit 109 to the pixel array unit 102. As a result, a test switch circuit 144 that can supply a test signal to each scanning line from the outside of the pixel array unit 102 is provided to perform a simple lighting test.

  Although various configurations are conceivable as the test switch circuit 144, for example, a mechanism in which the protection circuit 142 for electrostatic protection and the test switch circuit 144 are configured with different circuit elements, and a test signal is sent to the circuit element of the protection circuit 142. A mechanism of a protection & test switch circuit that is also used as a switch element constituting the test switch circuit 144 to be supplied to the scanning line can be considered (details will be described later). In the retrofitted configuration of the control unit, the protection circuit 142 has a point in time when the pixel array unit 102 and the control unit 109 are separated from each other. Since there is a greater possibility that static electricity will be applied via manufacturing equipment, etc. and the circuit elements will be destroyed than in the case of a TFT integrated configuration, each scanning line is provided for the purpose of protecting the circuit elements from static electricity damage due to static electricity. It is.

  Thus, in the mounted state, peripheral drive circuits such as the vertical drive unit 103, the horizontal drive unit 106, the protection circuits 142V and 140H, and the test switch circuits 144V and 142H are mounted on the same substrate 101 as the pixel array unit 102. It becomes the composition. In the illustrated example, the writing scanning unit 104, the driving scanning unit 105, and the horizontal driving unit 106 constituting the control unit 109 are configured by semiconductor chips and mounted on the display panel unit 100 by COG mounting technology. In order to clarify this also from the drawing, the control unit 109 (the writing scanning unit 104, the driving scanning unit 105, and the horizontal driving unit 106) is indicated by a dotted line. In addition, an electrical connection terminal PAD1 (Contact Pad) for connecting to the wiring on the display panel unit 100 when the COG is mounted is schematically shown.

  As a method of mounting an IC chip (IC: Integrated Circuit) such as the control unit 109 on the display panel unit 100 by the COG mounting technique, for example, a gold bump by electrolytic plating is used for an electrical connection terminal (bump), and the display panel A method of mounting on an electrode on the unit 100 by an ACF (Anisotropic Conductive Film) is known. Of course, other methods may be applied.

  As the protection circuits 142V and 140H and the test switch circuits 144V and 142H, for example, a mechanism in which the electrostatic protection circuit and the test switch circuit are constituted by different circuit elements may be adopted, or the circuit elements of the electrostatic protection circuit may be tested. You may employ | adopt the mechanism used as the protection & test switch circuit made to serve as a switch element which comprises the test switch circuit which supplies a signal to a scanning line.

  In the example shown in FIG. 1, the pulse signal is input from the outside of the display panel unit 100 via the terminal unit 108. However, the drive signal generation unit 200 that generates these various timing pulses is configured by a semiconductor chip. It can also be mounted on the display panel unit 100 by COG mounting technology.

  Various pulse signals are supplied to the terminal unit 108 from the drive signal generation unit 200 arranged outside the display device 1. Similarly, the video signal Vsig is supplied from the video signal processing unit 220. In the case of color display compatibility, video signals Vsig_R, G, and B for each color (in this example, three primary colors of R (red), G (green), and B (blue)) are supplied.

  For example, as a pulse signal for vertical driving, shift start pulses SPDS and SPWS which are examples of vertical write start pulses and vertical scanning clocks CKDS and CKWS (vertical scanning clocks xCKDS and xCKWS whose phases are reversed as necessary) ) And other necessary pulse signals are supplied. In addition, as a pulse signal for horizontal driving, necessary pulse signals such as a horizontal start pulse SPH, which is an example of a horizontal write start pulse, and a horizontal scanning clock CKH (and a horizontal scanning clock xCKH whose phase is inverted as necessary) are supplied. Is done.

  Each terminal of the terminal unit 108 is connected to the vertical driving unit 103 and the horizontal driving unit 106 via a signal line 199. For example, each pulse supplied to the terminal unit 108 is internally adjusted to a voltage level by a level shifter unit (not shown) as necessary, and then supplied to each unit of the vertical driving unit 103 and the horizontal driving unit 106 via a buffer. Supplied.

  Although the pixel array unit 102 is not shown in the drawing (details will be described later), pixel circuits P in which pixel transistors are provided with respect to an organic EL element as a display element are two-dimensionally arranged in a matrix form. On the other hand, scanning lines are wired for each row, and signal lines are wired for each column.

  For example, in the pixel array unit 102, the scanning lines 104WS and 105DSL on the vertical scanning side and video signal lines (data lines) 106HS which are scanning lines on the horizontal scanning side are formed in the pixel array unit 102. An organic EL element (not shown) and a thin film transistor for driving the organic EL element are omitted at the intersection between the vertical scanning lines and the horizontal scanning lines. A pixel circuit P is configured by a combination of an organic EL element and a thin film transistor.

  Specifically, for each pixel circuit P arranged in a matrix, the write scanning lines 104WS_1 to 104WS_n for n rows driven by the write scanning unit 104 with the write drive pulse WS and the drive scanning unit Power supply lines 105DSL_1 to 105DSL_n for n rows driven by the power supply drive pulse DSL by 105 are wired for each pixel row.

  The writing scanning unit 104 and the driving scanning unit 105 are configured by combinations of logic gates (including latches and shift registers), and select each pixel circuit P of the pixel array unit 102 in units of rows, that is, drive signal generation Each pixel circuit P is sequentially selected through the write scanning line 104WS and the power supply line 105DSL based on the vertical drive system pulse signal supplied from the unit 200.

  The horizontal drive unit 106 is configured by a combination of logic gates (including latches and shift registers), and selects each pixel circuit P of the pixel array unit 102 in units of columns, that is, supplied from the drive signal generation unit 200. Based on the pulse signal of the horizontal drive system, a predetermined potential in the video signal Vsig is sampled and written to the storage capacitor via the video signal line 106HS for the selected pixel circuit P.

  The display device 1 of the present embodiment is capable of line-sequential driving or dot-sequential driving, and the writing scanning unit 104 and the driving scanning unit 105 of the vertical driving unit 103 are pixels in line sequential (that is, in units of rows). The array unit 102 is scanned, and in synchronization with this, the horizontal drive unit 106 outputs the image signal for one horizontal line simultaneously (in the case of line sequential) or in units of pixels (in the case of dot sequential). Write to 102.

  As shown in the figure, the product form is provided as a display device 1 in the form of a module (composite part) including all of the display panel unit 100, the drive signal generation unit 200, and the video signal processing unit 220. For example, the display device can be provided only by the display panel unit 100, or the display device can be provided only by the pixel array unit 102.

  For example, the display device 1 includes a module-shaped one having a sealed configuration. For example, as shown in FIG. 1A, this corresponds to a case where the peripheral circuit panel is arranged outside. In this case, the pixel array unit 102 is configured as a display module including only the display panel unit 100 that is formed by being attached to an opposing unit such as transparent glass. The transparent facing portion is provided with a display layer (in this example, an organic layer and electrode layers on both sides thereof), a color filter, a protective film, a light shielding film, and the like.

  In the case of the arrangement outside the peripheral circuit panel (display module) shown in FIG. 1A, in addition to the pixel array unit 102, a circuit unit for inputting and outputting a video signal Vsig and various drive pulses to the pixel array unit 102 from the outside. TCP (Tape Carrier Package) method and COF (Chip On Flexible) method with FPC (flexible printed circuit) equipped with (equivalent to vertical driving unit 103 and horizontal driving unit 106 and its output driver). An electrical connection terminal PAD2 serving as an external connection terminal for connection is provided on the edge of the display panel unit 100. TCP is a name for a flexible tape in which a driver LSI (Large Scale Integrated Circuit) is mounted by bonding, and the method is usually TAB (Tape Automated Bonding). Incidentally, although FIG. 1A shows an example of the COF method, an example of the TCP method is shown in FIGS. 4 and 4A described later. Other points are basically the same as those in the COG mounting configuration.

  In FIGS. 1 and 1A, each element of the vertical driving unit 103 (the writing scanning unit 104 and the driving scanning unit 105), the protection circuit 142V, and the test switch circuit 144V are arranged only on one side of the pixel array unit 102. Although shown, it is also possible to adopt a configuration in which these are arranged on both the left and right sides with the pixel array unit 102 interposed therebetween. Similarly, FIG. 1 and FIG. 1A show a configuration in which the horizontal driving unit 106, the protection circuit 142H, and the test switch circuit 144H are arranged only on one side of the pixel array unit 102. It is also possible to adopt a configuration in which they are arranged on both the upper and lower sides.

  Further, regarding the mounting form of the control unit 109, FIG. 1 shows the case of a COG mounting configuration as an example of the on-panel arrangement configuration, and FIG. 1A shows the case of the arrangement configuration outside the peripheral circuit panel. In principle, the upper arrangement configuration is not limited to the COG mounting configuration, but may be a TFT integrated configuration. The term “in principle” is referred to here as a concept that can adopt a TFT integrated configuration, but in light of the background that the additional circuit 148 (the protection circuit 142 and the test switch circuit 144) is necessary, This is because it may be considered that the configuration including the protection circuit 142 and the test switch circuit 144 is hardly adopted while adopting the TFT integrated configuration.

  However, in the case of the TFT integrated configuration, it is not excluded to apply the mechanism of this embodiment described later to the control unit 109. In this case, since the TFT constituting the control unit 109 is manufactured integrally with the TFT constituting each pixel circuit P of the pixel array unit 102, the protection circuit 142 and the test switch circuit 144 are basically unnecessary. Instead, the control unit 109 may be handled as the peripheral circuit unit 140 and an embodiment described later may be applied. Of course, the provision of the protection circuit 142 and the test switch circuit 144 in the case of the TFT integrated configuration is not excluded. In this case, an embodiment described later may be applied to the control unit 109, the protection circuit 142, and the test switch circuit 144.

<Pixel circuit>
FIG. 2 is a diagram showing an embodiment of a pixel circuit P having a basic configuration of the present embodiment and an organic EL display device including the pixel circuit P. The display device 1 including the pixel circuit P having the basic configuration of the present embodiment in the pixel array unit 102 is referred to as a display device 1 having the basic configuration of the present embodiment. In addition, the vertical driving unit 103, the horizontal driving unit 106, the protection circuits 142V and 140H, and the test switch circuits 144V and 142H arranged on the periphery of the pixel array unit 102 on the substrate 101 of the display panel unit 100 are also shown. Yes. In order to indicate that there is a point in time when the control unit 109 is separate from the pixel array unit 102 in the peripheral circuit panel external arrangement configuration or COG mounting configuration (also collectively referred to as a control unit retrofit configuration), the control unit 109 (write The scanning unit 104, the driving scanning unit 105, and the horizontal driving unit 106) are indicated by dotted lines.

  Here, as described above, the protection circuits 142V and 140H are provided for each scanning line for all of the write scanning line 104WS, the power supply line 105DSL, and the video signal line 106HS. On the other hand, the test switch circuits 144V and 142H are provided for each scanning line for the write scanning line 104WS and the video signal line 106HS, but are not provided for the power supply line 105DSL.

  MOS transistors are used as the transistors including the drive transistor. In this case, for the drive transistor, the gate end is handled as the control input end, and either the source end or the drain end is handled as the input end, and the other is handled as the output end. In particular, regarding a driving transistor that supplies a driving current to the organic EL element 127, one of the source end and the drain end (here, the source end) is handled as an output end, and the other is the power supply end (here, the drain end). ).

  Hereinafter, an example of the pixel circuit P in the 2TR configuration will be specifically described. The pixel circuit P of the present embodiment shown in FIG. 2 is characterized in that the drive transistor is basically composed of an n-channel thin film field effect transistor. In addition, a circuit for suppressing fluctuations in the drive current Ids to the organic EL element due to deterioration over time of the organic EL element, that is, driving by correcting a change in current-voltage characteristics of the organic EL element which is an example of an electro-optical element A drive signal stabilization circuit (part 1) for maintaining the current Ids constant is provided.

  It is also characterized by the use of a drive method that maintains a constant drive current Ids by implementing a threshold correction function and mobility correction function that prevent drive current fluctuations due to drive transistor characteristic fluctuations (threshold voltage variations and mobility variations). Have. As a method for suppressing the influence on the drive current Ids due to characteristic variations of the drive transistor 121 (for example, variations and fluctuations in threshold voltage, mobility, etc.), the 2TR configuration drive circuit is directly adopted as the drive signal stabilization circuit (part 1). However, this is dealt with by devising the drive timing of the transistors 121 and 125.

  The pixel circuit P of the present embodiment is characterized by the connection mode of the storage capacitor 120, and is an example of a drive signal stabilization circuit (part 2) as a circuit that prevents drive current fluctuations due to deterioration with time of the organic EL element 127. A bootstrap circuit is configured. A feature is that it has a drive signal stabilization circuit (part 2) that realizes a bootstrap function that makes the drive current constant even when the current-voltage characteristic of the organic EL element changes with time (to prevent fluctuations in the drive current). It has.

  Incidentally, when the low-temperature polysilicon TFT is used as the driving transistor 121, the non-uniformity of the threshold voltage within the substrate surface is large, and the threshold correction function is almost essential, whereas the driving transistor 121 uses the microcrystalline silicon TFT. It is considered that the threshold voltage correction function can be removed because the non-uniformity of the threshold voltage in the substrate surface is small and the relationship with the required specifications. Here, an example in which all the above functions (threshold correction function, mobility correction function, bootstrap function) are applied will be described.

  Specifically, as illustrated in FIG. 2, the pixel circuit P of the present embodiment includes an n-channel driving transistor 121 and a sampling transistor 125, and an organic EL that is an example of an electro-optical element that emits light when current flows. An element 127 is included. In general, since the organic EL element 127 has a rectifying property, it is represented by a diode symbol. The organic EL element 127 has a parasitic capacitance Cel. In the figure, this parasitic capacitance Cel is shown in parallel with the organic EL element 127 (diode-like one).

  The storage capacitor 120 is connected between the source end (node ND121) and the gate end (node ND122) of the drive transistor 121, and the source end of the drive transistor 121 is directly connected to the anode end of the organic EL element 127. The storage capacitor 120 functions also as a bootstrap capacitor. The cathode terminal K of the organic EL element 127 is set to a cathode potential Vcath as a reference potential. This cathode potential Vcath is connected to a ground wiring Vcath (GND as an example) common to all pixels for supplying a reference potential.

  The ground wiring Vcath may be only a single-layer wiring (upper layer wiring) for the ground wiring Vcath. For example, an auxiliary wiring (auxiliary electrode) for cathode wiring is provided on the anode layer where the wiring for anode is formed. Reduce the resistance of the cathode wiring. This auxiliary wiring is, for example, wired in a grid, column, or row within the pixel array unit 102 (display area), and further wired around the pixel array unit 102 so as to have the same potential as the upper layer wiring. And a fixed potential is applied. Details of the auxiliary wiring will be described later.

  Sampling transistor 125 has a gate end connected to write scan line 104WS from write scan unit 104, a drain end connected to video signal line 106HS, and a source end connected to the gate end (node ND122) of drive transistor 121. Has been. An active H write drive pulse WS is supplied from the write scanning unit 104 to the gate end. The sampling transistor 125 may have a connection mode in which the source end and the drain end are reversed. As the sampling transistor 125, either a depletion type or an enhancement type can be used.

  The drain end of the drive transistor 121 is connected to a power supply line 105DSL from the drive scanning unit 105 that functions as a power scanner. The power supply line 105DSL is characterized in that the power supply line 105DSL itself has a power supply capability to the drive transistor 121. Specifically, the drive scanning unit 105 switches and supplies the first voltage Vcc on the high voltage side and the second voltage Vss on the low voltage side corresponding to the power supply voltage to the drain terminal of the drive transistor 121. A power supply voltage switching circuit is provided.

  The second potential Vss is set to a potential sufficiently lower than the offset potential Vofs of the video signal Vsig in the video signal line 106HS. Specifically, the gate-source voltage Vgs of the drive transistor 121 (the difference between the gate potential Vg and the source potential Vs) is larger than the threshold voltage Vth of the drive transistor 121. Two potential Vss is set. The offset potential Vofs is used for an initialization operation prior to the threshold correction operation and also used for precharging the video signal line 106HS in advance.

  In order to drive the pixel circuit P, a writing scanning unit 104, a driving scanning unit 105, and a horizontal driving unit 106 are arranged around the pixel array unit 102. The controller 109 functions as a drive signal stabilization circuit that maintains the drive current Ids flowing through the drive transistor 121 constant by optimizing the drive timing. For this reason, first, the drive scanning unit 105 preferably sets the sampling transistor 125 in a non-conducting state at the time when information corresponding to the signal amplitude Vin is written in the storage capacitor 120, and the video signal to the control input terminal of the drive transistor 121. It is preferable that the supply of Vsig is stopped and a bootstrap operation is performed in which the potential of the control input terminal is interlocked with the potential fluctuation of the output terminal of the driving transistor 121.

  The control unit 109 preferably executes the bootstrap operation even at the beginning of light emission after the end of the sampling operation. That is, the potential difference between the control input terminal and the output terminal of the drive transistor 121 is constant by turning the sampling transistor 125 in a conductive state after the signal potential is supplied to the sampling transistor 125 and then turning the sampling transistor 125 in a non-conductive state. To be maintained.

  In addition, the control unit 109 preferably controls the bootstrap operation so as to realize the temporal variation correction operation of the electro-optic element (organic EL element 127) in the light emission period. For this reason, the control unit 109 continuously keeps the sampling transistor 125 in a non-conductive state during a period in which the drive current Ids based on the information held in the holding capacitor 120 flows to the electro-optical element (organic EL element 127). Thus, it is preferable that the voltage variation at the control input terminal and the output terminal can be kept constant, and the temporal variation correction operation of the electro-optic element is realized. Even if the current-voltage characteristic of the organic EL element 127 varies with time due to the bootstrap operation of the storage capacitor 120 during light emission, the potential difference between the control input terminal and the output terminal of the drive transistor 121 is kept constant by the bootstrap storage capacitor 120. Therefore, a constant light emission luminance is always maintained.

  Preferably, the control unit 109 causes the sampling transistor 125 to conduct in a time zone in which the offset potential Vofs is supplied to the input terminal (the source terminal is a typical example) of the sampling transistor 125, thereby causing the threshold voltage Vth of the driving transistor 121 to be on. Control is performed so as to perform a threshold value correction operation for holding the voltage corresponding to. This threshold value correction operation is repeatedly executed at a plurality of horizontal periods preceding the writing of information corresponding to the signal amplitude Vin to the storage capacitor 120 as necessary, and reliably corresponds to the threshold voltage Vth of the drive transistor 121. It is preferable to hold the voltage in the holding capacitor 120.

  More preferably, prior to the threshold value correcting operation, the control unit 109 conducts the sampling transistor 125 in a time zone in which the offset potential Vofs is supplied to the input terminal of the sampling transistor 125 to perform a threshold value correcting preparatory operation ( Control is performed to execute a discharge operation or an initialization operation. Before the threshold correction operation, the potentials of the control input terminal and the output terminal of the drive transistor 121 are initialized. More specifically, the storage capacitor 120 is connected between the control input terminal and the output terminal, so that the potential difference between both ends of the storage capacitor 120 is set to be equal to or higher than the threshold voltage Vth.

<< Basic operation to keep driving current constant >>
In the threshold correction in the 2TR drive configuration, the drive scanning unit 105 of the control unit 109 supplies the drive current Ids to each pixel circuit P for one row in accordance with the scanning by the writing scanning unit 104, and the electro-optical element (organic EL). The first potential Vcc used to flow to the element 127) and the second potential Vss different from the first potential Vcc are switched and output. The write scanning unit 104 conducts the sampling transistor 125 in a time zone in which the voltage corresponding to the first potential Vcc is supplied to the power supply terminal of the driving transistor 121 and the signal potential is supplied to the sampling transistor 121. Control is performed so as to perform the threshold correction operation.

  In the threshold correction preparation operation in the 2TR drive configuration, sampling is performed in a time zone in which the voltage corresponding to the second potential Vss is supplied to the power supply terminal of the drive transistor 121 and the signal potential is supplied to the sampling transistor 125. It is preferable to initialize the potential of the control input terminal of the driving transistor 121 to the reference potential Vin and the potential of the output terminal to the second potential Vss by making the transistor 125 conductive.

  More preferably, after the threshold correction operation, the control unit 109 conducts the sampling transistor 125 in a time zone in which the voltage corresponding to the first potential Vcc is supplied to the driving transistor 121 and the signal potential is supplied to the sampling transistor 125. Thus, when information on the signal amplitude Vin is written in the storage capacitor 120, the correction for the mobility μ of the driving transistor 121 is controlled to be added to the information written in the storage capacitor 120. At this time, it is preferable that the sampling transistor 125 is turned on at a predetermined position within a time zone in which the signal potential is supplied to the sampling transistor 125 for a period shorter than the time zone.

  A circuit configuration that realizes a bootstrap function in which a holding capacitor 120 is disposed between the gate and the source of the driving transistor 121 and the potential Vg of the gate end is interlocked with the fluctuation of the potential Vs of the source end of the driving transistor 121. Further, by setting the drive timing, even if there is an anode potential variation (that is, a source potential variation) of the organic EL element 127 due to a variation with time in the characteristics of the organic EL element 127, the gate potential Vg is varied so as to cancel the variation. Thus, uniformity of screen brightness can be ensured. The bootstrap function can improve the deterioration correction capability of a current-driven light emitting element typified by an organic EL element. Of course, in the bootstrap function, the light emission current Iel begins to flow through the organic EL element 127 at the start of light emission, and as a result, the anode-cathode voltage Vel rises until it becomes stable. It also functions when the source potential Vs of the drive transistor 121 varies with the variation of the voltage Vel.

  In addition, due to variations in the manufacturing process of the drive transistor 121, there are fluctuations in characteristics such as threshold voltage and mobility for each pixel circuit P. Even when the driving transistor 121 is driven in the saturation region, even if the same gate potential is applied to the driving transistor 121 due to this characteristic variation, the drain current (driving current Ids) varies for each pixel circuit P, and the emission luminance is reduced. Appears as variations.

  On the other hand, by setting the drive timing to realize the threshold value correction function and the mobility correction function, the influence of those fluctuations can be suppressed, and the uniformity of the screen brightness can be ensured. In the threshold value correction operation and the mobility correction operation of the present embodiment, details are omitted, but assuming that the writing gain is 1 (ideal value), the gate-source voltage Vgs at the time of light emission is “Vin + Vth−ΔV”. Thus, the drain-source current Ids is not dependent on the variation or variation of the threshold voltage Vth, and is not dependent on the variation or variation of the mobility μ. As a result, even if the threshold voltage Vth and the mobility μ vary depending on the manufacturing process, the drive current Ids does not vary, and the light emission luminance of the organic EL element 127 does not vary.

<Operation of Pixel Circuit: This Embodiment>
FIG. 2A is a timing chart for explaining the operation when the information of the signal amplitude Vin is written in the storage capacitor 120 by the line sequential method as an example of the drive timing related to the pixel circuit P of the present embodiment shown in FIG. Here, in the example shown in FIG. 2A, the operation and mobility correction for writing information in accordance with the signal amplitude Vin to the storage capacitor 120 are determined by the rise and fall of the write drive pulse WS applied to the write scan line 104WS. It is an aspect to do.

  In the following, for ease of explanation and understanding, unless otherwise specified, it is assumed that the write gain is 1 (ideal value), and information on the signal amplitude Vin is written and held in the holding capacitor 120. Or it will be described briefly as sampling. Actually, the write gain is less than 1, and the holding capacitor 120 holds not the magnitude of the signal amplitude Vin itself but the information multiplied by the gain corresponding to the magnitude of the signal amplitude Vin. For ease of explanation and understanding, unless otherwise noted, the bootstrap gain is assumed to be 1 (ideal value) and will be described briefly.

  In the basic concept of threshold value correction and mobility correction at the drive timing in the pixel circuit P having the 2TR configuration, first, the video signal Vsig has an offset potential Vofs and a signal potential (Vofs + Vin) within a 1H period. A period which is divided in time and is in the offset potential Vofs which is an ineffective period is a first half of one horizontal period, and a period which is in a signal potential (Vofs + Vin) which is an effective period is a second half of one horizontal period.

  Further, the write drive pulse WS used for signal writing is also used for threshold correction and mobility correction. Preferably, the write drive pulse WS is activated twice within 1H period to turn on the sampling transistor 125. This is because the sampling (writing operation) of the signal amplitude Vin information and the mobility correction are determined by the rise and fall of the write drive pulse WS applied to the write scan line 104WS. Then, threshold correction is performed at the first on timing, and signal voltage writing and mobility correction are performed simultaneously at the second on timing. Thereafter, the driving transistor 121 receives a current from the power supply line 105DSL at the first potential (high potential side) and is held in the holding capacitor 120 (potential corresponding to the potential of the video signal Vsig during the effective period). In response to this, the drive current Ids is passed through the organic EL element 127.

  For example, in the light emission periods B and I, the power supply drive pulse DSL is at the first potential Vcc, the write drive pulse WS is inactive L, and the sampling transistor 125T1 is turned off. At this time, since the drive transistor 121 is set to operate in the saturation region, the drive current Ids flowing through the organic EL element 127 takes a value corresponding to the gate-source voltage Vgs of the drive transistor 121. The current flowing between the drain end and the source of the transistor operating in the saturation region is Ids, the mobility is μ, the channel width (gate width) is W, the channel length (gate length) is L, and the gate capacitance (gate oxidation per unit area) The driving transistor 121 is a constant current source having a value expressed by the following equation (1), where Cox is the film capacitance and Vth is the threshold voltage of the transistor. As apparent from the equation (1), the drain current Ids of the transistor is controlled by the gate-source voltage Vgs in the saturation region.

  Next, in the non-emission period, first, in the discharge period C, when the power driving pulse DSL is set to the second potential Vss, the organic EL element 127 is extinguished, and the power driving pulse DSL becomes the source of the driving transistor 121, and the organic EL element. The anode 127 is charged to the second potential Vss. Further, when the potential of the video signal line 106HS becomes the offset potential Vofs in the initialization period D, the write drive pulse WS is set to active H, the sampling transistor 125 is turned on, and the gate potential of the drive transistor 121 is set to the offset potential Vofs. To do.

  Thereafter, in the threshold correction period E, the potential of the power supply line 105DSL changes from the second potential Vss on the low potential side to the first potential Vcc on the high potential side, so that the gate terminal of the drive transistor 121 is held at the offset potential Vofs. In this state, the storage capacitor 120 and the parasitic capacitor Cel are charged by the drive current Ids. After a predetermined time has elapsed, the write drive pulse WS is set to inactive L and the sampling transistor 125 is turned off. If the threshold correction period is sufficient, this operation causes the gate-source voltage Vgs of the drive transistor 121 to take the value Vth.

  That is, when the potential difference between the potential of the node ND121 (source potential Vs) and the voltage of the node ND122 (gate potential Vg) has just reached the threshold voltage Vth, the driving transistor 121 changes from the on state to the off state (cuts off), and the driving is performed. The source potential Vs of the transistor 121 becomes “Vofs−Vth” and the drain current stops flowing, and the threshold correction period ends. That is, after a certain time has elapsed, the gate-source voltage Vgs of the drive transistor 121 takes a value called the threshold voltage Vth. By this threshold value correction function, it is possible to cancel the influence of the threshold voltage Vth of the drive transistor 121 that varies for each pixel circuit P. At this time, since the organic EL element 127 is reverse-biased, the organic EL element 127 does not emit light.

  Here, the threshold correction operation may be executed only once, but this is not essential. If necessary, the threshold correction operation may be repeated a plurality of times with one horizontal period as a processing cycle. For example, in practice, a voltage corresponding to the threshold voltage Vth is written in the storage capacitor 120 connected between the gate terminal and the source terminal of the driving transistor 121. However, the threshold correction period E is from the timing when the write drive pulse WS is set to active H to the timing when it is returned to inactive L. If this period is not sufficiently secured, the threshold correction period E ends before that. . In order to solve this problem, it is preferable to repeat the threshold correction operation a plurality of times. Here, illustration of the timing is omitted, but the threshold correction operation is repeatedly executed in a plurality of horizontal periods preceding the sampling (signal writing) of the signal amplitude Vin to the holding capacitor 120, so that the driving transistor is surely obtained. A voltage corresponding to the threshold voltage Vth of 121 is held in the holding capacitor 120.

  In addition to the threshold correction function, the control unit 109 according to the present embodiment has a mobility correction function that simultaneously corrects the mobility μ of the drive transistor 121 when holding information according to the signal amplitude Vin in the storage capacitor 120. I have. Incidentally, the period during which the signal potential (Vofs + Vin) is actually supplied to the video signal line 106HS by the horizontal drive unit 106 and the write drive pulse WS is set to active H is the period during which the signal amplitude Vin is written to the storage capacitor 120 ( Also referred to as a sampling period). In 2A, the sampling period and the mobility correction period are handled in the same manner and are referred to as a writing & mobility correction period H.

  In the writing & mobility correction period H, the sampling transistor 125 is in a conductive (on) state when the gate potential Vg of the driving transistor 121 is at the signal potential (Vofs + Vin), so that the gate end of the driving transistor 121 is at the signal potential. In a state of being fixed at (Vofs + Vin), the drive current Ids flows from the power supply line 105DSL to the drive transistor 121, and the capacitance value Cel of the capacitance value Cs of the storage capacitor 120 and the parasitic capacitance (equivalent capacitance) Cel of the organic EL element 127. The source potential Vs rises with time because it flows into the capacitance “C = Cs + Cel” (both other parasitic capacitances are neglected) and the charging is started. At this time, since the threshold value correcting operation of the driving transistor 121 is completed, the driving current Ids flowing through the driving transistor 121 reflects the mobility μ. As a result, the gate-source voltage Vgs of the driving transistor 121 is reduced to reflect the mobility μ, and becomes a gate-source voltage Vgs that completely corrects the mobility μ after a predetermined time has elapsed. In the timing chart of FIG. 2A, this increase is represented by ΔV. This increase, that is, the negative feedback amount ΔV, which is the mobility correction parameter, is subtracted from the gate-source voltage “Vgs = Vin + Vth” held in the holding capacitor 120 by the threshold correction, and “Vgs = Vin + Vth−ΔV”. Therefore, negative feedback is applied.

  Thereafter, the write scanning unit 104 cancels the application of the write drive pulse WS to the write scan line 104WS at the stage where the information of the signal amplitude Vin is held in the holding capacitor 120 (ie, inactive L (low)). ), The light emission period I is entered by making the sampling transistor 125 non-conductive and electrically disconnecting the gate terminal of the drive transistor 121 from the video signal line 106HS. When proceeding to the light emission period I, the horizontal driving unit 106 returns the potential of the video signal line 106HS to the offset potential Vofs at an appropriate time thereafter. Thereafter, the process proceeds to the next frame (or field), and the threshold correction preparation operation, the threshold correction operation, the mobility correction operation, and the light emission operation are repeated again.

  In the light emission period I, the application of the signal potential (Vofs + Vin) to the gate terminal of the drive transistor 121 is released, so that the gate potential Vg of the drive transistor 121 can be increased. A storage capacitor 120 is connected between the gate terminal and the source terminal of the driving transistor 121, and a bootstrap function is realized by the effect of the storage capacitor 120. Assuming that the bootstrap gain is 1 (ideal value), the gate potential Vg is completely linked to the variation of the source potential Vs of the driving transistor 121, and the gate-source voltage Vgs is kept constant. Can do.

  At this time, the drive current Ids flowing through the drive transistor 121 flows through the organic EL element 127, and the anode potential of the organic EL element 127 rises according to the drive current Ids. Let this increase be Vel. Eventually, as the source potential Vs rises, the reverse bias state of the organic EL element 127 is canceled, so that the organic EL element 127 actually starts to emit light by the inflow of the drive current Ids. The rise (Vel) of the anode potential of the organic EL element 127 at this time is nothing but the rise of the source potential Vs of the drive transistor 121, and the source potential Vs of the drive transistor 121 rises by Vel.

  The relationship between the drive current Ids and the gate voltage Vgs is obtained by substituting “Vin−ΔV + Vth” into Vgs of the equation (1) representing the transistor characteristics when the write gain is “1”. Can be expressed as: In formula (2), k = (1/2) (W / L) Cox.

  From this equation (2), it can be seen that the term of the threshold voltage Vth is canceled and the drive current Ids supplied to the organic EL element 127 does not depend on the threshold voltage Vth of the drive transistor 121. Since the drive current Ids is basically determined by the signal amplitude Vin (specifically, the sampling voltage held in the holding capacitor 120 corresponding to the signal amplitude Vin = Vgs), the organic EL element 127 emits light with a luminance corresponding to the signal amplitude Vin. Will do. At this time, the information held in the holding capacitor 120 is corrected by the feedback amount ΔV. This correction amount ΔV works so as to cancel the effect of the mobility μ located in the coefficient part of the equation (2). Therefore, the drive current Ids substantially depends only on the signal amplitude Vin. Since the drive current Ids does not depend on the threshold voltage Vth, even if the threshold voltage Vth varies depending on the manufacturing process, the drain-source drive current Ids does not vary, and the light emission luminance of the organic EL element 127 does not vary.

  In addition, a storage capacitor 120 is connected between the gate terminal G and the source terminal S of the drive transistor 121. Due to the effect of the storage capacitor 120, a bootstrap operation is performed at the beginning of the light emission period. The gate potential Vg and the source potential Vs of the drive transistor 121 rise while the gate-source voltage Vgs of the transistor is kept constant, and the gate potential Vg becomes “Vofs + Vin + Vel”. At this time, since the gate-source voltage Vgs of the drive transistor 121 is constant, the drive transistor 121 passes a constant current (drive current Ids) to the organic EL element 127. As a result, the potential at the anode end A of the organic EL element 127 (= potential at the node ND121) rises to a voltage at which a current called a drive current Ids in a saturated state can flow through the organic EL element 127.

Here, since the IV characteristic of the organic EL element 127 changes as the light emission time becomes longer, the potential of the node ND121 also changes over time. However, the drive transistor 121 is driven by the bootstrap function of the storage capacitor 120. Since the gate-source potential Vgs is kept constant, the current flowing through the organic EL element 127 does not change, and the light emission luminance of the organic EL element 127 is also kept constant.
<< Auxiliary Wiring Layout >>
3 and 3A are problems related to wiring between the control unit 109 (the writing scanning unit 104, the driving scanning unit 105, and the horizontal driving unit 106) arranged around the pixel array unit 102 and the pixel array unit 102. FIG. FIG. Here, FIG. 3 is an overall schematic diagram showing the layout of the first example of the lower electrode and the auxiliary wiring of the organic EL element 127. FIG. 3A is a diagram illustrating a layout of a second example which is a modification example of FIG.

  A layout of the first example of the lower electrode and the auxiliary wiring of the organic EL element 127 is shown in FIG. As shown in this figure, the lower electrodes 504 of the organic EL elements 127 are arranged in a two-dimensional matrix corresponding to the arrangement of the pixel circuits P arranged in a matrix. The organic EL element 127 has a laminated structure of a lower electrode 504, an organic layer 506, and an upper electrode 508. Between the lower electrodes 504, auxiliary wirings 515 configured in the same layer as the lower electrodes 504 are arranged in a lattice shape so as to surround the lower electrodes 504 (that is, the pixel circuits P), and further on the outer periphery of the pixel array section. The configuration is wired so as to surround the whole 102. A portion of the auxiliary wiring 515 that surrounds the entire pixel array unit 102 is distinguished from a grid-shaped auxiliary wiring in the pixel array unit 102 and is particularly referred to as an annular auxiliary wiring. The auxiliary wiring 515 of the anode layer L3 on which the lower electrode 504 is formed is connected to the upper electrode 508 on the upper layer by a cathode contact KC at an appropriate location (in the example in the figure, the center and the entire outer periphery between each pixel). The

  In the layout of the second example shown in FIG. 3A, the auxiliary wiring 515 is arranged so as to surround the entire pixel array unit 102 in order to increase the pixel aperture ratio when the top emission type high-definition pixel structure is used. Thus, a layout in which the pixel array unit 102 (display area) is wired in a grid, a column, or a row is not used. For example, a high-definition pixel may not use an auxiliary wiring layout in the pixel in order to increase the aperture ratio.

  In any configuration, the auxiliary wiring 515 is wired so as to surround the entire pixel array unit 102, and the contact with the upper electrode is taken over the entire outer periphery, thereby reducing the contact resistance with the upper electrode (cathode electrode). ing. Thus, when the auxiliary wiring 515 is made wider than the pixel array portion 102 in order to reduce the contact resistance with the upper electrode, as shown in FIG. 3 and FIG. 3A (see also FIG. 4 and FIG. 7 described later), the auxiliary wiring 515 The wiring 515 overlaps each scanning line Lscan (write scanning line 104WS, power supply line 105DSL, video signal line 106HS) connected from the control unit 109 to the pixel array unit 102 in a wide range.

<< Problem of wiring structure at the panel edge >>
4 to 5H are diagrams illustrating a comparative example of the mounting manner around the pixel array unit 102. FIG. These drawings explain the problem of the wiring structure at the edge of the panel. Here, FIG. 4 and FIG. 4A show the case of the arrangement configuration outside the peripheral circuit panel shown in FIG. 1A, and in particular, FIG. 4A shows details of TCP mounting.

  FIG. 5 is a perspective plan view for explaining the arrangement relationship between the auxiliary wiring 515 and each scanning line Lscan in the comparative example. 5A (1) is a cross-sectional view in a direction (aa ′ line) orthogonal to the longitudinal direction of the scanning line Lscan in FIG. 5, and FIG. 5A (2) is a longitudinal direction (b−) of the scanning line Lscan in FIG. It is sectional drawing of b 'line.

  5B to 5E, focusing on the scanning lines of the vertical scanning system, outlines the locations where the lead-out wiring Ldrawn is connected to the pixel array unit 102 in the outer periphery of the pixel array unit 102 that is the display area. FIG. Here, FIG. 5B is a layout example (plan view), FIG. 5C is a plan view of the whole outline, FIG. 5D is an enlarged view (plan view and cross-sectional view) of a dotted line part in FIG. FIG. 5E is a diagram for explaining the details of the intersection of the first wiring layer L1 and the second wiring layer L2.

  5F to 5H are diagrams illustrating a state in which the protection circuit 142 and the test switch circuit 144 are provided on the outer periphery of the pixel array unit 102. FIG. Here, FIG. 5F is a layout example (plan view) focusing on the scanning lines of the vertical scanning system, and FIG. 5G is a circuit diagram of the protection circuit 142 and a plan view showing an outline of the layout. FIG. 5H is a plan view showing an outline of the layout when focusing on the circuit diagram of the test switch circuit 144 and the scanning lines (R, G, B video signal lines 106HS) of the horizontal scanning system.

  As shown in FIG. 4 and FIG. 4A, an electrical connection terminal PAD2 for connecting by the COF method is provided at the edge portion of the substrate 101 of the display panel unit 100. On the substrate 101, a pixel array portion 102 serving as a display area is provided, and an auxiliary wiring 515 is provided outside the pixel array portion 102. The auxiliary wiring 515 is a ground wiring Vcath that is common to all pixels together with the upper electrode that is not shown in the figure, and is a power supply that is an example of the electrical connection terminal PAD2 provided at the edge of the substrate 101 of the display panel section 100. A reference voltage (GND as an example) is supplied from the TCP 520. Although two power supply TCPs 520 are provided in FIG. 4 and four power supply TCPs 520 are provided in FIG. 4A, the number is arbitrary.

  The electrical connection terminal PAD2 for the control unit 109 is also substantially the same as the power supply TCP 520, and the signal supply TAB 530_WS for the write drive pulse WS provided at the edge portion of the substrate 101 of the display panel unit 100, the power Each signal is supplied from the power input unit 530_DSL for the driving pulse DSL and the signal supply TAB 530_sig for the video signal Vsig. A driver LSI 532 is bonded to each signal supply TAB 530 by the TAB method, the driver output is connected to the edge of the substrate 101, and the driver LSI 532 is mounted outside the substrate 101. Although not shown, a circuit board on which a pre-stage circuit (for example, a shift register) for supplying a signal to the driver LSI 532 is connected is connected to each signal supply TAB 530 on the side opposite to the board 101.

  Here, in the mounting example of the comparative example shown in FIGS. 4 and 4A, the entire additional circuit 148 in the periphery of the pixel array unit 102 is shielded by a solid film using the auxiliary wiring 515 of the anode layer L3. That is, in the mounting example of the comparative example, the auxiliary wiring 515 is provided wider than the area for the cathode contact KC on the outer periphery of the pixel array unit 102, and the auxiliary wiring 515 covers the entire additional circuit 148. Yes. By doing so, the phenomenon that light enters the transistor of the peripheral circuit section 140 is prevented.

  As shown in FIGS. 5 and 5A, auxiliary wiring in the same layer as the lower electrode 504 (in this example, the anode electrode) in the peripheral portion of the pixel array unit 102, that is, between the pixel array unit 102 and the control unit 109. 515 is a structure in which an interlayer insulating film 502b and an interlayer insulating film 503 which are dielectrics are sandwiched between the drawing line Ldrawn of the scanning line Lscan (the writing scanning line 104WS, the power supply line 105DSL, and the video signal line 106HS). Wrapped structure). Accordingly, the length of the lead wiring Ldrawn becomes longer. In addition, in this example, since the peripheral circuit unit 140 is disposed between the pixel array unit 102 and the control unit 109, the length corresponding to the peripheral circuit unit 140 is required.

  The material of the scanning line Lscan is various, but is selected from the following viewpoints, for example. First, paying attention to the inside of the pixel array unit 102, at least the writing scanning line 104WS and the power supply line 105DSL related to the vertical scanning system become one of the vertical / horizontal wirings (for example, horizontal wiring), and the horizontal scanning is performed on this. The video signal line 106HS related to the system is the other vertical / horizontal wiring (for example, vertical wiring). If the cathode potential Vcath of the organic EL element 127 is a normal wiring instead of a solid wiring, the wiring for the cathode potential Vcath (cathode wiring) is a horizontal wiring or a vertical wiring.

  Each of the wirings (the write scanning line 104WS, the power supply line 105DSL, and the video signal line 106HS) extends in the horizontal direction or the vertical direction, and the corresponding scanning unit (write scanning unit) provided around the pixel array unit 102. 104, drive scanning unit 105, and horizontal drive unit 106). When the horizontal direction of the screen is considered, a detailed explanatory diagram is omitted, but the write drive pulse WS is commonly supplied from the write scanning unit 104 to all the pixel circuits P in one row. The pixel circuit P (referred to as a far-side pixel) farther from the writing scanning unit 104 is closer to the writing scanning unit 104 (referred to as a near-side pixel) because the waveform of the pulse WS is affected by the wiring capacitance or wiring resistance. ), The waveform becomes dull. For this reason, the distribution characteristics of the wiring capacitance and the wiring resistance may affect the operations of threshold correction and mobility correction. The same applies to the power supply line 105DSL and the video signal line 106HS (or the cathode wiring), and the distribution characteristics of the wiring capacitance and wiring resistance may affect the operations of threshold correction and mobility correction. is there.

  In consideration of these points, each wiring is wired using a single-layer metal wiring such as aluminum Al, molybdenum Mo, and titanium Ti or a multi-layered metal wiring that does not have optical transparency so as to reduce resistance. . As described above, since vertical wiring and horizontal wiring are required, basically, at least two layers (in this example, the first wiring layer L1) are overlapped at the intersection of the vertical wiring and the horizontal wiring. And metal wiring of the second wiring layer L2) is required.

  Further, paying attention to the difference between the first wiring layer L1 and the second wiring layer L2, the first wiring layer L1 is heat treatment (annealing process) for forming a thin film transistor, and therefore needs to be resistant to heat. Molybdenum Mo is preferably used although it has higher resistance than Al or titanium Ti. That is, the heat capacity of the electrode material of the first wiring layer L1 is preferably as small as possible so as to serve as a heat sink in the heat treatment process. Aluminum Al or an alloy material thereof is not suitable as an electrode material for the first wiring layer L1 because heat lock, whisker, or void is generated in the heat treatment process.

  In particular, when a microcrystalline silicon TFT is used as the thin film transistor, the degree of required heat resistance is increased. This is because, unlike heat treatment using an excimer laser, a continuous wave laser beam (continuous laser beam and continuous laser beam) is generated from a high-power semiconductor laser device having a light intensity profile shaped into a line shape or a square shape, in order to form a microcrystalline silicon TFT. ), Move (scan) the amorphous silicon film one row at a time at a constant speed, slide it to the next row, and then start scanning in the same or reverse direction as in the previous row By repeating this operation, irradiation is performed over the entire region, and the amorphous silicon film is changed to a microcrystalline silicon film. Therefore, the amount of heat necessary for crystallization becomes very large.

  On the other hand, the second wiring layer L2 is not required to have heat resistance as compared with the first wiring layer L1, and mainly from the viewpoint of lowering resistance, for example, aluminum Al or titanium Ti having lower resistance than molybdenum Mo or those It is preferable to use an alloy material (such as Ti—Al—Ti).

  When attention is paid to the peripheral portion of the pixel array unit 102, regardless of whether the pixel array unit 102 is the first wiring layer L1 or the second wiring layer L2, the lead-out wiring Ldrawn is connected to the pixel circuit P from the outer periphery of the panel. Since the molybdenum has a high resistance, the second wiring layer L2 to which an electrode material having a lower resistance than molybdenum Mo is applied is used from the viewpoint of reducing the resistance. Incidentally, the scanning line Lscan in which the pixel array unit 102 is the first wiring layer L1 needs to be transferred to the second wiring layer L2 at the edge of the pixel array unit 102.

  Here, since the wiring (drawing wiring) outside the pixel array portion for connection needs to be laid out within a limited area outside the pixel array portion, the power supply line 105DSL that requires a large current is relatively wide. However, the other write scanning lines 104WS and video signal lines 106HS are formed with a minimum line width in accordance with the pattern design rule.

  However, if the wiring width is narrow, disconnection is likely to occur, and the pixel circuit P of the pixel array unit 102 does not function normally due to disconnection, and display defects are likely to occur. For example, disconnection may occur due to mechanical stress applied in the manufacturing process.

  Further, as shown in FIGS. 5B to 5E, when the layer structure of the pixel array portion 102 (around the lead-out wiring portion) and the layer structure of the lead-out wiring are different, a step is generated, and the lead-out wiring is further easily disconnected. That is, the auxiliary wiring 515 is annularly arranged in the second wiring layer L2 on the outer periphery of the display area (in the vicinity of the pixel array section 102). In order to prevent an interlayer short circuit from occurring, an a-Si forming an TFT and an etching stop layer are arranged at the intersection of the first wiring layer L1 and the second wiring layer L2 in addition to the gate insulating film. As shown in FIG. 5E, in order to reduce the resistance of the first wiring layer L1 at the intersection of the first wiring layer L1 and the second wiring layer L2 in the pixel array portion 102 (pixel region) and the outer periphery of the pixel region. For example, a structure in which low resistance metals such as MO and Clad (AlNd) are conjugated (laminated) is employed. 5F to 5H, when the protection circuit 142 and the test switch circuit 144 are provided on the outer periphery of the pixel array unit 102, the layer structure of the protection circuit 142 and the test switch circuit 144 (around the lead-out wiring unit) Since the layer structure of the lead-out wiring is different, a step is generated, and the lead-out wiring is further easily disconnected.

  Further, even when a heat treatment is applied in the subsequent process after forming the second wiring layer L2, for example, when the organic EL element 127 is formed, the extraction wiring Ldrawn is formed in the second wiring layer L2 using the electrode material having inferior heat resistance. If it forms, it will become easy to disconnect by heat stress.

<Improvement method: basic concept>
Therefore, in the present embodiment, each lead-out wiring Ldrawn is arranged in a plurality of wiring layers using a wiring layer other than the second wiring layer L2 (to make the lead-out wiring Ldrawn redundant), thereby The problem of display failure due to “disconnection” will be solved. A so-called backup concept is adopted in which even if the lead-out wiring Ldrawn of one wiring layer is disconnected, the occurrence of display defects is prevented by the presence of the lead-out wiring Ldrawn of the other wiring layer.

  Here, when arranging the lead-out wiring Ldrawn in a plurality of wiring layers, various mechanisms can be considered as to how the wiring layers other than the second wiring layer L2 are set. For example, the first wiring layer L1 It is conceivable to arrange the wiring layers, and it is also conceivable to add third and fourth wiring layers other than the first wiring layer L1 and the second wiring layer L2. However, adding the third and fourth wiring layers may be disadvantageous in that the manufacturing process becomes complicated and costs increase. Therefore, in the present embodiment, the extraction wiring Ldrawn of each scanning line Lscan drawn from the pixel array portion 102 to the outer peripheral portion is formed by the first wiring layer L1 and the second wiring layer L2. Hereinafter, the lead wiring Ldrawn of the first wiring layer L1 is referred to as a first lead wiring Ldrawn_L1, and the lead wiring Ldrawn of the second wiring layer L2 is referred to as a second lead wiring Ldrawn_L2.

  The lead wiring Ldrawn formed of two layers establishes electrical connection (the connection point is referred to as a contact LC) in at least two places (preferably in the vicinity of the end in the layer) in the longitudinal direction. In this way, between the contacts LC, even if the first wiring layer L1 or the second wiring layer L2 is disconnected, the other wiring layer is connected. In other words, it is possible to prevent the pad or IC on the outer periphery of the panel from being disconnected from the pixel circuit P. The more points where the contact LC is taken, the greater the resistance to disconnection in each layer. Further, as an additional effect, when no disconnection occurs, the wiring resistance is lowered, so that the voltage drop of the lead wiring Ldrawn can be suppressed.

  Further, as an additional effect of using the first wiring layer L1, it is possible to suppress variations in TFT characteristics by making the thermal profile in the panel uniform during annealing with continuous laser light when forming microcrystalline silicon TFTs. Can do.

<< Improvement Method: First Embodiment >>
6 to 6B are diagrams for explaining a first embodiment of a wiring arrangement (layout) that can prevent a display defect caused by disconnection of the lead wiring Ldrawn. Here, FIG. 6 is a perspective plan view for explaining the arrangement relationship between the auxiliary wiring 515 and each scanning line Lscan in the first embodiment. 6A is a cross-sectional view in the direction (a ′ ′ line) perpendicular to the longitudinal direction of the scanning line Lscan in FIG. 6, and FIG. 6B is the addition of the longitudinal direction (bb ′ line) of the scanning line Lscan in FIG. They are a plan perspective view (1) and a cross-sectional view (2) focusing on the transistor of the circuit 148 (particularly the protection circuit 142).

  The first embodiment is an example of a layout in the case where an additional circuit 148 (protection circuit 142 or test switch circuit 144) is provided between the pad or control unit 109 and the pixel array unit 102. The first embodiment is different from the second embodiment described later in that the area where the additional circuit 148 is disposed in the longitudinal direction of the lead wiring Ldrawn is only the second wiring layer L2. Have. As understood from FIGS. 5F to 5H, various wirings pass (cross) in the region where the additional circuit 148 is disposed. Therefore, in the actual layout plane, there is a duplication of the drawing wiring Ldrawn. This is because stratification becomes difficult. However, if the problem can be solved in terms of layout, it is preferable that the lead wiring Ldrawn be formed in multiple layers in the region where the additional circuit 148 is disposed.

  In the mechanism of the first embodiment, as can be understood from FIGS. 6 to 6B, the lead-out wiring Ldrawn of each scanning line Lscan drawn from the pixel array section 102 to the outer peripheral portion is the first wiring layer L1 and the second wiring layer. L2 and is electrically connected by contacts LC at the end on the signal input portion side in the longitudinal direction, both ends of the additional circuit 148 region (referred to as additional circuit region), and the end on the pixel array portion 102 side. Connected. Therefore, in the portion excluding the additional circuit region in the longitudinal direction of the lead wiring Ldrawn, that is, between the signal input portion and the additional circuit region or between the additional circuit region and the pixel array portion 102, the first lead wiring Ldrawn_L1 and the second lead wiring Ldrawn_L1 Even if one of the lead lines Ldrawn_L2 is disconnected, the other wiring layer is connected, so that the electrical connection is maintained as a whole, so that the connection between the signal input unit and the pixel array unit 102 is not performed. Connection can be prevented.

<About microcrystalline silicon TFT>
FIG. 7 is a schematic cross-sectional view of a microcrystalline silicon TFT. When forming the microcrystalline silicon TFT, first, a gate electrode forming film is formed on the first wiring layer L1 on the glass substrate. At this time, in this embodiment, the lead-out wiring Ldrawn for the scanning line Lscan is also formed. As the gate electrode formation film, a molybdenum film is formed to a thickness of 90 nm by sputtering, for example. Next, through a photolithography process and an etching process, the gate electrode formation film is patterned into a predetermined shape to produce a gate electrode and an extraction wiring Ldrawn.

  Next, an interlayer insulating film 502a (gate insulating film) is formed on the substrate so as to cover the gate electrode and the lead wiring Ldrawn. The interlayer insulating film 502a is formed of, for example, a laminated film of a silicon nitride film (film thickness is 50 nm, for example) and a silicon oxide film (film thickness is 120 nm, for example). Further, as a film for forming a channel layer in the interlayer insulating film 502a, an amorphous silicon film is formed to a thickness of, for example, 15 nm by, for example, plasma enhancement-chemical vapor deposition (PE-CVD).

  Next, a silicon oxide film is formed on the amorphous silicon film to a thickness of, for example, 20 nm to form a buffer film. Next, molybdenum is deposited to a thickness of, for example, 100 nm on the buffer film by, for example, PE-CVD or sputtering to form a light-heat conversion film. The buffer film plays a role of preventing molybdenum silicide from being generated by diffusion of molybdenum (Mo) of the light-to-heat conversion film, which becomes a high temperature when irradiated with laser light, into the amorphous silicon film.

  Next, the light-heat conversion film is irradiated with laser light to heat the light-heat conversion film, and the amorphous silicon film in the lower layer is changed to a microcrystalline silicon film by this heat. The laser light source used in the laser annealing process at this time is, for example, a broad area type high-power semiconductor laser device having a wavelength of 808 nm, and a light output (continuous laser light) of about 4 W is obtained by continuous oscillation. Laser light emitted from a semiconductor laser device is passed through a uniform illumination optical system using a microlens array, etc., and the light intensity profile on the long axis side is a flat top hat type, and the light intensity profile on the short axis side is a Gaussian type. The beam is shaped into a rectangular beam, the beam is condensed to a light intensity of about 2 mW / μm ^ 2, irradiated onto the light-heat conversion film, and the substrate is moved at a constant speed of about 40 mm / s. The molybdenum film is heated to a high temperature by irradiation with high-intensity semiconductor laser light, and this heat is transferred to the underlying buffer oxide film and amorphous silicon film by thermal conduction, and the amorphous silicon film reaches the melting point. . The melted amorphous silicon film is cooled and solidified as the irradiation light passes through to be changed into microcrystalline silicon, and a microcrystalline silicon film is formed.

  Next, the light-to-heat conversion film and the buffer film that are unnecessary for forming the transistor are removed. Next, if necessary, an amorphous silicon film is formed on the microcrystalline silicon film to a thickness of, for example, 120 nm by, for example, a PE-CVD method. Thus, a channel layer having a two-layer channel structure including a microcrystalline silicon film and an amorphous silicon film is manufactured.

  Next, the same process as that of a general amorphous silicon TFT is performed. For example, a channel protective film is formed on the amorphous silicon film by, for example, a chemical vapor deposition method, for example, using a silicon nitride film. Thereafter, a stopper layer is formed on the channel layer using a channel protective film by a normal photolithography process and etching process. Further, an amorphous silicon layer (n + a-Si layer) doped with, for example, phosphorus as an n-type impurity is formed in the region where the source / drain is formed on the amorphous silicon film, for example, by chemical vapor deposition. To do. Thereafter, an island structure is formed by a photolithography process and a dry etching process using a reactive ion etching apparatus.

  Next, to cover the n + a-Si layer, for example, by sputtering, the second wiring layer L2 is made of aluminum Al, titanium Ti, or an alloy material thereof (Ti-Al-Ti, etc.) having a lower resistance than molybdenum Mo. ) To form an electrode film for forming the source and drain electrodes and the second lead wiring Ldrawn_L2. Further, the source film, the drain electrode, and the second extraction wiring Ldrawn_L2 are formed by patterning the electrode film by a photolithography process and a dry etching process using, for example, a reactive ion etching apparatus.

  Through the above-described steps, the inverted staggered thin film transistor 1 is formed in which the channel layer has a two-layer structure of a microcrystalline silicon film and an amorphous silicon film.

  Here, when the channel layer of the microcrystalline silicon TFT having the bottom gate structure according to the present embodiment is formed, the first wiring layer L1 includes not only the gate electrode but also the first lead wiring Ldrawn_L1. Is laid out over the entire surface of the panel, and in the process of irradiating high-power continuous laser light to change the amorphous silicon film to the microcrystalline silicon film, the thermal profile of the entire panel is This is more uniform than when the wiring Ldrawn_L1 does not exist, and the variation in TFT characteristics is suppressed.

  Not only microcrystalline silicon TFTs, but also other thin film transistors, when annealing is performed with laser light (for example, a solid laser), non-uniformity in the thermal profile can be a problem. The problem is small as compared with the crystalline silicon TFT, and in particular, the effect of making one wiring layer of the lead wiring Ldrawn into the first wiring layer L1 in the microcrystalline silicon TFT is high.

<< Improvement Method: Second Embodiment >>
FIG. 8 and FIG. 8A are diagrams for explaining a second embodiment of the wiring arrangement (layout) that can prevent the display defect caused by the disconnection of the lead wiring Ldrawn. Here, FIG. 8 is a perspective plan view for explaining the positional relationship between the auxiliary wiring 515 and each scanning line Lscan in the second embodiment. FIG. 8A is a plan perspective view (1) and a cross-sectional view (2) focusing on the transistor of the additional circuit 148 (particularly the protection circuit 142) in the longitudinal direction (bb ′ line) of the scanning line Lscan in FIG. The sectional view in the direction (aa ′ line) orthogonal to the longitudinal direction of the scanning line Lscan in FIG. 8 is omitted, but is the same as in the first embodiment.

  The second embodiment is another example of a layout in the case where an additional circuit 148 (protection circuit 142 or test switch circuit 144) is provided between the pad or control unit 109 and the pixel array unit 102. In the second embodiment, as a difference from the first embodiment, the first wiring layer L1 and the second wiring layer L2 are also provided in the region where the additional circuit 148 is disposed in the longitudinal direction of the lead wiring Ldrawn. It is characterized in that the lead wiring Ldrawn is arranged.

  In the mechanism of the second embodiment, as can be understood from FIG. 8 and FIG. 8A, the lead-out wiring Ldrawn of each scanning line Lscan drawn from the pixel array unit 102 to the outer peripheral part is the first wiring layer L1 and the second wiring layer. L2 is electrically connected to each other on the signal input part side and the pixel array part 102 side in the longitudinal direction by a contact LC. For this reason, even if the first wiring Ldrawn_L1 and the second wiring Ldrawn_L2 are disconnected in the portion including the additional circuit region in the longitudinal direction of the drawing wiring Ldrawn, that is, in the entire range in the longitudinal direction, the other wiring Since the layers are connected, the electrical connection as a whole is maintained, so that the unconnected state between the signal input unit and the pixel array unit 102 can be prevented.

<< Improvement Method: Third Embodiment >>
FIGS. 9 to 9B are diagrams for explaining a third embodiment of the wiring arrangement (layout) that can prevent display defects caused by disconnection of the lead wiring Ldrawn. Here, FIG. 9 is a diagram for explaining a mounting mode around the pixel array unit 102 in the third embodiment. FIG. 9A is a perspective plan view illustrating the positional relationship between the auxiliary wiring 515 and each scanning line Lscan in the third embodiment. FIG. 9B is a cross-sectional view in the longitudinal direction (bb ′ line) of the scanning line Lscan in FIG. 9A. The sectional view in the direction (aa ′ line) orthogonal to the longitudinal direction of the scanning line Lscan in FIG. 9A is omitted, but is the same as in the first embodiment.

  As is apparent from FIGS. 9 to 9B, the third embodiment is an example in which the additional circuit 148 is not provided between the signal input unit side and the pixel array unit 102 side in the longitudinal direction of the lead wiring Ldrawn. Since the additional circuit 148 does not exist, the length of the lead-out wiring Ldrawn can be shortened.

  In the mechanism of the third embodiment, as can be understood from FIGS. 9A and 9B, the lead-out wiring Ldrawn of each scanning line Lscan drawn from the pixel array section 102 to the outer peripheral portion is the first wiring layer L1 and the second wiring layer. L2 is electrically connected to each other on the signal input part side and the pixel array part 102 side in the longitudinal direction by a contact LC. For this reason, in the entire range in the longitudinal direction of the lead wiring Ldrawn, even if one of the first lead wiring Ldrawn_L1 and the second lead wiring Ldrawn_L2 is disconnected, the other wiring layer is connected. Therefore, the non-connection between the signal input unit and the pixel array unit 102 can be prevented.

1 is a block diagram (COG mounting configuration) showing an outline of a configuration of an active matrix display device which is an embodiment of a display device according to the present invention. 1 is a block diagram (outside peripheral circuit panel arrangement configuration) showing an outline of the configuration of an active matrix display device which is an embodiment of a display device according to the present invention. FIG. It is a figure which shows one Embodiment of the organic EL display apparatus provided with the pixel circuit of the basic composition of this embodiment, and the said pixel circuit. FIG. 3 is a timing chart showing an example of drive timing related to the pixel circuit of the present embodiment shown in FIG. 2. FIG. It is the whole schematic diagram which showed the layout of the 1st comparative example of the lower electrode and auxiliary wiring of an organic EL element. It is the figure which showed the layout of the 2nd comparative example which is a modification with respect to FIG. It is a figure explaining the example of mounting in the case of the arrangement configuration outside a peripheral circuit panel shown to FIG. 1A. It is a figure explaining the detail of TCP mounting in the case of the peripheral circuit panel outside arrangement | positioning structure shown to FIG. 1A. It is a plane perspective view explaining the arrangement relationship between the auxiliary wiring and each scanning line in the comparative example. 6 is a cross-sectional view (1) in a direction (a-a ′ line) orthogonal to the longitudinal direction of the scanning line in FIG. 5 and a cross-sectional view (2) in the longitudinal direction (b-b ′ line) of the scanning line Lscan. FIG. 6 is a layout example (plan view) of a portion where the lead-out wiring is connected to the pixel array portion in the outer peripheral portion of the pixel array portion. It is a top view of the outline of Drawing 5B. It is an enlarged view of the dotted line part in FIG. 5C. It is a figure explaining the detail of the intersection of a 1st wiring layer and a 2nd wiring layer. It is a layout example (plan view) in a state where a protection circuit and a test switch circuit are provided on the outer periphery of the pixel array unit. It is a figure which shows the outline | summary of a protection circuit. It is a figure which shows the outline | summary of a test switch circuit. FIG. 3 is a perspective plan view illustrating an arrangement relationship between auxiliary wirings and scanning lines in the first embodiment. It is sectional drawing of the direction (a-a 'line) orthogonal to the longitudinal direction of the scanning line in FIG. FIG. 7 is a plan perspective view (1) and a cross-sectional view (2) focusing on the transistor of the protection circuit in the longitudinal direction (b-b ′ line) of the scanning line in FIG. 6. It is a cross-sectional schematic diagram of a microcrystalline silicon TFT. It is a plane perspective view explaining the arrangement relationship between the auxiliary wiring and each scanning line in the second embodiment. FIG. 9 is a plan perspective view (1) and a cross-sectional view (2) focusing on the transistor of the protection circuit in the longitudinal direction (b-b ′ line) of the scanning line in FIG. 8. It is a figure explaining the mounting aspect of the pixel array part periphery in 3rd Embodiment. It is a plane perspective view explaining the arrangement relationship between the auxiliary wiring and each scanning line in the third embodiment. It is sectional drawing of the longitudinal direction (b-b 'line) of the scanning line in FIG. 9A.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 100 ... Display panel part, 101 ... Board | substrate, 102 ... Pixel array part, 103 ... Vertical drive part, 104 ... Write scanning part, 104WS ... Write scanning line, 105 ... Drive scanning part, 105DSL ... Power supply Supply line 106 ... Horizontal drive unit 106HS ... Video signal line 109 ... Control unit 120 ... Retention capacitor 121 ... Drive transistor 125 ... Sampling transistor 127 ... Organic EL element 140 ... Peripheral circuit unit 142 ... Protection Circuit: 144: Test switch circuit, 148: Additional circuit, 200: Drive signal generation unit, 220: Video signal processing unit, 504: Lower electrode (anode electrode), 506: Organic layer, 508: Upper electrode (cathode electrode), 515 ... auxiliary wiring, LC ... contact, Lscan ... scanning line, Ldrawn, Ldrawn_L1, Ldrawn_L2 ... lead-out wiring

Claims (4)

A pixel circuit including an electro-optical element that performs display according to the signal amplitude, and a pixel array unit in which scanning lines are arranged in a matrix;
A lead-out line that is a line that is led out from each scanning line of the pixel array section to the peripheral circuit side and transmits various signals for driving the pixel circuit;
Equipped with a,
The lead-out wiring is formed by a first wiring layer made of molybdenum and a second wiring layer made of a metal material having a lower resistance than molybdenum and disposed next to the first wiring layer ,
Contacts for making electrical connection between the first wiring layer and the second wiring layer in the portion of the lead wiring are formed in at least two places in the longitudinal direction of the lead wiring ,
The transistor constituting the peripheral circuit is a bottom-gate transistor in which a gate electrode is disposed on the substrate side,
A gate electrode of the transistor is formed by the first wiring layer;
The source electrode and the drain electrode of the transistor are formed by the second wiring layer,
The display device in which the semiconductor layer of the transistor is formed by subjecting an amorphous silicon film to an annealing process, and the second wiring layer is formed after the annealing process . The display device according to claim 1, wherein the second wiring layer is made of aluminum, titanium, or an alloy material thereof. The display device according to claim 1, wherein the semiconductor layer is made of microcrystalline silicon. The display device according to claim 1, wherein the annealing process is a laser annealing process.

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