JP2009175389A - Display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent harmful effects caused by overlapping with scanning lines from peripheral circuit parts, regarding an organic EL display where an auxiliary wiring connected to a cathode electrode is formed in an anode layer so as to surround a pixel array section. <P>SOLUTION: A slit portion 515a is formed in the auxiliary wiring 515 above the scanning line (Lscan) of a second wiring layer L2, then, a parasitic capacity (Cscan) is reduced, and the wiring delay is reduced. Accordingly, a signal writing speed is increased, shading is prevented, and then, high image quality is obtained. Consequently, a high-definition, high image quality panel is obtained. By forming the slit portion 515a, an interlayer short with the scanning line (Lscan) due to a foreign substance is prevented, then, the yield is improved. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  In the present invention, pixel circuits (also referred to as pixels) each including a current-driven electro-optical element (also referred to as a display element or a light-emitting element) whose luminance changes depending on the magnitude of a driving signal are arranged in a matrix. The present invention relates to an active matrix display device that includes a display panel portion having a pixel array portion as a main portion, has an active element for each pixel circuit, and performs display driving in units of pixels by the active element.

  In recent years, in the field of display devices, panel-type display devices have become mainstream in place of conventional CRT (Cathode Ray Tube) display devices because they have features such as thinness, light weight, and high definition.

  Among panel-type display devices, there is a display device that uses an electro-optical element whose luminance changes depending on an applied voltage or a flowing current as a display element of a pixel. For example, a liquid crystal display element is a typical example of a voltage-driven electro-optic element whose luminance changes depending on an applied voltage, and an organic electroluminescence ( Organic electro luminescence, organic EL, organic light emitting diode, OLED (hereinafter referred to as organic EL) element is a typical example. The organic EL display device using the latter organic EL element is a so-called self-luminous display device using an electro-optic element which is a self-luminous element as a pixel display element.

  In a panel type display device, a pixel array unit in which elements constituting a pixel circuit such as a TFT or an electro-optical element are arranged in a matrix, a scanning line arranged around the pixel array unit and driving each pixel, and A control unit mainly including a connected scanning unit (horizontal drive unit or vertical drive unit), and a drive signal generation unit and a video signal processing unit that generate various signals for operating the control unit. In general, the entire apparatus is constructed. A scanning circuit in which a scanning line, a power supply line, and the like are extended between the pixel array unit and a scanning circuit other than the pixel array unit, and a power supply voltage and a signal are input to a thin film transistor and an electro-optical element that form the pixel circuit. The form which supplies a signal from is taken.

  At this time, various methods have been considered for arranging circuits other than the pixel array section. As an example, circuits other than the pixel array section are arranged outside the panel, and the panel edge section is arranged. A scanning line (for example, a writing scanning line, a power supply line, and a video signal line) is extended to the terminal area of the pixel, and a power supply voltage and a signal are supplied from a scanning circuit or a power supply circuit to a thin film transistor or an electro-optical element constituting the pixel circuit. May be adopted (see Patent Document 1).

Japanese Patent Laid-Open No. 2007-041561

  Here, the current-driven electro-optical element has a laminated structure sandwiched between a light emitting layer and two electrodes (referred to as a lower electrode and an upper electrode). For example, an organic EL element has an organic thin film (organic layer) formed by laminating an organic hole transport layer or an organic light emitting layer between a lower electrode and an upper electrode, and emits light when an electric field is applied to the organic thin film. The color gradation is obtained by controlling the current value flowing through the organic EL element. Display is performed by extracting light from one electrode (upper electrode) side.

  For this reason, the upper electrode on the light transmitting side (referred to as the display surface side) needs to be light transmissive, and the electrode resistance tends to increase. As a mechanism for alleviating this problem, a mechanism is considered in which auxiliary wiring is provided in the same layer as the other lower electrode layer (see Patent Document 2).

JP 2004-207217 A

  In the mechanism described in Patent Document 2, auxiliary wiring is formed in a lattice shape so as to surround pixel circuits arranged in a two-dimensional matrix in the pixel array portion, and further, auxiliary wiring is provided so as to surround the outer periphery of the pixel array portion. Forming. The contact resistance is lowered by establishing electrical connection with the upper electrode over the entire outer periphery.

  However, as in the mechanism described in Patent Document 2, if the auxiliary wiring and the upper electrode are electrically connected to the entire outer periphery of the pixel array portion, the connection to the circuit outside the pixel array portion is prevented. The scanning line to be taken overlaps with the auxiliary wiring on the outer peripheral portion of the pixel array portion, and a relatively large parasitic capacitance is formed. For this reason, the pulse signal becomes dull, the effective pulse width is shortened, a timing shift occurs, and the image quality is deteriorated. In addition, since the auxiliary wiring and the scanning line (for example, the writing scanning line, the power supply line, and the video signal line) overlap in a wide range, the interlayer short circuit through the foreign matter frequently occurs, resulting in a decrease in yield.

  The present invention has been made in view of the above circumstances, and prevents adverse effects caused by overlapping of scanning lines that supply signals to each pixel circuit of the pixel array unit with auxiliary wirings on the outer periphery of the pixel array unit. The purpose is to provide a mechanism that can do this.

  One embodiment of the display device according to the present invention transmits a pixel array unit in which pixel circuits including electro-optic elements that perform display according to signal amplitude are arranged in a matrix and various signals for driving the pixel circuits. A pixel array in the same layer as the layer on which the first electrode on the side opposite to the display surface side of the electro-optic element is disposed. Auxiliary wiring is formed so as to surround the periphery of the portion, and the auxiliary wiring is electrically connected to the second electrode on the display surface side of the electro-optic element around the pixel array portion. In the peripheral portion, an opening is formed on the upper layer side of the scanning line of the auxiliary wiring.

  In short, when the scanning line and the auxiliary wiring are formed so as to overlap each other in the peripheral portion of the pixel array section, it is said that an opening is formed in the auxiliary wiring on the upper layer side of the scanning line. That is. If an opening is formed in the auxiliary wiring on the upper layer side of the scanning line, the opening does not overlap.

  According to one embodiment of the present invention, the opening is formed in the auxiliary wiring on the upper layer side of the scanning line, so that the opening does not overlap and the parasitic capacitance is reduced accordingly. As a result, the phenomenon that the pulse signal becomes dull can be alleviated and timing deviation can be prevented, so that image quality deterioration can be prevented. In addition, since the overlap between the auxiliary wiring and the scanning line is reduced, the interlayer short circuit through the foreign matter is also reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Overview of display device>
1 and 1A are block diagrams showing an outline of the configuration of an active matrix display device which is an embodiment of a display device according to the present invention. Here, FIG. 1 shows a case of a COG mounting configuration in which a semiconductor chip for a control unit is directly mounted on a glass substrate on which a pixel array unit is mounted by COG mounting technology (details will be described later), and FIG. 1A shows a display panel. The pixel array portion is mounted on the part, and the peripheral circuit panel outside arrangement configuration in which the control unit is mounted on another substrate (for example, a flexible substrate) is shown.

  In the configuration example shown here, for example, an organic EL element that is a current-driven element is used as a display element (electro-optical element, light-emitting element) of a pixel, and a thin film transistor (TFT) is used as an active element. A case where the present invention is applied to an active matrix type organic EL display (hereinafter referred to as “organic EL display device”) in which an organic EL element is formed on a semiconductor substrate on which the substrate is formed will be described as an example.

  The thin film transistors can be broadly classified into, for example, an amorphous silicon TFT made of amorphous silicon, a microcrystalline silicon TFT made of microcrystalline silicon (nanocrystalline silicon), a multi-layer, depending on the type of semiconductor constituting the channel layer which is an active region. There are low-temperature polysilicon TFTs (non-alkali glass substrates) or high-temperature polysilicon TFTs (quartz glass substrates) made of crystalline silicon, and a mechanism for making the channel layer into a two-layer structure by combining these is also considered (reference) References 1-4). Depending on the type, for example, there are differences in element characteristics such as threshold voltage Vth, mobility μ, element variation, and stability over time. In this embodiment, the pixel array unit 102 and all its peripheral parts As the semiconductor composing the channel layer, a microcrystalline silicon TFT having relatively good variation in threshold voltage Vth (in-plane uniformity) and stability over time, and higher mobility than an amorphous silicon TFT can be used. An example of application will be described.

Reference 1: Japanese Patent Application Laid-Open No. 10-242052 Reference 2: Japanese Patent Application Laid-Open No. 2007-5508 Reference 3: Japanese Patent Application Laid-Open No. 2007-35964 Reference 4: “Takaki Umehiro” From manufacturing process to next generation TFT- ", first edition, Japan, Industrial Research Committee, October 25, 2007, especially p74-88

  The display device 1 is a mobile terminal device such as a portable music player, a digital camera, a notebook personal computer, or a mobile phone using various electronic devices, for example, a recording medium such as a semiconductor memory, a mini disk (MD), or a cassette tape. In addition, video signals input to electronic devices such as video cameras and video signals generated in the electronic devices can be used in display units of electronic devices in various fields that display still images and moving images (videos).

  In the following description of the overall configuration, an organic EL element is specifically described as an example of a pixel display element. However, this is merely an example, and the target display element is not limited to an organic EL element. In general, all the embodiments described later can be applied to all electro-optical elements that emit light by current drive, and not only current drive but also all electro-optical elements that emit light by voltage drive. The embodiments of the present invention can be similarly applied.

  As shown in FIGS. 1 and 1A, a display device 1 has an aspect ratio in which a pixel circuit (also referred to as a pixel) P having an organic EL element (not shown) as a plurality of display elements is a display aspect ratio. Display panel unit 100 having a pixel array unit 102 arranged to form an effective video area of X: Y (for example, 9:16) as a main part, and various pulse signals for driving and controlling the display panel unit 100 A drive signal generation unit (so-called timing generator) 200 that is an example of a panel control unit that emits a video signal and a video signal processing unit 220 are provided. The drive signal generation unit 200 and the video signal processing unit 220 are built in a one-chip IC (Integrated Circuit), and are arranged outside the display panel unit 100 in this example.

  In the case of the COG mounting configuration shown in FIG. 1, the display panel unit 100 includes a pixel array unit 102 in which pixel circuits P are arranged in a matrix of n rows × m columns on a substrate 101. A vertical drive unit 103 that scans the pixel circuit P in the vertical direction and a horizontal drive unit 106 (also referred to as a horizontal selector or a data line drive unit) that scans the pixel circuit P in the horizontal direction are mounted by COG mounting technology, and for external connection The terminal portion (pad portion) 108 is disposed at the end of one side of the display panel portion 100. If necessary, an interface (IF) unit that interfaces each of the drive units 103 and 106 with an external circuit may be mounted by a COG mounting technique.

  The vertical drive unit 103 includes, for example, a write scan unit (write scanner WS; Write Scan) 104 and a drive scan unit (drive scanner DS; Drive Scan) 105 that functions as a power supply scanner having power supply capability. For example, the pixel array unit 102 is driven by the writing scanning unit 104 and the driving scanning unit 105 from one side or both sides in the horizontal direction shown in the figure, and driven by the horizontal driving unit 106 from one side or both sides in the vertical direction shown in the figure. It has come to be.

  The vertical driving unit 103 (the writing scanning unit 104 and the driving scanning unit 105) and the horizontal driving unit 106 control writing of the signal potential to the holding capacitor, threshold correction operation, mobility correction operation, and bootstrap operation. The control unit 109 is configured to function as a drive circuit that drives the pixel circuit P of the pixel array unit 102. The control unit 109 is a signal supply circuit that supplies a signal to the pixel circuit P of the pixel array unit 102.

  The configuration of the illustrated vertical drive unit 103 and the corresponding scanning line is shown in conformity with the case where the pixel circuit P has a 2TR configuration of the present embodiment described later. However, depending on the configuration of the pixel circuit P, other configurations may be used. A scanning unit and a scanning line may be provided.

  Further, a protection circuit 142 and a test switch circuit 144 can be mounted on the display panel unit 100 as an example of the peripheral circuit unit 140 for each of the vertical driving unit 103 and the horizontal driving unit 106. As the protection circuit 142, a protection circuit 142V for the vertical drive unit 103 and a protection circuit 142H for the horizontal drive unit 106 are provided for each scanning line, and as the test switch circuit 144, a test switch circuit 144V for the vertical drive unit 103 is provided. A test switch circuit 144H for the horizontal driving unit 106 is provided for each scanning line.

  The protection circuits 142V and 140H and the test switch circuits 144V and 142H are not formed by the COG mounting technology, but by a mechanism (TFT integrated configuration) that simultaneously generates each TFT in the process of generating the TFT of the pixel array unit 102. Yes. In the present embodiment, it is not essential to provide the protection circuits 142V (for the vertical drive unit 103) and 140H (for the horizontal drive unit 106) because of the relationship with the invention.

  Here, the significance of providing the protection circuit 142 and the test switch circuit 144 as additional circuits will be described as follows. First, as a product form, the display panel unit 100 in which the pixel array unit 102 and the control unit 109 are mounted on the same glass substrate, the drive signal generation unit 200, and the video signal processing unit 220 are separated (on the panel). The display panel unit 100 is mounted with a pixel array unit 102, and the control unit 109, the drive signal generation unit 200, the video signal processing unit 220, and the like are on a separate substrate (for example, a flexible substrate). A configuration in which a circuit is mounted (referred to as a peripheral circuit panel outside arrangement configuration) can be considered.

  Further, in the case where the pixel array unit 102 and the control unit 109 are mounted on the same glass substrate (substrate 101) and the display panel unit 100 is configured to be disposed on the panel, the process of generating the TFT of the pixel array unit 102 is performed. At the same time, the pixel is generated by a mechanism (referred to as a TFT integrated configuration) for generating each TFT for the control unit 109 (and the drive signal generation unit 200 and the video signal processing unit 220 as necessary) and COG (Chip On Glass) mounting technology. A mechanism (referred to as a COG mounting configuration) in which a semiconductor chip for the control unit 109 (and the drive signal generation unit 200 and the video signal processing unit 220 as necessary) is directly mounted on the substrate 101 on which the array unit 102 is mounted is considered. It is done.

  In the configuration outside the peripheral circuit panel and the COG mounting configuration (also collectively referred to as a control unit retrofit configuration), there is a point in time when the pixel array unit 102 and the control unit 109 are separate. Since the image display cannot be performed unless the pixel array unit 102 and the control unit 109 are connected, a defect of each pixel in the pixel array unit 102 (TFT short circuit or open) or a scan line defect (disconnection or adjacent scanning). Inspection such as contact with wire) cannot be performed.

  For this reason, when the control unit retrofit configuration is adopted, the purpose is to inspect each pixel and scanning line of the pixel array unit 102 in the peripheral portion of the pixel array unit 102 without connecting the control unit 109 to the pixel array unit 102. As a result, a test switch circuit 144 that can supply a test signal to each scanning line from the outside of the pixel array unit 102 is provided to perform a simple lighting test.

  Although various configurations are conceivable as the test switch circuit 144, for example, a mechanism in which the protection circuit 142 for electrostatic protection and the test switch circuit 144 are configured with different circuit elements, and a test signal is sent to the circuit element of the protection circuit 142. A mechanism of a protection & test switch circuit that is also used as a switch element constituting the test switch circuit 144 to be supplied to the scanning line can be considered (details will be described later). In the retrofitted configuration of the control unit, the protection circuit 142 has a point in time when the pixel array unit 102 and the control unit 109 are separated from each other. Since there is a greater possibility that static electricity will be applied via manufacturing equipment, etc. and the circuit elements will be destroyed than in the case of a TFT integrated configuration, each scanning line is provided for the purpose of protecting the circuit elements from static electricity damage due to static electricity. It is.

  Thus, in the mounted state, peripheral drive circuits such as the vertical drive unit 103, the horizontal drive unit 106, the protection circuits 142V and 140H, and the test switch circuits 144V and 142H are mounted on the same substrate 101 as the pixel array unit 102. It becomes the composition. In the illustrated example, the writing scanning unit 104, the driving scanning unit 105, and the horizontal driving unit 106 constituting the control unit 109 are configured by semiconductor chips and mounted on the display panel unit 100 by COG mounting technology. In order to clarify this also from the drawing, the control unit 109 (the writing scanning unit 104, the driving scanning unit 105, and the horizontal driving unit 106) is indicated by a dotted line. In addition, an electrical connection terminal PAD1 (Contact Pad) for connecting to the wiring on the display panel unit 100 when the COG is mounted is schematically shown.

  As a method of mounting an IC chip (IC: Integrated Circuit) such as the control unit 109 on the display panel unit 100 by the COG mounting technique, for example, a gold bump by electrolytic plating is used for an electrical connection terminal (bump), and the display panel A method of mounting on an electrode on the unit 100 by an ACF (Anisotropic Conductive Film) is known. Of course, other methods may be applied.

  As the protection circuits 142V and 140H and the test switch circuits 144V and 142H, for example, a mechanism in which the electrostatic protection circuit and the test switch circuit are constituted by different circuit elements may be adopted, or the circuit elements of the electrostatic protection circuit may be tested. You may employ | adopt the mechanism used as the protection & test switch circuit made to serve as a switch element which comprises the test switch circuit which supplies a signal to a scanning line.

  In the example shown in FIG. 1, the pulse signal is input from the outside of the display panel unit 100 via the terminal unit 108. However, the drive signal generation unit 200 that generates these various timing pulses is configured by a semiconductor chip. It can also be mounted on the display panel unit 100 by COG mounting technology.

  Various pulse signals are supplied to the terminal unit 108 from the drive signal generation unit 200 arranged outside the display device 1. Similarly, the video signal Vsig is supplied from the video signal processing unit 220. In the case of color display compatibility, video signals Vsig_R, G, and B for each color (in this example, three primary colors of R (red), G (green), and B (blue)) are supplied.

  For example, as a pulse signal for vertical driving, shift start pulses SPDS and SPWS which are examples of vertical write start pulses and vertical scanning clocks CKDS and CKWS (vertical scanning clocks xCKDS and xCKWS whose phases are reversed as necessary) ) And other necessary pulse signals are supplied. In addition, as a pulse signal for horizontal driving, necessary pulse signals such as a horizontal start pulse SPH, which is an example of a horizontal write start pulse, and a horizontal scanning clock CKH (and a horizontal scanning clock xCKH whose phase is inverted as necessary) are supplied. Is done.

  Each terminal of the terminal unit 108 is connected to the vertical driving unit 103 and the horizontal driving unit 106 via a signal line 199. For example, each pulse supplied to the terminal unit 108 is internally adjusted to a voltage level by a level shifter unit (not shown) as necessary, and then supplied to each unit of the vertical driving unit 103 and the horizontal driving unit 106 via a buffer. Supplied.

  Although the pixel array unit 102 is not shown in the drawing (details will be described later), pixel circuits P in which pixel transistors are provided with respect to an organic EL element as a display element are two-dimensionally arranged in a matrix form. On the other hand, scanning lines are wired for each row, and signal lines are wired for each column.

  For example, in the pixel array unit 102, the scanning lines 104WS and 105DSL on the vertical scanning side and video signal lines (data lines) 106HS which are scanning lines on the horizontal scanning side are formed in the pixel array unit 102. An organic EL element (not shown) and a thin film transistor for driving the organic EL element are omitted at the intersection between the vertical scanning lines and the horizontal scanning lines. A pixel circuit P is configured by a combination of an organic EL element and a thin film transistor.

  Specifically, for each pixel circuit P arranged in a matrix, the write scanning lines 104WS_1 to 104WS_n for n rows driven by the write scanning unit 104 with the write drive pulse WS and the drive scanning unit Power supply lines 105DSL_1 to 105DSL_n for n rows driven by the power supply drive pulse DSL by 105 are wired for each pixel row.

  The writing scanning unit 104 and the driving scanning unit 105 are configured by combinations of logic gates (including latches and shift registers), and select each pixel circuit P of the pixel array unit 102 in units of rows, that is, drive signal generation Each pixel circuit P is sequentially selected through the write scanning line 104WS and the power supply line 105DSL based on the vertical drive system pulse signal supplied from the unit 200.

  The horizontal drive unit 106 is configured by a combination of logic gates (including latches and shift registers), and selects each pixel circuit P of the pixel array unit 102 in units of columns, that is, supplied from the drive signal generation unit 200. Based on the pulse signal of the horizontal drive system, a predetermined potential in the video signal Vsig is sampled and written to the storage capacitor via the video signal line 106HS for the selected pixel circuit P.

  The display device 1 of the present embodiment is capable of line-sequential driving or dot-sequential driving, and the writing scanning unit 104 and the driving scanning unit 105 of the vertical driving unit 103 are pixels in line sequential (that is, in units of rows). The array unit 102 is scanned, and in synchronization with this, the horizontal drive unit 106 outputs the image signal for one horizontal line simultaneously (in the case of line sequential) or in units of pixels (in the case of dot sequential). Write to 102.

  As shown in the figure, the product form is provided as a display device 1 in the form of a module (composite part) including all of the display panel unit 100, the drive signal generation unit 200, and the video signal processing unit 220. For example, the display device can be provided only by the display panel unit 100, or the display device can be provided only by the pixel array unit 102.

  For example, the display device 1 includes a module-shaped one having a sealed configuration. For example, as shown in FIG. 1A, this corresponds to a case where the peripheral circuit panel is arranged outside. In this case, the pixel array unit 102 is configured as a display module including only the display panel unit 100 that is formed by being attached to an opposing unit such as transparent glass. The transparent facing portion is provided with a display layer (in this example, an organic layer and electrode layers on both sides thereof), a color filter, a protective film, a light shielding film, and the like.

  In the case of the arrangement outside the peripheral circuit panel (display module) shown in FIG. 1A, in addition to the pixel array unit 102, a circuit unit for inputting and outputting a video signal Vsig and various drive pulses to the pixel array unit 102 from the outside. TCP (Tape Carrier Package) method and COF (Chip On Flexible) method with FPC (flexible printed circuit) equipped with (equivalent to vertical driving unit 103 and horizontal driving unit 106 and its output driver). An electrical connection terminal PAD2 serving as an external connection terminal for connection is provided on the edge of the display panel unit 100. TCP is a name for a flexible tape in which a driver LSI (Large Scale Integrated Circuit) is mounted by bonding, and the method is usually TAB (Tape Automated Bonding). Incidentally, although FIG. 1A shows an example of the COF method, an example of the TCP method is shown in FIGS. 3 and 3A described later. Other points are basically the same as those in the COG mounting configuration.

  In FIGS. 1 and 1A, each element of the vertical driving unit 103 (the writing scanning unit 104 and the driving scanning unit 105), the protection circuit 142V, and the test switch circuit 144V are arranged only on one side of the pixel array unit 102. Although shown, it is also possible to adopt a configuration in which these are arranged on both the left and right sides with the pixel array unit 102 interposed therebetween. Similarly, FIG. 1 and FIG. 1A show a configuration in which the horizontal driving unit 106, the protection circuit 142H, and the test switch circuit 144H are arranged only on one side of the pixel array unit 102. It is also possible to adopt a configuration in which they are arranged on both the upper and lower sides.

  Further, regarding the mounting form of the control unit 109, FIG. 1 shows the case of a COG mounting configuration as an example of the on-panel arrangement configuration, and FIG. 1A shows the case of the arrangement configuration outside the peripheral circuit panel. The upper arrangement configuration is not limited to the COG mounting configuration but may be a TFT integrated configuration. In this case, since the TFT constituting the control unit 109 is manufactured integrally with the TFT constituting each pixel circuit P of the pixel array unit 102, the protection circuit 142 and the test switch circuit 144 are basically unnecessary. Instead, the control unit 109 may be handled as the peripheral circuit unit 140 and an embodiment described later may be applied.

<Pixel circuit>
FIG. 2 is a diagram showing an embodiment of a pixel circuit P having a basic configuration of the present embodiment and an organic EL display device including the pixel circuit P. The display device 1 including the pixel circuit P having the basic configuration of the present embodiment in the pixel array unit 102 is referred to as a display device 1 having the basic configuration of the present embodiment. In addition, the vertical driving unit 103, the horizontal driving unit 106, the protection circuits 142V and 140H, and the test switch circuits 144V and 142H arranged on the periphery of the pixel array unit 102 on the substrate 101 of the display panel unit 100 are also shown. Yes. In order to indicate that there is a point in time when the control unit 109 is separate from the pixel array unit 102 in the peripheral circuit panel external arrangement configuration or COG mounting configuration (also collectively referred to as a control unit retrofit configuration), the control unit 109 (write The scanning unit 104, the driving scanning unit 105, and the horizontal driving unit 106) are indicated by dotted lines.

  Here, as described above, the protection circuits 142V and 140H are provided for each scanning line for all of the write scanning line 104WS, the power supply line 105DSL, and the video signal line 106HS. On the other hand, the test switch circuits 144V and 142H are provided for each scanning line for the write scanning line 104WS and the video signal line 106HS, but are not provided for the power supply line 105DSL.

  MOS transistors are used as the transistors including the drive transistor. In this case, for the drive transistor, the gate end is handled as the control input end, and either the source end or the drain end is handled as the input end, and the other is handled as the output end. In particular, regarding a driving transistor that supplies a driving current to the organic EL element 127, one of the source end and the drain end (here, the source end) is handled as an output end, and the other is the power supply end (here, the drain end). ).

  Hereinafter, an example of the pixel circuit P in the 2TR configuration will be specifically described. The pixel circuit P of the present embodiment shown in FIG. 2 is characterized in that the drive transistor is basically composed of an n-channel thin film field effect transistor. In addition, a circuit for suppressing fluctuations in the drive current Ids to the organic EL element due to deterioration over time of the organic EL element, that is, driving by correcting a change in current-voltage characteristics of the organic EL element which is an example of an electro-optical element A drive signal stabilization circuit (part 1) for maintaining the current Ids constant is provided.

  It is also characterized by the use of a drive method that maintains a constant drive current Ids by implementing a threshold correction function and mobility correction function that prevent drive current fluctuations due to drive transistor characteristic fluctuations (threshold voltage variations and mobility variations). Have. As a method for suppressing the influence on the drive current Ids due to characteristic variations of the drive transistor 121 (for example, variations and fluctuations in threshold voltage, mobility, etc.), the 2TR configuration drive circuit is directly adopted as the drive signal stabilization circuit (part 1). However, this is dealt with by devising the drive timing of the transistors 121 and 125.

  The pixel circuit P of the present embodiment is characterized by the connection mode of the storage capacitor 120, and is an example of a drive signal stabilization circuit (part 2) as a circuit that prevents drive current fluctuations due to deterioration with time of the organic EL element 127. A bootstrap circuit is configured. A feature is that it has a drive signal stabilization circuit (part 2) that realizes a bootstrap function that makes the drive current constant even when the current-voltage characteristic of the organic EL element changes with time (to prevent fluctuations in the drive current). It has.

  Incidentally, when the low-temperature polysilicon TFT is used as the driving transistor 121, the non-uniformity of the threshold voltage within the substrate surface is large, and the threshold correction function is almost essential, whereas the driving transistor 121 uses the microcrystalline silicon TFT. It is considered that the threshold voltage correction function can be removed because the non-uniformity of the threshold voltage in the substrate surface is small and the relationship with the required specifications. Here, an example in which all the above functions (threshold correction function, mobility correction function, bootstrap function) are applied will be described.

  Specifically, as illustrated in FIG. 2, the pixel circuit P of the present embodiment includes an n-channel driving transistor 121 and a sampling transistor 125, and an organic EL that is an example of an electro-optical element that emits light when current flows. An element 127 is included. In general, since the organic EL element 127 has a rectifying property, it is represented by a diode symbol. The organic EL element 127 has a parasitic capacitance Cel. In the figure, this parasitic capacitance Cel is shown in parallel with the organic EL element 127 (diode-like one).

  The storage capacitor 120 is connected between the source end (node ND121) and the gate end (node ND122) of the drive transistor 121, and the source end of the drive transistor 121 is directly connected to the anode end of the organic EL element 127. The storage capacitor 120 functions also as a bootstrap capacitor. The cathode terminal K of the organic EL element 127 is set to a cathode potential Vcath as a reference potential. This cathode potential Vcath is connected to a ground wiring Vcath (GND as an example) common to all pixels for supplying a reference potential.

  The ground wiring Vcath may be only a single-layer wiring (upper layer wiring) for the ground wiring Vcath. For example, an auxiliary wiring (auxiliary electrode) for cathode wiring is provided on the anode layer where the wiring for anode is formed. Reduce the resistance of the cathode wiring. This auxiliary wiring is, for example, wired in a grid, column, or row within the pixel array unit 102 (display area), and further wired around the pixel array unit 102 so as to have the same potential as the upper layer wiring. And a fixed potential is applied. Details of the auxiliary wiring will be described later.

  Sampling transistor 125 has a gate end connected to write scan line 104WS from write scan unit 104, a drain end connected to video signal line 106HS, and a source end connected to the gate end (node ND122) of drive transistor 121. Has been. An active H write drive pulse WS is supplied from the write scanning unit 104 to the gate end. The sampling transistor 125 may have a connection mode in which the source end and the drain end are reversed. As the sampling transistor 125, either a depletion type or an enhancement type can be used.

  The drain end of the drive transistor 121 is connected to the power supply line 105DSL from the drive scanning unit 105 that functions as a power scanner. The power supply line 105DSL is characterized in that the power supply line 105DSL itself has a power supply capability to the drive transistor 121. Specifically, the drive scanning unit 105 switches and supplies the first voltage Vcc on the high voltage side and the second voltage Vss on the low voltage side corresponding to the power supply voltage to the drain terminal of the drive transistor 121. A power supply voltage switching circuit is provided.

  The second potential Vss is set to a potential sufficiently lower than the offset potential Vofs of the video signal Vsig in the video signal line 106HS. Specifically, the gate-source voltage Vgs of the drive transistor 121 (the difference between the gate potential Vg and the source potential Vs) is larger than the threshold voltage Vth of the drive transistor 121. Two potential Vss is set. The offset potential Vofs is used for an initialization operation prior to the threshold correction operation and also used for precharging the video signal line 106HS in advance.

  In order to drive the pixel circuit P, a writing scanning unit 104, a driving scanning unit 105, and a horizontal driving unit 106 are arranged around the pixel array unit 102. The controller 109 functions as a drive signal stabilization circuit that maintains the drive current Ids flowing through the drive transistor 121 constant by optimizing the drive timing. For this reason, first, the drive scanning unit 105 preferably sets the sampling transistor 125 in a non-conducting state at the time when information corresponding to the signal amplitude Vin is written in the storage capacitor 120, and the video signal to the control input terminal of the drive transistor 121. It is preferable that the supply of Vsig is stopped and a bootstrap operation is performed in which the potential of the control input terminal is interlocked with the potential fluctuation of the output terminal of the driving transistor 121.

  The control unit 109 preferably executes the bootstrap operation even at the beginning of light emission after the end of the sampling operation. That is, the potential difference between the control input terminal and the output terminal of the drive transistor 121 is constant by turning the sampling transistor 125 in a conductive state after the signal potential is supplied to the sampling transistor 125 and then turning the sampling transistor 125 in a non-conductive state. To be maintained.

  In addition, the control unit 109 preferably controls the bootstrap operation so as to realize the temporal variation correction operation of the electro-optic element (organic EL element 127) in the light emission period. For this reason, the control unit 109 continuously keeps the sampling transistor 125 in a non-conductive state during a period in which the drive current Ids based on the information held in the holding capacitor 120 flows to the electro-optical element (organic EL element 127). Thus, it is preferable that the voltage variation at the control input terminal and the output terminal can be kept constant, and the temporal variation correction operation of the electro-optic element is realized. Even if the current-voltage characteristic of the organic EL element 127 varies with time due to the bootstrap operation of the storage capacitor 120 during light emission, the potential difference between the control input terminal and the output terminal of the drive transistor 121 is kept constant by the bootstrap storage capacitor 120. Therefore, a constant light emission luminance is always maintained.

  Preferably, the control unit 109 causes the sampling transistor 125 to conduct in a time zone in which the offset potential Vofs is supplied to the input terminal (the source terminal is a typical example) of the sampling transistor 125, thereby causing the threshold voltage Vth of the driving transistor 121 to be on. Control is performed so as to perform a threshold value correction operation for holding the voltage corresponding to. This threshold value correction operation is repeatedly executed at a plurality of horizontal periods preceding the writing of information corresponding to the signal amplitude Vin to the storage capacitor 120 as necessary, and reliably corresponds to the threshold voltage Vth of the drive transistor 121. It is preferable to hold the voltage in the holding capacitor 120.

  More preferably, prior to the threshold value correcting operation, the control unit 109 conducts the sampling transistor 125 in a time zone in which the offset potential Vofs is supplied to the input terminal of the sampling transistor 125 to perform a threshold value correcting preparatory operation ( Control is performed to execute a discharge operation or an initialization operation. Before the threshold correction operation, the potentials of the control input terminal and the output terminal of the drive transistor 121 are initialized. More specifically, the storage capacitor 120 is connected between the control input terminal and the output terminal, so that the potential difference between both ends of the storage capacitor 120 is set to be equal to or higher than the threshold voltage Vth.

<< Basic operation to keep driving current constant >>
In the threshold correction in the 2TR drive configuration, the drive scanning unit 105 of the control unit 109 supplies the drive current Ids to each pixel circuit P for one row in accordance with the scanning by the writing scanning unit 104, and the electro-optical element (organic EL). The first potential Vcc used to flow to the element 127) and the second potential Vss different from the first potential Vcc are switched and output. The write scanning unit 104 conducts the sampling transistor 125 in a time zone in which the voltage corresponding to the first potential Vcc is supplied to the power supply terminal of the driving transistor 121 and the signal potential is supplied to the sampling transistor 121. Control is performed to perform the threshold value correction operation.

  In the threshold correction preparation operation in the 2TR drive configuration, sampling is performed in a time zone in which the voltage corresponding to the second potential Vss is supplied to the power supply terminal of the drive transistor 121 and the signal potential is supplied to the sampling transistor 125. It is preferable to initialize the potential of the control input terminal of the driving transistor 121 to the reference potential Vin and the potential of the output terminal to the second potential Vss by making the transistor 125 conductive.

  More preferably, after the threshold correction operation, the control unit 109 conducts the sampling transistor 125 in a time zone in which the voltage corresponding to the first potential Vcc is supplied to the driving transistor 121 and the signal potential is supplied to the sampling transistor 125. Thus, when information on the signal amplitude Vin is written in the storage capacitor 120, the correction for the mobility μ of the driving transistor 121 is controlled to be added to the information written in the storage capacitor 120. At this time, it is preferable that the sampling transistor 125 is turned on at a predetermined position within a time zone in which the signal potential is supplied to the sampling transistor 125 for a period shorter than the time zone.

  A circuit configuration that realizes a bootstrap function in which a holding capacitor 120 is disposed between the gate and the source of the driving transistor 121 and the potential Vg of the gate end is interlocked with the fluctuation of the potential Vs of the source end of the driving transistor 121. Further, by setting the drive timing, even if there is an anode potential variation (that is, a source potential variation) of the organic EL element 127 due to a variation with time in the characteristics of the organic EL element 127, the gate potential Vg is varied so as to cancel the variation. Thus, uniformity of screen brightness can be ensured. The bootstrap function can improve the deterioration correction capability of a current-driven light emitting element typified by an organic EL element. Of course, in the bootstrap function, the light emission current Iel begins to flow through the organic EL element 127 at the start of light emission, and as a result, the anode-cathode voltage Vel rises until it becomes stable. It also functions when the source potential Vs of the drive transistor 121 varies with the variation of the voltage Vel.

  In addition, due to variations in the manufacturing process of the drive transistor 121, there are fluctuations in characteristics such as threshold voltage and mobility for each pixel circuit P. Even when the driving transistor 121 is driven in the saturation region, even if the same gate potential is applied to the driving transistor 121 due to this characteristic variation, the drain current (driving current Ids) varies for each pixel circuit P, and the emission luminance is reduced. Appears as variations.

  On the other hand, by setting the drive timing to realize the threshold value correction function and the mobility correction function, the influence of those fluctuations can be suppressed, and the uniformity of the screen brightness can be ensured. In the threshold value correction operation and the mobility correction operation of the present embodiment, details are omitted, but assuming that the writing gain is 1 (ideal value), the gate-source voltage Vgs at the time of light emission is “Vin + Vth−ΔV”. Thus, the drain-source current Ids is not dependent on the variation or variation of the threshold voltage Vth, and is not dependent on the variation or variation of the mobility μ. As a result, even if the threshold voltage Vth and the mobility μ vary depending on the manufacturing process, the drive current Ids does not vary, and the light emission luminance of the organic EL element 127 does not vary.

<Operation of Pixel Circuit: This Embodiment>
FIG. 2A is a timing chart for explaining the operation when the information of the signal amplitude Vin is written in the storage capacitor 120 by the line sequential method as an example of the drive timing related to the pixel circuit P of the present embodiment shown in FIG. Here, in the example shown in FIG. 2A, the operation and mobility correction for writing information in accordance with the signal amplitude Vin to the storage capacitor 120 are determined by the rise and fall of the write drive pulse WS applied to the write scan line 104WS. It is an aspect to do.

  In FIG. 2A, the change in the potential of the write scanning line 104WS, the change in the potential of the power supply line 105DSL, and the change in the potential of the video signal line 106HS are shown with a common time axis. In addition to these potential changes, changes in the gate potential Vg and source potential Vs of the drive transistor 121 are also shown. Basically, the same driving is performed for each row of the write scanning line 104WS and the power supply line 105DSL with a delay of one horizontal scanning period.

  In the following, for ease of explanation and understanding, unless otherwise specified, it is assumed that the write gain is 1 (ideal value), and information on the signal amplitude Vin is written and held in the holding capacitor 120. Or it will be described briefly as sampling. Actually, the write gain is less than 1, and the holding capacitor 120 holds not the magnitude of the signal amplitude Vin itself but the information multiplied by the gain corresponding to the magnitude of the signal amplitude Vin. For ease of explanation and understanding, unless otherwise noted, the bootstrap gain is assumed to be 1 (ideal value) and will be described briefly.

  In the pixel circuit P of the present embodiment, as the drive timing, first, the sampling transistor 125 is turned on in accordance with the write drive pulse WS supplied from the write scan line 104WS, and the video supplied from the video signal line 106HS. The signal Vsig is sampled and held in the holding capacitor 120. At the drive timing, when writing the information of the signal amplitude Vin of the video signal Vsig to the storage capacitor 120, from the viewpoint of sequential scanning, line sequential driving that simultaneously transmits the video signal for one row to the video signal line 106HS of each column. To do.

  In the basic concept of threshold value correction and mobility correction at the drive timing in the pixel circuit P having the 2TR configuration, first, the video signal Vsig is set to the offset potential Vofs and the signal potential (Vofs + Vin) within the 1H period. We shall have in time division. Specifically, the period in which the video signal Vsig is at the offset potential Vofs, which is the ineffective period, is defined as the first half of one horizontal period, and the period in which the signal potential (Vofs + Vin), which is the effective period, is defined as the latter half of the one horizontal period. To do.

  Further, the write drive pulse WS used for signal writing is also used for threshold correction and mobility correction. Preferably, the write drive pulse WS is activated twice within 1H period to turn on the sampling transistor 125. This is because the sampling (writing operation) of the signal amplitude Vin information and the mobility correction are determined by the rise and fall of the write drive pulse WS applied to the write scan line 104WS. Then, threshold correction is performed at the first on timing, and signal voltage writing and mobility correction are performed simultaneously at the second on timing. Thereafter, the driving transistor 121 receives a current from the power supply line 105DSL at the first potential (high potential side) and is held in the holding capacitor 120 (potential corresponding to the potential of the video signal Vsig during the effective period). In response to this, the drive current Ids is passed through the organic EL element 127.

  For example, in the light emission periods B and I, the power supply drive pulse DSL is at the first potential Vcc, the write drive pulse WS is inactive L, and the sampling transistor 125T1 is turned off. At this time, since the drive transistor 121 is set to operate in the saturation region, the drive current Ids flowing through the organic EL element 127 takes a value corresponding to the gate-source voltage Vgs of the drive transistor 121. The current flowing between the drain end and the source of the transistor operating in the saturation region is Ids, the mobility is μ, the channel width (gate width) is W, the channel length (gate length) is L, and the gate capacitance (gate oxidation per unit area) The driving transistor 121 is a constant current source having a value expressed by the following equation (1), where Cox is the film capacitance and Vth is the threshold voltage of the transistor. As apparent from the equation (1), the drain current Ids of the transistor is controlled by the gate-source voltage Vgs in the saturation region.

  Next, in the non-light emission period, first, in the discharge period C, the power supply driving pulse DSL is set to the second potential Vss. At this time, when the second potential Vss is smaller than the sum of the threshold value VthEL and the cathode voltage Vcath of the organic EL element 127, that is, if “Vss <VthEL + Vcath”, the organic EL element 127 is extinguished and the power supply driving pulse DSL is driven by the driving transistor. 121 source. At this time, the anode of the organic EL element 127 is charged to the second potential Vss.

  Further, when the potential of the video signal line 106HS becomes the offset potential Vofs in the initialization period D, the write drive pulse WS is set to active H, the sampling transistor 125 is turned on, and the gate potential of the drive transistor 121 is set to the offset potential Vofs. To do. At this time, the gate-source voltage Vgs of the driving transistor 121 takes a value of “Vofs−Vss”. Since this threshold value correcting operation cannot be performed unless this “Vofs−Vss” is larger than the threshold voltage Vth of the driving transistor 121, it is necessary to satisfy “Vofs−Vss> Vth”.

  In the threshold correction period E, the power supply driving pulse DSL is again set to the first potential Vcc. By setting the drain which is the power supply end of the driving transistor 121 to the first potential Vcc, the anode of the organic EL element 127 becomes the source of the driving transistor 121 and a current flows. Since the equivalent circuit of the organic EL element 127 is represented by a diode and a parasitic capacitance Cel as shown in FIG. 2, “Vel ≦ Vcath + VthEL” (the leakage current of the organic EL element 127 is considerably smaller than the current flowing through the drive transistor 121. ), The drive current Ids of the drive transistor 121 is used to charge the storage capacitor 120 and the parasitic capacitor Cel. At this time, Vel rises with time. After a certain time has elapsed, the write drive pulse WS is set to inactive L, and the sampling transistor 125 is turned off.

  This operation realizes a threshold correction function. By this threshold value correction function, it is possible to cancel the influence of the threshold voltage Vth of the drive transistor 121 that varies for each pixel circuit P. If the threshold correction period is sufficient, this operation causes the gate-source voltage Vgs of the drive transistor 121 to take the value Vth. At this time, “Vel = Vofs−Vth ≦ Vcath + VthEL”.

  In the threshold correction period E, the source potential Vs of the driving transistor 121 starts to rise as the potential of the power supply line 105DSL changes from the second potential Vss on the low potential side to the first potential Vcc on the high potential side. That is, the gate end of the drive transistor 121 is held at the offset potential Vofs, and the drain current tends to flow until the potential Vs at the source end of the drive transistor 121 rises and the drive transistor 121 is cut off. When cut off, the source potential Vs of the drive transistor 121 becomes “Vofs−Vth”.

  Since the equivalent circuit of the organic EL element 127 is represented by a parallel circuit of a diode and a parasitic capacitance Cel, as long as “Vel ≦ Vcath + VthEL”, that is, the leakage current of the organic EL element 127 is considerably larger than the current flowing through the drive transistor 121. As long as the current is small, the current of the drive transistor 121 is used to charge the storage capacitor 120 and the parasitic capacitor Cel. At this time, since the organic EL element 127 is reverse-biased, the organic EL element 127 does not emit light.

  As a result, when the current path of the drain current flowing through the drive transistor 121 is interrupted, the voltage Vel at the anode end A of the organic EL element 127, that is, the potential of the node ND121 increases with time. Then, when the potential difference between the potential of the node ND121 (source potential Vs) and the voltage of the node ND122 (gate potential Vg) is just the threshold voltage Vth, the driving transistor 121 is turned off from the on state, and the drain current does not flow. The threshold correction period ends. That is, after a certain time has elapsed, the gate-source voltage Vgs of the drive transistor 121 takes a value called the threshold voltage Vth.

  Here, the threshold correction operation may be executed only once, but this is not essential. If necessary, the threshold correction operation may be repeated a plurality of times with one horizontal period as a processing cycle. For example, in practice, a voltage corresponding to the threshold voltage Vth is written in the storage capacitor 120 connected between the gate terminal and the source terminal of the driving transistor 121. However, the threshold correction period E is from the timing when the write drive pulse WS is set to active H to the timing when it is returned to inactive L. If this period is not sufficiently secured, the threshold correction period E ends before that. .

  In order to solve this problem, it is preferable to repeat the threshold correction operation a plurality of times. Here, illustration of the timing is omitted, but the threshold correction operation is repeatedly executed in a plurality of horizontal periods preceding the sampling (signal writing) of the signal amplitude Vin to the holding capacitor 120, so that the driving transistor is surely obtained. A voltage corresponding to the threshold voltage Vth of 121 is held in the holding capacitor 120.

  The control unit 109 according to the present embodiment has a mobility correction function in addition to the threshold value correction function. That is, the vertical driving unit 103 supplies the sampling transistor 125 to the conductive scanning line 104WS in a time zone in which the video signal line 106HS is in the signal potential (Vofs + Vin) that is the effective period of the video signal Vsig. The write drive pulse WS is made active (H level in this example) only for a period shorter than the above-described time zone. By appropriately setting the active period (which is both the sampling period and the mobility correction period) of the write drive pulse WS, the information corresponding to the signal amplitude Vin is held in the holding capacitor 120 at the same time. Add correction for mobility μ. The period during which the signal potential (Vofs + Vin) is actually supplied to the video signal line 106HS by the horizontal drive unit 106 and the write drive pulse WS is set to active H is the period during which the signal amplitude Vin is written to the storage capacitor 120 (sampling period). Also referred to as). In FIG. 2A, the sampling period and the mobility correction period are handled in the same manner and are referred to as a writing & mobility correction period H.

  In the writing & mobility correction period H, the sampling transistor 125 is turned on (on) while the gate potential Vg of the driving transistor 121 is at the signal potential (Vofs + Vin). Accordingly, in the write & mobility correction period H, the drive current Ids flows through the drive transistor 121 while the gate end of the drive transistor 121 is fixed to the signal potential (Vofs + Vin). The gate potential Vg of the drive transistor 121 becomes the signal potential (Vofs + Vin) because the sampling transistor 125 is turned on, but the current flows from the power supply line 105DSL, so that the source potential Vs increases with time.

  When the threshold voltage of the organic EL element 127 is VthEL and the write gain is ideally “1”, the organic EL element 127 is reversed by setting “Vofs−Vth + ΔV <VthEL + Vcath”. Since it is in a bias state and is in a cut-off state (high impedance state), it does not emit light, and exhibits simple capacitance characteristics instead of diode characteristics. If the source potential Vs at this time does not exceed the sum of the threshold voltage VthEL and the cathode potential Vcath of the organic EL element 127 (if the leakage current of the organic EL element 127 is considerably smaller than the current flowing through the driving transistor 121), the driving transistor 121 The drain current (driving current Ids) flowing in the capacitor flows into a capacitance “C = Cs + Cel” obtained by combining both the capacitance value Cs of the storage capacitor 120 and the parasitic capacitance (equivalent capacitance) Cel of the organic EL element 127 and starts charging. To do. As a result, the source potential Vs of the drive transistor 121 increases. At this time, since the threshold value correcting operation of the driving transistor 121 is completed, the driving current Ids flowing through the driving transistor 121 reflects the mobility μ.

  In the timing chart of FIG. 2A, this increase is represented by ΔV. This increase, that is, the negative feedback amount ΔV, which is the mobility correction parameter, is subtracted from the gate-source voltage “Vgs = Vin + Vth” held in the holding capacitor 120 by the threshold correction, and “Vgs = Vin + Vth−ΔV”. Therefore, negative feedback is applied. At this time, the source potential Vs of the drive transistor 121 becomes a value “Vofs−Vth + ΔV” obtained by subtracting the voltage “Vgs = Vin + Vth−ΔV” held in the storage capacitor from the gate potential Vg (= Vofs + Vin). In this manner, in the writing & mobility correction period H, sampling of the signal amplitude Vin and adjustment of the negative feedback amount (mobility correction parameter) ΔV for correcting the mobility μ are performed. The write scanning unit 104 can adjust the time width of the write & mobility correction period H, thereby optimizing the negative feedback amount of the drive current Ids for the storage capacitor 120.

  Here, “optimizing the negative feedback amount” means that the mobility correction can be appropriately performed at any level in the range from the black level to the white level of the video signal potential. The amount of negative feedback applied to the gate-source voltage Vgs depends on the drain current Ids extraction time, that is, the write & mobility correction period H. The longer this period, the larger the negative feedback amount. The negative feedback amount ΔV is ΔV = Ids · t / Cel (the parasitic capacitance other than Cel is ignored).

  As is apparent from this equation, the negative feedback amount ΔV increases as the drive current Ids, which is the drain-source current of the drive transistor 121, increases. Conversely, when the drive current Ids of the drive transistor 121 is small, the negative feedback amount ΔV is small. Thus, the negative feedback amount ΔV is determined according to the drive current Ids. When the mobility μ is large, the driving current Ids at this time is large, and the source rises quickly. On the contrary, when the mobility μ is small, the drive current Ids is small, and the source rises slowly. As a result, the gate-source voltage Vgs of the driving transistor 121 is reduced to reflect the mobility μ, and becomes a gate-source voltage Vgs that completely corrects the mobility μ after a predetermined time has elapsed.

  In this way, at the drive timing in the pixel circuit P of the present embodiment, in the writing & mobility correction period H, the sampling of the signal amplitude Vin and the adjustment of the negative feedback amount ΔV for correcting the variation in the mobility μ are performed. Done at the same time. Of course, the negative feedback amount ΔV can be optimized by adjusting the time width of the writing & mobility correction period H.

  In addition, the control unit 109 of this embodiment also has a bootstrap function. That is, the write scanning unit 104 cancels the application of the write drive pulse WS to the write scan line 104WS at the stage where the information of the signal amplitude Vin is held in the holding capacitor 120 (ie, inactive L (low)). ), The sampling transistor 125 is turned off, and the gate terminal of the drive transistor 121 is electrically disconnected from the video signal line 106HS (light emission period I). When proceeding to the light emission period I, the horizontal driving unit 106 returns the potential of the video signal line 106HS to the offset potential Vofs at an appropriate time thereafter. Thereafter, the process proceeds to the next frame (or field), and the threshold correction preparation operation, the threshold correction operation, the mobility correction operation, and the light emission operation are repeated again.

  In the light emission period I, the gate end of the drive transistor 121 is disconnected from the video signal line 106HS. Since the application of the signal potential (Vofs + Vin) to the gate terminal of the driving transistor 121 is released, the gate potential Vg of the driving transistor 121 can be increased. A storage capacitor 120 is connected between the gate terminal and the source terminal of the driving transistor 121, and a bootstrap operation is performed by the effect of the storage capacitor 120. Assuming that the bootstrap gain is 1 (ideal value), the gate potential Vg is interlocked with the variation of the source potential Vs of the drive transistor 121, and the gate-source voltage Vgs can be kept constant. .

  At this time, the drive current Ids flowing through the drive transistor 121 flows through the organic EL element 127, and the anode potential of the organic EL element 127 rises according to the drive current Ids. Let this increase be Vel. Eventually, as the source potential Vs rises, the reverse bias state of the organic EL element 127 is canceled, so that the organic EL element 127 actually starts to emit light by the inflow of the drive current Ids. The rise (Vel) of the anode potential of the organic EL element 127 at this time is nothing but the rise of the source potential Vs of the drive transistor 121, and the source potential Vs of the drive transistor 121 rises by Vel.

  The relationship between the drive current Ids and the gate voltage Vgs is obtained by substituting “Vin−ΔV + Vth” into Vgs of the equation (1) representing the transistor characteristics when the write gain is “1”. Can be expressed as: In formula (2), k = (1/2) (W / L) Cox.

  From this equation (2), it can be seen that the term of the threshold voltage Vth is canceled and the drive current Ids supplied to the organic EL element 127 does not depend on the threshold voltage Vth of the drive transistor 121. Basically, the drive current Ids is determined by the signal amplitude Vin (specifically, the sampling voltage held in the holding capacitor 120 corresponding to the signal amplitude Vin = Vgs). In other words, the organic EL element 127 emits light with a luminance corresponding to the signal amplitude Vin. At this time, the information held in the holding capacitor 120 is corrected by the feedback amount ΔV. This correction amount ΔV works so as to cancel the effect of the mobility μ located in the coefficient part of the equation (2). Therefore, the drive current Ids substantially depends only on the signal amplitude Vin. Since the drive current Ids does not depend on the threshold voltage Vth, even if the threshold voltage Vth varies depending on the manufacturing process, the drain-source drive current Ids does not vary, and the light emission luminance of the organic EL element 127 does not vary.

  In addition, a storage capacitor 120 is connected between the gate terminal G and the source terminal S of the drive transistor 121. Due to the effect of the storage capacitor 120, a bootstrap operation is performed at the beginning of the light emission period. The gate potential Vg and the source potential Vs of the drive transistor 121 rise while the gate-source voltage Vgs of the transistor is kept constant, and the gate potential Vg becomes “Vofs + Vin + Vel”. At this time, since the gate-source voltage Vgs of the drive transistor 121 is constant, the drive transistor 121 passes a constant current (drive current Ids) to the organic EL element 127. As a result, the potential at the anode end A of the organic EL element 127 (= potential at the node ND121) rises to a voltage at which a current called a drive current Ids in a saturated state can flow through the organic EL element 127.

  Here, the organic EL element 127 has its IV characteristic changed as the light emission time becomes longer. Therefore, the potential of the node ND121 also changes with time. However, even if the anode potential fluctuates due to such deterioration of the organic EL element 127 with time, the gate-source voltage Vgs held in the holding capacitor 120 is always kept constant. Since the drive transistor 121 operates as a constant current source, the IV characteristic of the organic EL element 127 changes with time, and even if the source potential Vs of the drive transistor 121 changes accordingly, the drive transistor 121 drives the drive transistor 121. Since the gate-source potential Vgs 121 is kept constant (≈Vin−ΔV + Vth or ≈ (1−g) Vin−ΔV + Vth), the current flowing through the organic EL element 127 does not change. The light emission brightness is also kept constant.

  Regardless of the characteristic variation of the organic EL element 127, an operation for correction (operation based on the effect of the storage capacitor 120) for maintaining the gate-source voltage of the driving transistor 121 constant and maintaining the luminance constant is performed. This is called a bootstrap operation. By this bootstrap operation, even if the IV characteristic of the organic EL element 127 changes with time, it is possible to display an image without luminance deterioration associated therewith.

<< Peripheral circuit implementation example >>
3 to 3B are diagrams illustrating an example of mounting around the pixel array unit 102. Here, FIG. 3 shows the case of the peripheral circuit panel outside arrangement shown in FIG. 1A in the case where the protection circuit 142 and the test switch circuit 144 are not provided. FIG. 3A shows the case of the peripheral circuit panel outside arrangement configuration shown in FIG. 1A in the case where the protection circuit 142 and the test switch circuit 144 are provided, and particularly shows details of TCP mounting. FIG. 3B shows an example of the electrical connection terminal PAD2 applied in the case of the arrangement configuration outside the peripheral circuit panel.

  As shown in FIG. 3 and FIG. 3A, an electrical connection terminal PAD <b> 2 for connecting by the COF method is provided at the edge portion of the substrate 101 of the display panel unit 100. On the substrate 101, a pixel array portion 102 serving as a display area is provided, and an auxiliary wiring 515 is provided outside the pixel array portion 102. The auxiliary wiring 515 is a ground wiring Vcath that is common to all pixels together with the upper electrode that is not shown in the figure, and is a power supply that is an example of the electrical connection terminal PAD2 provided at the edge of the substrate 101 of the display panel section 100. A reference voltage (GND as an example) is supplied from the TCP 520. Although three power supply TCPs 520 are provided in FIG. 3 and four power supply TCPs 520 are provided in FIG. 3A, the number is arbitrary.

  The electrical connection terminal PAD2 for the control unit 109 is also substantially the same as the power supply TCP 520, and the signal supply TAB 530_WS for the write drive pulse WS provided at the edge portion of the substrate 101 of the display panel unit 100, the power Each signal is supplied from the power input unit 530_DSL for the driving pulse DSL and the signal supply TAB 530_sig for the video signal Vsig. A driver LSI 532 is bonded to each signal supply TAB 530 by the TAB method, the driver output is connected to the edge of the substrate 101, and the driver LSI 532 is mounted outside the substrate 101. Although not shown, a circuit board on which a pre-stage circuit (for example, a shift register) for supplying a signal to the driver LSI 532 is connected is connected to each signal supply TAB 530 on the side opposite to the board 101.

  As shown in FIG. 3B (1), the power supply TCP 520 is provided with a plurality (three in the figure) of cathode electrode pads 524 that are connected to the FPC at a predetermined pitch. It extends to the edge of the wiring 515 (peripheral portion of the pixel array portion 102 which is a display region) and is commonly connected at the contact portion 526.

  The signal supply TAB 530 is also substantially the same as the power supply TCP 520, and as shown in FIG. 3B (2), a plurality of signal electrode pads 534 serving as connection ends with the FPC (for the write drive pulse WS in the figure). 3 for each of the power supply driving pulses DSL, and a scanning line (two types of writing scanning line 104WS and power supply line 105DSL) in which the signal electrode pad 534 extends from the pixel array portion 102 and a contact portion 536 are provided. Although not shown, a plurality of signal electrode pads 534 serving as connection ends with the FPC are provided at a predetermined pitch with respect to the write drive pulse WS, and the signal electrode pads 534 are connected to the pixel array. The scanning line (video signal line 106HS) extending from the portion 102 is connected to each other by a contact portion 536.

<< Auxiliary Wiring Layout >>
4 to 4B are problems related to wiring between the control unit 109 (the writing scanning unit 104, the driving scanning unit 105, and the horizontal driving unit 106) arranged around the pixel array unit 102 and the pixel array unit 102. FIG. Here, FIG. 4 is an overall schematic diagram showing a layout of the first comparative example of the lower electrode of the organic EL element 127 and the auxiliary wiring. FIG. 4A is a detailed view of the panel edge showing the layout of the first comparative example of the lower electrode of the organic EL element and the auxiliary wiring. FIG. 4B is a diagram illustrating a layout of a second comparative example which is a modified example of FIG.

  The layout of the first comparative example of the lower electrode and the auxiliary wiring of the organic EL element 127 is shown in FIGS. 4 and 4A. As shown in this figure, the lower electrodes 504 of the organic EL elements 127 are arranged in a two-dimensional matrix corresponding to the arrangement of the pixel circuits P arranged in a matrix. The organic EL element 127 has a laminated structure of a lower electrode 504, an organic layer 506, and an upper electrode 508. Between the lower electrodes 504, auxiliary wirings 515 configured in the same layer as the lower electrodes 504 are arranged in a lattice shape so as to surround the lower electrodes 504 (that is, the pixel circuits P), and further on the outer periphery of the pixel array section. The configuration is wired so as to surround the whole 102. The auxiliary wiring 515 of the anode layer L3 on which the lower electrode 504 is formed is connected to the upper electrode 508 on the upper layer by a cathode contact KC at an appropriate location (in the example in the figure, the center and the entire outer periphery between each pixel). The

  4A, the auxiliary wiring 515 is provided wider than the area for the cathode contact KC on the outer periphery of the pixel array unit 102, and the auxiliary wiring 515 covers the protection circuit 142 and the test switch circuit 144. It is like that. By doing so, the phenomenon that light enters the transistor of the peripheral circuit section 140 is prevented (details will be described later).

  In the layout of the second comparative example shown in FIG. 4B, the auxiliary wiring 515 surrounds the entire pixel array unit 102 in order to increase the pixel aperture ratio when the top emission type high-definition pixel structure is used. A layout in which the wiring is arranged in a lattice shape, a column, or a row in the pixel array portion 102 (display area) is not used. For example, a high-definition pixel may not use an auxiliary wiring layout in the pixel in order to increase the aperture ratio.

  In any configuration, the auxiliary wiring 515 is wired so as to surround the entire pixel array unit 102, and the contact with the upper electrode is taken over the entire outer periphery, thereby reducing the contact resistance with the upper electrode (cathode electrode). ing. As described above, when the auxiliary wiring 515 is made wider than the pixel array unit 102 in order to reduce the contact resistance with the upper electrode, the auxiliary wiring 515 is respectively transmitted from the control unit 109 to the pixel array as shown in FIGS. 3 and 4A. Each scanning line Lscan (write scanning line 104WS, power supply line 105DSL, video signal line 106HS) connected to the unit 102 overlaps over a wide range.

<< Electrode layer structure >>
5 to 5B are diagrams illustrating the layer structure of the electrode. Here, FIG. 5 is a plan perspective view of the entire layer structure for three pixels of R, B, and G for color display. FIG. 5A shows a plan perspective view (FIG. 5A (1)) focusing on the first wiring layer L1 and the second wiring layer L2 for one pixel, and an anode layer L3 serving as a third wiring layer for one pixel. FIG. 5B is a plan perspective view (FIG. 5A (2)) of interest. FIG. 5B is a perspective plan view (FIG. 5B (1)) and a cross-sectional view (FIG. 5B (2)) of the entire layer structure for one pixel.

  As shown in FIG. 5 and FIG. 5A (1), on the pixel circuit P side, a lower electrode 504 (for example, an anode electrode) is disposed on the substrate 101, and an opening (hereinafter referred to as an opening) of the organic EL element 127 is formed on the lower electrode 504. 127a) (referred to as an EL opening). The lower electrode 504 is provided with a connection hole 504a (for example, TFT-anode contact), and is connected to an input / output terminal (a source electrode in this example) of the driving transistor 121 disposed below the lower electrode 504 through the connection hole 504a. An electrode 504 is connected.

  The periphery of the lower electrode 504 is covered with an opening defining insulating film 505 that is an insulating film pattern, and the upper electrode 508 is provided thereon so as to cover almost the entire surface of the pixel array unit 102. The lower electrodes 504 are arranged in a matrix corresponding to the arrangement of the pixel circuits P (see FIG. 4, FIG. 4B, and FIG. 4A). In this configuration example, the auxiliary wiring 515 is formed around the opening defining insulating film 505. Further, the EL opening 127a is widely exposed so that only a portion where the lower electrode 504, the organic layer 506, and the upper electrode 508 constituting the organic EL element 127 are stacked becomes a light emitting region.

  As shown in FIG. 5A (2), in this configuration example, the electrode plate of the first wiring layer L 1 extending from the gate of the driving transistor 121 and the electrode plate of the second wiring layer L 2 extending from the source of the driving transistor 121. And the storage capacitor 120 is formed.

  FIG. 5B shows the entire layer structure for one pixel. Incidentally, FIG. 5B (1) is a state in which FIG. 5A (2) is superimposed on FIG. 5A (1), and FIG. 5B (2) is a cross section taken along the line aa ′ in FIG. 5B (1). FIG. As shown in FIG. 5B (2), the pixel circuit P is provided at a position corresponding to each pixel circuit P on the substrate 101 and a thin film transistor (TFT) such as a driving transistor 121 and a sampling transistor 125 constituting the pixel circuit P and a holding circuit. A lowermost layer (first wiring layer L1) and a polysilicon layer for forming circuit elements such as a capacitor 120 (capacitance value Cs) are disposed. An interlayer insulating film 502a (oxide film) functioning as a gate insulating film is provided on the first wiring layer L1.

  A polysilicon layer serving as one electrode of the source and drain of the thin film transistor or the storage capacitor 120 is provided further on the interlayer insulating film 502a. In this manner, various wirings constituting the pixel circuit P are formed by the conductive layers constituting each element (thin film transistor, storage capacitor 120) and the conductive layers constituting the source electrode and the drain electrode. These circuit elements are covered with an interlayer insulating film 502b (oxide film) that functions as a channel protective film (etching stop layer). The interlayer insulating films 502a and 502b are collectively referred to as an interlayer insulating film 502.

  Further above the interlayer insulating film 502, a second wiring layer L2 for a scanning line connected to the source electrode, drain electrode, and gate electrode of the thin film transistor is provided. Then, an interlayer insulating film 503 that functions as a planarizing film is provided as an upper layer in a state of covering the second wiring layer L2, and the organic EL element 127 is formed on the interlayer insulating film 503. The organic EL element 127 includes a lower electrode 504 (for example, an anode electrode), an organic layer 506, and an upper electrode 508 (for example, a cathode electrode) that are stacked in order from the lower layer side, and is disposed between the lower electrode 504 and the upper electrode 508. Therefore, the organic EL element 127 has a capacitance component (parasitic capacitance Cel). Specifically, the organic layer 506 has a multilayer structure made of, for example, a low molecular material. For example, a hole injection layer, a hole transport layer, and a light emitting layer are sequentially arranged from the lower electrode 504 side to the upper electrode 508 side. Layer, and an electron transport layer (also serving as an electron injection layer). And in the case of a color display correspondence, the thing suitable for a display color is used as an organic material of a light emitting layer.

  The first wiring layer L1 provided first on the substrate 101 is also used as a layer for forming circuit elements such as thin film transistors (the drive transistor 121 and the sampling transistor 125). Although illustration is omitted, a light shielding metal layer is provided on the surface of the substrate 101 opposite to the side where the transistor and the organic EL element 127 are disposed for light leakage and temperature diffusion.

  In the organic EL display device 1 having such a layer structure, an opening of the organic EL element 101 can be configured as a so-called top emission method in which emitted light is extracted from the side opposite to the substrate 101 on which the organic EL elements 127 are arranged. It is effective in securing the rate. Further, with such a top emission method, the aperture ratio of the organic EL element 127 does not depend on the layout of the thin film transistors that constitute the pixel circuit P. For this reason, a pixel circuit P using a plurality of thin film transistors and storage capacitors 120 can be arranged corresponding to each pixel.

  Since the display device 1 having such a structure is a top emission type in which emitted light is extracted from the side opposite to the substrate 101, the lower electrode 504 is made of a material having high light shielding properties and high reflectance. On the other hand, the upper electrode is configured using a material having high light transmittance. Therefore, the wiring resistance of the upper electrode is increased. Even if the upper electrode is a solid wiring, there is a limit in reducing the resistance value. The auxiliary wiring 515 contributes to reducing the resistance value of the entire cathode wiring by wiring in parallel with the high resistance upper electrode in electrical circuit.

<< Problem of wiring structure at the panel edge >>
6 to 6C are diagrams for explaining problems caused by the wiring structure of the auxiliary wiring and each scanning line in the comparative example. Here, FIG. 6 is a diagram for explaining the arrangement relationship between the auxiliary wiring and each scanning line in the comparative example shown in FIGS. 4 to 4B. 6A is a perspective plan view focusing on the wiring between the vertical drive unit 103 and the pixel array unit 102, and FIG. 6B is a cross-sectional view taken along the line bb ′ in FIG. It is sectional drawing. FIG. 6A is a diagram for explaining a problem appearing in an image caused by a parasitic capacitance formed between the auxiliary wiring and the write scanning line 104 in the comparative example. FIG. 6B is a diagram illustrating a problem that appears in an image due to the wiring resistance of the power supply line 105DSL in the comparative example. FIG. 6C is a diagram for explaining a wiring short-circuit caused by a foreign substance in the comparative example.

  In order to correspond to the pixel circuit P having the layer structure as described above, the wiring structure between the pixel array unit 102 and the control unit 109 has substantially the same layer structure as shown in FIG. . In FIG. 6A, as shown in FIG. 4A, the auxiliary wiring 515 is provided wider than the area for the cathode contact KC on the outer periphery of the pixel array portion 102, and the auxiliary wiring 515 is protected. The circuit 142 and the test switch circuit 144 are shown as being covered.

  As shown in FIG. 6B, an interlayer insulating film 502 is provided on the substrate 101, and a scanning line Lscan is disposed on the interlayer insulating film 502 as the second wiring layer L2. Then, an interlayer insulating film 503 is sequentially provided so as to cover the interlayer insulating film 502 and the scanning line Lscan of the second wiring layer L2. Further, the auxiliary wiring 515 is disposed in the same layer as the anode layer L3 on the interlayer insulating film 503. The auxiliary wiring 515 is covered with an opening defining insulating film 505 that is an insulating film pattern that defines a pixel opening. Between the pixel array unit 102 and the control unit 109, as can be seen from FIG. 6B, an interlayer insulating film 503 (an interlayer insulating film 502b and an interlayer insulating film) which is a dielectric between the scanning line Lscan and the auxiliary wiring 515 is used. 503) is sandwiched (overlapping structure), and thus has a capacitance component (parasitic capacitance Cscan).

  As shown in FIG. 6A, the scanning line Lscan (shown by paying attention to the writing scanning line 104WS for vertical scanning in FIG. 6A) is wired in the horizontal direction. On the control unit 109 side (referred to as the scanning signal input end side) and the opposite side (referred to as the scanning signal output end side) of the pixel array unit 102, the wiring resistance of the scanning line Lscan (indicated by a symbol of a resistance element in the drawing). ) And the wiring delay difference caused by the parasitic capacitance Cscan, the input pulse is more dull on the scanning signal output end side than on the scanning signal input end side, and the effective pulse width is more on the scanning signal output end side than on the signal input end side. Shorter. As in this example, when focusing on the write scanning line 104WS, if the effective pulse width is narrowed, a phenomenon occurs in which the timing is shifted and sufficient writing cannot be performed. However, the effective pulse width at the signal input end side and the scanning signal output end side may occur. As a result, the brightness of the output end side of the image is lower than that of the input end side, and shading occurs, causing image quality degradation. Further, as the time of one horizontal period of the panel signal becomes shorter as the definition becomes higher, the writing time becomes severe, and the image quality deterioration becomes more remarkable.

  Of the scanning lines Lscan, the power supply line 105DSL needs to consider a problem caused by wiring resistance. FIG. 6B is a diagram for explaining this point. As shown in FIG. 2, the pixel circuit P is configured by two transistors (the driving transistor 121 and the sampling transistor 125) and one capacitor (the holding capacitor 120), and has a threshold correction function, a mobility correction function, and a bootstrap function. In order to make it work, the drain side, which is the power supply end of the drive transistor 121, is switched and driven by the first potential Vcc and the second potential Vss. Therefore, as shown in FIG. 6B (1), for the write drive pulse WS Similarly to the write scan line 104WS, the power supply line 105DSL is wired in the horizontal direction.

  Therefore, if the drive current Ids flowing through the drive transistor 121 differs depending on the video pattern, the power supply voltage changes in the horizontal direction in relation to the wiring resistance. The drive transistor 121 is used in the saturation region. However, as shown in FIG. 6B (2), when the power supply voltage changes, the source-drain voltage fluctuates, and due to the Early effect, the same drive voltage (between the gate and source) Even with the voltage Vgs), a difference occurs in the drive current Ids. For this reason, for example, as shown in FIG. 6B (3), when a window pattern is displayed, it is visually recognized as horizontal crosstalk. In order to take measures against the lateral crosstalk, for example, it is necessary to suppress a current drop due to a voltage drop. Generally, since the visual recognition level of the luminance difference is within 1%, measures are taken to satisfy this level.

  Further, in the peripheral portion of the pixel array portion 102, the auxiliary wiring 515 in the same layer as the lower electrode 504 (in this example, the anode electrode) is a scanning line Lscan (writing scanning line 104WS, power supply line 105DSL, video signal line 106HS). As shown in FIG. 6C, there is a concern that the interlayer short circuit through the foreign material frequently occurs and the yield is reduced.

<Improvement method: basic concept>
FIG. 7 and FIG. 7A are diagrams for explaining a technique for improving a problem based on the overlap of the scanning line Lscan and the auxiliary wiring 515 in the peripheral portion of the pixel array unit 102. Here, FIG. 7 corresponds to FIG. 6 showing the comparative example, and is a diagram for explaining the arrangement relationship between the auxiliary wiring 515 and each scanning line Lscan in the mechanism of this embodiment. FIG. 7A is a diagram for explaining the effect of improving the influence of the parasitic capacitance formed between the auxiliary wiring 515 and the scanning line Lscan.

  As described above, in the periphery of the pixel array unit 102, the scanning line Lscan and the auxiliary wiring 515 overlap with each other, so that the parasitic capacitance Cscan is formed. This parasitic capacitance Cscan is formed by a parallel plate structure of parallel running portions. Therefore, by taking measures from this viewpoint, it is considered that the problem based on the overlap of the scanning line Lscan and the auxiliary wiring 515 can be improved. Specifically, the capacitance value of the parasitic capacitance Cscan may be made smaller than that of the comparative example.

  The capacitance value Cp_0 of the parasitic capacitance Cscan formed between the parallel plate electrodes can be specified based on the definition formula of the capacitance formed between the conductors. In other words, the capacitor has a corresponding electrode and is formed by interposing a dielectric between the electrodes. The capacitance C is a value obtained by dividing one charge Q of the capacitor conductive plates by the potential difference V between the conductive plates, and the influence of other conductors may be ignored. Specifically, C = Q / V = εA / t, where the facing interval t of each conductor (electrode), the facing area A, and the relative dielectric constant ε of the substance between the electrodes are defined. In the comparative example shown in FIG. 6B, the material between the conductors is the interlayer insulating film 502b and the interlayer insulating film 503.

  Therefore, in order to reduce the capacitance C (that is, the capacitance value Cp_0 of the parasitic capacitance Cscan), a substance having a small relative dielectric constant ε is interposed between the electrode plates (ε_0> ε_1: referred to as the first method). Alternatively, the facing area A of the electrode plates may be reduced (A_0> A_1: referred to as the second method), or the distance t between the electrode plates may be increased (t_0 <t_1: referred to as the third method). I understand that. Of course, these three methods may be arbitrarily combined (referred to as a fourth method).

  Based on the above, any of the first to fourth methods described above may be employed as a method for laying out the parasitic capacitance Cscan formed between the auxiliary wiring 515 and the scanning line Lscan. However, in this embodiment, the case where the second method is employed will be described in detail.

  The reason why the second method is adopted will be described in detail for the following reason. In the first method, in order to change the relative dielectric constant ε, it is necessary to change the material, and accordingly, various things such as film thickness and homogeneity must be taken into account, which is not easy. In the third method, since the film thickness needs to be changed, various things such as the film thickness and homogeneity must be taken into account, and cannot be simplified. On the other hand, the second method can be realized more easily than the first and third methods.

  Therefore, the basic idea of the improvement method of this embodiment, which will be described as a detailed example, is that the layout is made so that the facing area between the scanning line Lscan and the auxiliary wiring 515 is sufficiently smaller than before. Ultimately, the facing area is zero.

  Basically, it is similar to the previous configuration in that the scanning line Lscan is arranged in the second wiring layer L2 and the auxiliary wiring 515 is arranged in the same layer as the anode layer. However, the present embodiment is different in that the facing area A_1 between the scanning line Lscan and the auxiliary wiring 515 is made smaller than the conventional facing area A_0.

  The facing area A_1 in the present embodiment is set to a level that can be said to be smaller than the conventional common facing area A_0. For this purpose, an opening is formed on the upper side of the scanning line Lscan of the auxiliary wiring 515. For example, it is assumed that the opposing interval t of the electrode plates (in this example, the interval between the layer where the auxiliary wiring 515 is arranged and the scanning line Lscan) and the relative dielectric constant ε of the substance interposed between the electrode plates are the same as before. The capacitance value Cp_1 of the parasitic capacitance Cscan can be made smaller than the conventional capacitance value Cp_0 in the general facing area A_0. As shown in FIG. As long as it can be said that it is sufficiently smaller than the conventional facing area A_0.

  Structurally, an opening is formed on the upper side of the scanning line Lscan of the auxiliary wiring 515 so that a portion of the auxiliary wiring 515 facing the scanning line Lscan has a portion where no electrode is provided. . In short, the amount of overlap is reduced by providing a slit portion 515a in a portion of the auxiliary wiring 515 facing the scanning line Lscan.

  By forming a slit in the auxiliary wiring 515, ultimately, as shown in FIG. 7 (3), the width of the slit 515a (opening) is made wider than the width of the scanning line Lscan. Then, by not providing any electrode at the portion of the auxiliary wiring 515 facing the scanning line Lscan, a mechanism is adopted in which the overlap amount becomes zero, that is, the facing area A_1 becomes zero. You can also.

  As a target for reducing the parasitic capacitance Cscan by making the facing area A smaller than before, attention should be paid to the delay of the scanning pulse and the effective pulse width. For example, as shown in FIG. 7A, the relationship between the time constant τ shown in Expression (3) related to the product of the wiring resistance of the scanning line Lscan and the parasitic capacitance Cscan and one horizontal period satisfies “5τ <1H”. A slit 515 a is provided in the wiring 515. For example, if the pulse waveform at the scanning signal output terminal of the pixel array unit 102 rises 98% of the pulse waveform at the scanning signal input terminal (FIG. 7A), it may be considered that there is no practical problem.

  As described above, in this embodiment, the auxiliary wiring 515 formed in the same layer as the anode layer on the scanning line Lscan of the second wiring layer L2 is slit, thereby reducing the parasitic capacitance Cscan_1 and reducing the wiring delay. It relaxes. As a result, the signal writing time can be increased, shading can be prevented, and high image quality can be achieved. As a result, high definition and high image quality of the panel can be achieved.

  In addition, by providing the slit portion 515a, not only the parasitic capacitance with the scanning line Lscan is reduced, but also an interlayer short circuit with the scanning line Lscan due to a foreign substance can be prevented, and the yield can be improved. In the case of the pixel circuit P shown in FIG. 2, the scanning line Lscan corresponds to the writing scanning line 104WS, the power supply line 105DSL, and the video signal line 106HS, and the writing scanning line 104WS, the auxiliary wiring 515, and the power supply line 105DSL. In addition, it is possible to prevent a short circuit between the auxiliary wiring 515 and the horizontal driving unit 106gs and the auxiliary wiring 515.

  Further, as an additional effect, the slit portion 515a is formed in the auxiliary wiring 515 in the panel edge portion having a large area, so that the layers from the interlayer insulating film 503 are formed when each layer of the organic EL element 127 is formed (during the baking process). There is also an advantage that this slit portion 515a can function as a gas vent hole for venting gas.

<< Improvement Method: First Embodiment >>
FIG. 8 is a diagram for explaining a first embodiment of a wiring arrangement (layout) that can improve the problem based on the overlap between the scanning line Lscan and the auxiliary wiring 515. The first embodiment is a layout example in which additional circuits such as a protection circuit 142 and a test switch circuit 144 arranged between the control unit 109 and the pixel array unit 102 are not considered.

  When adopting a mechanism in which the facing area A_1 becomes zero, as shown in FIG. 7C, the width Wslit (hereinafter also referred to as slit width) of the slit portion 515a applied to the auxiliary wiring 515 is at least the width of the scanning line Lscan. Larger than that. When attention is paid only to the parasitic capacitance Cscan, if the slit width Wslit applied to the auxiliary wiring 515 becomes larger than the width of the scanning line Lscan, the opposing area A remains zero thereafter, so that it is not affected by the slit width Wslit. .

  However, in an actual situation, from the viewpoint of the manufacturing process, there is a problem of how large the slit width Wslit should be with respect to the width Wscan of the scanning line Lscan (hereinafter also referred to as scanning line width). Specifically, in the process of forming each layer, an exposure process using a mask is performed. Mask exposure and CD (critical dimension) loss must be taken into consideration during this exposure process. Here, the CD loss means a difference in processing dimension with respect to the mask dimension. Specifically, it is the difference between the dimension of the resist pattern before etching and the dimension of the completed electrode when the electrode is formed by dry etching using the resist pattern as a mask.

  For example, as shown in FIG. 8A, when a slit having a width Wslit in the auxiliary wiring 515 is to be formed, a plurality of reflected lights from the interface are mutually connected depending on the film thickness and refractive index of the auxiliary wiring 515. Multiple interferences tend to cause degradation of the resist pattern profile due to halation. The light intensity distribution in the resist film fluctuates depending on the state of the reflected light, and a skirt 515b is generated at the lower end portion (both sides of the slit portion 515a) of the auxiliary wiring 515 formed on the interlayer insulating film 503 after the development process. . As a result, the processing dimension of the slit width Wslit of the auxiliary wiring 515 formed in the subsequent etching process varies. Basically, the actual slit width Wslit_1 is narrower than the intended slit width Wslit_0.

Therefore, when it is assumed that the mask displacement is zero, the actual slit width Wslit_1 may be made wider than the width obtained by adding the exposure margin to the electrode width Wscan of the scanning line Lscan. Considering the mask displacement, further margin is required. The figure shows the margin x _0. A margin x _0, the slit width Wslit_0 aimed, becomes as if showing the relationship between the electrode width Wscan scanline Lscan the formula formula (2).

Therefore, as shown in FIG. 8B, the scanning line Lscan around the pixel array unit 102 and the same layer as the anode layer that extends in parallel to the scanning line Lscan in a direction perpendicular to the extending direction. The distance from the auxiliary wiring 515 arranged in the plane (distance in a plane perspective state) is a slit with a value equal to or larger than the margin x ₀ in consideration of an exposure margin such as CD loss or mask displacement on both sides of the slit portion 515a. By designing the portion 515a, it is possible to reliably prevent the scanning line Lscan and the auxiliary wiring 515 from overlapping even when mask displacement occurs.

<< Improvement Method: Second Embodiment >>
FIG. 9 to FIG. 10B are diagrams for explaining a second embodiment of the wiring arrangement (layout) that can improve the problem based on the overlapping of the scanning line Lscan and the auxiliary wiring 515. 9 to 9D are diagrams for explaining a configuration example of the additional circuit 148 (the protection circuit 142 and the test switch circuit 144). In particular, in the first configuration example shown in FIG. 9, the protection circuits 142V and 140H and the test switch circuits 144V and 142H are configured with different circuit elements (MOS transistors) and used for simple lighting inspection and normal use. 9A, the second configuration example shown in FIG. 9A is a case in which a circuit element (MOS transistor) of the protection circuits 142V and 140H is used as a switch element constituting the test switch circuits 144V and 142H. Shows the state during simple lighting inspection and normal use. In any case, three (k−1, k, k + 1) th scanning lines of the same type are shown.

  FIG. 9B is a schematic configuration diagram when the additional circuit 148 (the protection circuit 142 and the test switch circuit 144) is mounted in the vicinity of the pixel array unit 102. FIG. 9C is an equivalent circuit diagram of the display device 1 when an additional circuit 148 (protection circuit 142 and test switch circuit 144) is provided so as to correspond to FIG. 9B. FIG. 9D is a diagram illustrating a problem when the technique of the first embodiment is applied to the transistor portion of the peripheral circuit section 140. 9D (1) is a perspective plan view focusing on the wiring between the vertical drive unit 103 and the pixel array unit 102, and FIG. 9D (2) is a cc ′ line in FIG. 9D (1). FIG.

  10 to 10B are diagrams showing the wiring arrangement (layout) of the second embodiment focusing on the transistor portion of the peripheral circuit section 140. 10 is a layout example of the scanning line Lscan of the vertical scanning system, and FIG. 10A is a plan perspective view focusing on the wiring between the vertical driving unit 103 and the pixel array unit 102. FIG. (2) is a cross-sectional view taken along the line bb ′ of FIG. 10 (1).

  FIG. 10A is a layout example focusing on the horizontal scanning system protection circuit 142H, and FIG. 10B is a layout example focusing on the vertical scanning system protection circuit 142V. Here, FIGS. 10A (1) and 10B are plan perspective views, and FIG. 10A (2) is a cross-sectional view taken along the line d-d ′ of FIG. 10A (1). Although the cross-sectional view taken along the line d-d ′ in FIG. 10B is omitted, it is only necessary to arrange one element of the thin film transistor in FIG. 10A (2) in the arrangement direction. 10A and 10B show the protection circuit 142, the mechanism of the second embodiment is also applied to the test switch circuit 144.

  The second embodiment is characterized by a layout in the case where a peripheral circuit unit 140 such as a protection circuit 142 or a test switch circuit 144 is arranged between the control unit 109 and the pixel array unit 102. In particular, an additional circuit is configured. This considers the relationship with the transistor to be used.

  When the control unit retrofit configuration is adopted, there is a point in time when the pixel array unit 102 and the control unit 109 are separated from each other. There is a greater possibility that static electricity is applied to the circuit element via the TFT or the like than in the case of the TFT integrated configuration. In order to cope with this, protection circuits 142V and 140H are provided for each scanning line in the periphery of the pixel array unit 102 for the purpose of protecting circuit elements from electrostatic breakdown due to static electricity.

  In the case of adopting a retrofitting configuration of the control unit, a test switch circuit is used when a simple lighting test (raster lighting test) is performed at the time of panel manufacture without connecting the control unit 109 to each corresponding scanning line of the pixel array unit 102. 144V and 142H are provided, and a test signal is supplied to all the scanning lines to cause the organic EL elements 127 of each pixel circuit P to emit light, so that TFT defects (short circuit or open) and scanning line defects (open) And the presence of short circuit between adjacent parts).

  For this reason, for example, as shown in FIG. 9, the supply of electrostatic protection elements and test signals to the scanning lines 301 to which the scanning signals IN from the vertical driving unit 103 and the horizontal driving unit 106 are supplied is turned on / off. A switch element that can be turned off is provided. As an example of an element for electrostatic protection, a configuration in which a MOS transistor is diode-connected can be used, and a MOS transistor can also be used as an example of a switch element. When the MOS transistor is used, both the N channel and the P channel can be used, and a CMOS configuration in which the N channel and the P channel are combined can be adopted.

  For example, in the first configuration example shown in FIG. 9, the protection circuit 142 (140V, 140H) and the test switch circuit 144 (142V, 142H) are configured by different circuit elements, and all of the circuit elements have N-channels. A configuration example using MOS transistors is shown. Specifically, the protection circuit 142 has a gate and a source that are connected in common to the scanning line 302 and a drain that is connected to the power supply line 304 of the positive power supply Vdd, and a gate and a source that are common. And a diode-connected MOS transistor 314 having a drain connected to the scanning line 302 and connected to the power supply line 306 of the negative power supply Vss2.

  The test switch circuit 144 includes a MOS transistor 332 arranged between the scanning line 302 and the test signal supply line 322 so that one of the source and the drain is connected to the scanning line 302. In each MOS transistor 332 provided for each scanning line 302, the other of the source and the drain is commonly connected to the test signal supply line 322 (regardless of the scanning line number), and the gate is common to the switch control line 324. (Regardless of the scanning line number). As shown in FIG. 9D, the MOS transistor 332 is turned on when the switch control line 324 is set to H level during the simple lighting test, and the MOS transistor 332 is set when the switch control line 324 is set to L level during normal operation. Turns off.

  On the other hand, the second configuration example shown in FIG. 9A shows a configuration example in which the protection circuit 142 and the test switch circuit 144 are configured by common circuit elements, and N-channel MOS transistors are used for all the circuit elements. Yes. Specifically, the protection circuit 142 and the test switch circuit 144 include a diode-connected MOS transistor 312 whose gate and source are commonly connected to the scanning line 302 and whose drain is connected to the power line 304 of the positive power supply Vdd, A MOS transistor 332 is disposed between the scanning line 302 and the test signal supply line 322 so that one of the source and the drain is connected to the scanning line 302. In each MOS transistor 332 provided for each scanning line, the other of the source and the drain is commonly connected to the test signal supply line 322 (regardless of the scanning line number), and the gate is commonly connected to the switch control line 324. They are connected (regardless of the scanning line number).

  That is, the second configuration example shown in FIG. 9A is obtained by removing the diode-connected MOS transistor 314 of the first configuration example shown in FIG. At the time of the simple lighting test, the MOS transistor 332 is turned on by setting the switch control line 324 to the H level, and at the normal time, it is turned off by setting the switch control line 324 and the test signal supply line 322 to the negative power source Vss2. .

  Here, as described above, in any of the configuration examples shown in FIGS. 9 and 9A, the test signal instead of the signal for driving the pixel circuit P is supplied to the test signal supply line 322 during the simple lighting test in the manufacturing stage. Vtest and a gate control signal (DC potential or pulse) Ngate for turning on the MOS transistor 332 are input to the switch control line 324 from the outside of the panel. In the configuration example shown in FIG. 9A, after commercialization, the test signal supply line 322 and the switch control line 324 are supplied with the negative power source Vss2 from the outside of the panel. That is, in the panel after commercialization, the test signal supply line 322 and the switch control line 324 function as power supply lines for supplying the negative power supply Vss2.

  For example, in FIG. 9B, the additional circuit 148V in the vertical scanning system applies the second configuration example shown in FIG. 9A, and the additional circuit 148H in the horizontal scanning system shows an example in which the second configuration example shown in FIG. 9 is applied. ing. As the circuit arrangement (layout) of the vertical scanning system, the writing scanning unit 104 and the driving scanning unit 105 are driven from both the left and right directions shown in the figure, and the additional circuit 148V is also arranged on both the left and right sides to correspond to them. is doing. On the other hand, the circuit arrangement of the horizontal scanning system is such that the horizontal driving unit 106 drives from one side in the vertical direction (only the upper side) shown in the figure, and the test switch circuit 144 in the additional circuit 148H is on the horizontal driving unit 106 side (that is, illustrated). The protection circuit 142 is disposed on the side opposite to the horizontal driving unit 106 (that is, only on the lower side in the drawing).

  In this case, in FIG. 9C, the additional circuit 148V side of the vertical scanning system turns on the MOS transistor 332 by the gate control signal Ngate, and connects the pixel circuit P to the other of the source and drain of the MOS transistor 332 via the test signal supply line 322. The test signal Vtest corresponding to the write drive pulse WS on the side and the power supply drive pulse DSL is supplied, and the additional circuit 148H side of the horizontal scanning system turns on the MOS transistor 332 by the gate control signal Ngate and passes through the test signal supply line 322. Then, a test signal Vtest corresponding to the video signal Vsig on the pixel circuit P side is supplied to the other of the source and drain of the MOS transistor 332 to perform a raster lighting test.

  Here, leakage current may be a problem for the transistor. The causes of leakage current can be broadly classified into those caused by the element structure of the transistor itself and those caused by an external factor. For example, it is conceivable to deal with the problem caused by the element structure by adopting an LDD (Lightly Doped Drain) structure generally provided to suppress electrical leakage of the TFT.

  On the other hand, as a thing resulting from an external factor, what originates in light (external light) injecting into a thin-film transistor can be considered, for example. Specifically, in the display device 1 having the layer configuration as described above, a pixel circuit disposed between the substrate 101 and the second wiring layer L2 (on the lower layer side of the organic EL element 127 on the pixel array unit 102 side). Peripheral circuit unit 140 is arranged in the same layer as P). In the case of a top emission type display device, light incident from the display surface side (hereinafter referred to as external light) irradiates circuit elements (thin film transistors) constituting the peripheral circuit unit 140 provided in the peripheral part of the pixel array unit 102. There is a concern that it will be.

  For example, consider a thin film transistor using amorphous silicon (a-Si). In general, in a thin film transistor using a-Si, when the channel portion CH is exposed to light, the leak characteristics greatly fluctuate. Although illustration is omitted, compared with a thin film transistor in a dark place (that is, without light irradiation), a thin film transistor in a light place (that is, with light irradiation) has a large leak current and deteriorates leak characteristics. In particular, the leakage current in the off region increases by about 1 to 2 digits. Then, the deterioration of the leak characteristics due to the light causes a decrease in circuit characteristics.

  As a countermeasure against this, it is sufficient to prevent light from leaking into the transistor, and it is conceivable to cover the light incident surface side of the transistor constituting the peripheral circuit portion 140 with a light shielding layer. As an example, paying attention to the point that the auxiliary wiring 515 is provided on the optical input side of the transistor of the peripheral circuit portion 140, the auxiliary wiring 515 covers the transistor of the peripheral circuit portion 140 as shown in FIG. 4A. Conceivable. That is, the auxiliary wiring 515 is used as a light shielding layer for preventing the occurrence of a leakage current of the transistor due to light irradiation. When such a mechanism is employed, light entering the transistor is blocked by the auxiliary wiring 515 functioning as a light-blocking layer, so that light is not incident on the transistor, and variation in characteristics of the transistor due to light irradiation is prevented.

  On the other hand, as shown in the first embodiment, as shown in FIG. 9D (1), the slit portion 515a is provided in the portion of the auxiliary wiring 515 facing the scanning line Lscan to reduce the overlap amount. In addition, when this technique is applied to the transistor portion of the peripheral circuit portion 140, light is transmitted to the transistor of the peripheral circuit portion 140 (particularly the channel region is a problem) through the slit portion 515a as shown in FIG. 9D (2). As a result, the light shielding function using the auxiliary wiring 515 deteriorates.

<Layout of Second Embodiment>
Therefore, in the second embodiment, as shown in FIG. 10, no slit is formed in the auxiliary wiring 515 of the anode layer L3 above the protection circuit 142 (particularly the channel formation region of the transistor). Thus, as shown in FIGS. 10A and 10B, the thin film transistor (particularly the channel region) included in the protection circuit 142 is covered with the auxiliary wiring 515 having a light shielding property. In other words, the channel region of the thin film transistor included in the protection circuit 142 is characterized in that it is disposed only below the auxiliary wiring 515 functioning as a light shielding layer.

  When the thin film transistor is covered with the light shielding layer (auxiliary wiring 515 in this example), the channel portion CH (portion where the gate electrode Qg is laminated) of the thin film transistor is disposed only below the light shielding layer (auxiliary wiring 515). The source and drain of the thin film transistor and the wiring portion extending from the source and drain do not need to be covered with the light shielding layer (auxiliary wiring 515).

  By adopting such a structure, as shown in FIG. 10 (2) showing a cross section taken along line bb ′ of FIG. 10 (1), the portion other than the thin film transistor is shown in FIG. 9D (2). Similarly to the above, external light incident from the display surface (aperture defining insulating film 505) side enters the interlayer insulating film 503 and the interlayer insulating film 502 through the slit portion 515a. On the other hand, as shown in FIG. 10A (2), the thin film transistor (particularly the channel portion CH of the thin film transistor) constituting the protection circuit 142 is selectively disposed only below the auxiliary wiring 515; Light does not pass through and the thin film transistor can be prevented from being exposed to external light. As a result, the characteristic variation of the thin film transistor (particularly the deterioration of the leak characteristic) due to light irradiation is prevented.

1 is a block diagram (COG mounting configuration) showing an outline of a configuration of an active matrix display device which is an embodiment of a display device according to the present invention. 1 is a block diagram (outside peripheral circuit panel arrangement configuration) showing an outline of the configuration of an active matrix display device which is an embodiment of a display device according to the present invention. FIG. It is a figure which shows one Embodiment of the organic EL display apparatus provided with the pixel circuit of the basic composition of this embodiment, and the said pixel circuit. FIG. 3 is a timing chart showing an example of drive timing related to the pixel circuit of the present embodiment shown in FIG. 2. FIG. It is a figure explaining the example of mounting in the case of the arrangement configuration outside a peripheral circuit panel shown to FIG. 1A, when a protection circuit and a test switch circuit are not provided. It is a figure explaining the details of TCP mounting in the case of the arrangement configuration outside a peripheral circuit panel shown in FIG. 1A in the case where a protection circuit and a test switch circuit are provided. It is a figure which shows an example of the electrical connection terminal applied in the case of arrangement | positioning structure outside a peripheral circuit panel. It is the whole schematic diagram which showed the layout of the 1st comparative example of the lower electrode of an organic EL element, and auxiliary wiring. It is detail drawing of the panel edge which showed the layout of the 1st comparative example of the lower electrode of an organic EL element, and auxiliary wiring. It is the figure which showed the layout of the 2nd comparative example which is a modification with respect to FIG. It is a plane perspective view of the whole layer structure about 3 pixels of R, B, G for color displays. FIG. 6 is a plan perspective view focusing on a first wiring layer and a second wiring layer and a plane perspective view focusing on an anode layer for one pixel. It is the plane perspective view and sectional drawing of the whole layer structure about 1 pixel. FIG. 4 is a diagram illustrating an arrangement relationship between auxiliary lines and scanning lines in the comparative example shown in FIGS. 4 to 4B. It is a figure explaining the problem which appears in the image resulting from the parasitic capacitance formed between the auxiliary wiring and the writing scanning line in a comparative example. It is a figure explaining the problem which appears in the image resulting from the wiring resistance of the power supply line in a comparative example. It is a figure explaining the wiring short by the foreign material in a comparative example. It is a figure explaining the arrangement | positioning relationship of the auxiliary wiring and a scanning line in the structure of this embodiment. It is a figure explaining the effect which improves the influence by the parasitic capacitance formed between an auxiliary wiring and a scanning line. It is a figure explaining 1st Embodiment of the layout which made it possible to improve the problem based on the scanning line and auxiliary wiring overlapping. It is a figure which shows the state at the time of the simple lighting test | inspection at the time of employ | adopting the structure which comprises a protection circuit and a test switch circuit by another circuit element, and normal use. It is a figure which shows the state at the time of the simple lighting test | inspection at the time of employ | adopting the structure which combines the circuit element of a protection circuit as a switch element of a test switch circuit, and normal use. It is a schematic block diagram in the case of mounting a protection circuit and a test switch circuit. FIG. 10 is an equivalent circuit diagram of the display device when a protection circuit and a test switch circuit are provided so as to correspond to FIG. 9B. It is a figure explaining the problem at the time of applying the method of 1st Embodiment to the transistor part of a peripheral circuit part. It is the figure which showed the layout of 2nd Embodiment about the scanning line of a vertical scanning system. It is the figure which showed the layout of 2nd Embodiment which paid its attention to the protection circuit and test switch circuit of a horizontal scanning system. It is the figure which showed the layout of 2nd Embodiment which paid its attention to the protection circuit and test switch circuit of a vertical scanning system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 100 ... Display panel part, 101 ... Board | substrate, 102 ... Pixel array part, 103 ... Vertical drive part, 104 ... Write scanning part, 104WS ... Write scanning line, 105 ... Drive scanning part, 105DSL ... Power supply Supply line 106 ... Horizontal drive unit 106HS ... Video signal line 109 ... Control unit 120 ... Retention capacitor 121 ... Drive transistor 125 ... Sampling transistor 127 ... Organic EL element 127a ... EL opening 140 ... Peripheral Circuit unit 142 ... Protection circuit 144 ... Test switch circuit 200 ... Drive signal generation unit 220 ... Video signal processing unit 504 ... Lower electrode 506 ... Organic layer 508 ... Upper electrode 515 ... Auxiliary wiring 515a ... Slit (opening)

Claims (5)

A pixel array unit in which pixel circuits including electro-optic elements that perform display according to signal amplitude are arranged in a matrix;
A scanning line for transmitting various signals for driving the pixel circuit;
In addition,
In the same layer as the layer on which the first electrode opposite to the display surface side of the electro-optic element is disposed, auxiliary wiring is formed so as to surround the periphery of the pixel array portion, and the auxiliary wiring is formed in the pixel array. The second electrode on the display surface side of the electro-optic element is electrically connected around the portion,
In the peripheral portion of the pixel array portion, an opening is formed on the upper side of the scanning line of the auxiliary wiring. The scanning line is configured to be supplied with the signal from a signal supply circuit via an electrical connection terminal,
2. The display device according to claim 1, wherein an opening is formed on the upper side of the scanning line of the auxiliary wiring between the pixel array portion and the electrical connection terminal. The display device according to claim 1, wherein a width of the opening is wider than a width of the scanning line. The display device according to claim 1, wherein the width of the opening is wider than the width of the scanning line plus an exposure margin. A switch element for supplying a test signal input from an inspection apparatus for manufacturing inspection to the scanning line, and / or a protective element for protecting against electrostatic breakdown due to static electricity applied to the scanning line , Provided around the pixel array section,
The auxiliary wiring extends to an upper layer of the switch element and / or the protection element so as to cover a channel region of the switch element and / or the protection element. Display device.

Images