JPH08271931A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: To prevent the dot defects which make the pixels of a liquid crystal display part defective by disposing conductive films, in an island form, in regions where one electrode climbs over the difference in level formed by another electrode. CONSTITUTION: The respective thin-film transistors TFT 1 to TFT 3 divided to a plurality of the pixels of the liquid crystal display part are composed of the island regions of an (i) type semiconductor layer AS. The respective transparent pixel electrodes ITO 1 to ITO 3 connected to the respective TFT 1 to TFT 3 are superposed on the scanning signal lines GL of the next stage of the row direction on the side opposite to the side to be connected to the TFTs. The island regions composed of the first and second conductive films d1, d2 are disposed similarly to the source electrodes SD1 between the respective pixel electrodes ITO 1 to ITO 3 and the electrodes electrically connected to the scanning signal lines GL of the next stage. As a result, the disconnection of the pixel electrodes ITOs at the time of climbing over the shape of the difference in level of the scanning signal lines GL is averted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique effective when applied to an active matrix type liquid crystal display device in which pixels are composed of thin film transistors and pixel electrodes.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a liquid crystal display section in which a plurality of pixels are arranged in a matrix. Each pixel of the liquid crystal display section is arranged in an intersecting region between two adjacent scanning signal lines (gate signal lines) and two adjacent video signal lines (drain signal lines). The scanning signal lines extend in the column direction (horizontal direction) and are arranged in the row direction. The video signal lines extend in the row direction (vertical direction) crossing the scanning signal lines, and a plurality of video signal lines are arranged in the column direction.

The pixels are mainly composed of liquid crystal, a transparent pixel electrode and a common transparent pixel electrode which are arranged with the liquid crystal interposed therebetween.
It is composed of a thin film transistor (TFT). The transparent pixel electrode and the thin film transistor are provided for each pixel. The transparent pixel electrode is connected to a source electrode of the thin film transistor. The drain electrode of the thin film transistor is connected to the video signal line, and the gate electrode is connected to the scanning signal line.

Regarding the liquid crystal display device, for example,
Published by Nikkei McGraw-Hill, Nikkei Electronics, 19
December 15, 86, pp. 193-200.

Further, in the active matrix type liquid crystal display device, there are JP-A-61-93488 and JP-A-61-29820 as known examples using a laminated structure of conductive films for scanning signal lines.

However, in any of the known examples, the scanning signal line of the present invention is composed of a laminated film of a first conductive film made of a metal different from aluminum and a second conductive film made of aluminum and connected to the scanning signal line. There is no description of a structure in which the lower electrode of the capacitive element and the gate electrode of the thin film transistor are formed of a single-layer film made of the same conductive film as the first conductive film.

In any of the known examples, a conductive film is provided so as to overlap with the upper electrode of the capacitive element of the present invention, and the conductive film has a step difference in which the upper electrode is formed by the lower electrode of the capacitive element. There is no description of the configuration of providing islands in the area overcoming.

Therefore, the technique disclosed in the above-mentioned publicly known example was not sufficient to prevent the occurrence of defective screen defects, which is the subject of the present invention.

[0009]

In the above-mentioned liquid crystal display device, foreign matter such as dust is mixed in the liquid crystal display portion during the manufacturing process, or foreign matter is attached to the mask used in the photolithography technique. . When a foreign substance is mixed in or exists between the glass substrate and the gate line of the thin film transistor (or the capacitance line of the capacitive element), the gate line (or the capacitance line) is broken, and the broken pixel line becomes defective. So-called line defects occur.

Further, in a liquid crystal display device having a large display screen size and a long gate line (or capacitance line), the wiring resistance of the gate line (or capacitance line) causes a decrease in signal transmission speed, which enables high-speed operation. There was a problem of not having.

In this type of liquid crystal display device,
A thin film transistor or a capacitor is formed of a laminated body of insulating films or conductive films. For example, when the upper electrode crosses over the lower electrode of the capacitor or the source and drain electrodes cross over the gate electrode of the thin film transistor. , In the step portion formed by the lower electrode and the gate electrode,
The upper electrode, the source, and the drain electrodes are disconnected, and the corresponding pixel malfunctions, so-called point defect malfunction occurs.

An object of the present invention is to provide a liquid crystal display device,
It is an object of the present invention to provide a technique capable of reducing point defects that cause defective pixels in a liquid crystal display unit.

Another object of the present invention is to provide a liquid crystal display device capable of high-speed operation with a high signal writing speed.

Another object of the present invention is to provide a technique capable of reducing the point defects in the liquid crystal display portion and the probability of occurrence of point defects or line defects in the liquid crystal display portion in the liquid crystal display device. To provide.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

In a liquid crystal display device having a pixel composed of a thin film transistor and a pixel electrode in an intersecting region between two adjacent scanning signal lines and two adjacent video signal lines, the thin film transistor includes the two thin film transistors. Of the scanning signal lines, a gate electrode electrically connected to one scanning signal line, a gate insulating film provided on the gate electrode, a semiconductor layer provided on the gate insulating film, and the semiconductor A source electrode and a drain electrode electrically connected to the layer, respectively, one of the source electrode and the drain electrode is connected to the pixel electrode, and the other is one of the two video signal lines. And the scanning signal line is formed of a laminated film of a first conductive film made of a metal different from aluminum and a second conductive film made of aluminum. The pixel electrode of the pixel, which is formed of a single-layer film made of the same conductive film as the first conductive film and is selected by one of the two scanning signal lines, is used as one electrode. An electrode electrically connected to the other scanning signal line of the present scanning signal line is the other electrode, and a storage capacitor element having a dielectric edge film between the one electrode and the other electrode is configured, The other electrode is composed of a single-layer film made of the first conductive film, and a conductive film is provided so as to overlap with the one electrode. The conductive film is formed by planarizing the one electrode with the other electrode. It is characterized in that it is provided in an island shape in a region overcoming a step.

Further, the width of the second conductive film is smaller than that of the first conductive film at least at the intersection with the scanning signal line.

The conductive film is formed of the same conductive layer as the video signal line.

According to the above-mentioned means, since the scanning signal line is composed of the laminated film of the first conductive film made of a metal different from aluminum and the second conductive film made of aluminum, the wiring resistance can be reduced and the scanning can be performed. It is possible to prevent disconnection of the signal line.

Further, since the other electrode (lower electrode) of the storage capacitor is composed of the first conductive film made of a metal different from aluminum, compared to the case where the other electrode is composed of the second conductive film made of aluminum. Hillocks generated in aluminum prevent pinholes from opening in the dielectric of the storage capacitor and short circuit between one electrode (upper electrode) and the other electrode of the storage capacitor. Can be prevented.

Further, a conductive film is provided so as to overlap with one electrode (upper electrode) of the storage capacitor, and the conductive film has a step difference in which the one electrode is formed by the other electrode (lower electrode) in plan view. Since the one electrode and the pixel electrode, which are integrally formed, are electrically connected by the conductive film even when a connection failure occurs in the step portion formed by the other electrode, since the one electrode and the pixel electrode are integrally formed in the area overcoming Since it is connected, there is no disconnection.

Further, since the width of the second conductive film is made smaller than that of the first conductive film at least at the intersection with the scanning signal line, the step formed by the scanning signal line is relaxed. The video signal line formed above does not break at the step portion formed by the scanning signal line.

Further, by forming the conductive film from the same conductive film as the video signal line, disconnection between one electrode of the storage capacitor element and the pixel electrode can be prevented without increasing the number of manufacturing steps.

The structure of the present invention will be described below with reference to an embodiment in which the present invention is applied to an active matrix type color liquid crystal display device.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals and their repeated description will be omitted.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment I) One pixel of the liquid crystal display portion of the active matrix type color liquid crystal display device which is Embodiment I of the present invention is shown in FIG. The cut cross section is shown in FIG. Further, FIG. 3 (plan view of a main part) shows a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 1 are arranged.

As shown in FIGS. 1 to 3, the liquid crystal display device includes a thin film transistor TFT and a transparent pixel electrode IT on the inner (liquid crystal side) surface of the lower transparent glass substrate SUB1.
A pixel having O is formed. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 [mm].

Each pixel is within an intersection area between two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines) DL. It is arranged (in a region surrounded by four signal lines). As shown in FIGS. 1 and 3, the scanning signal lines GL extend in the column direction and a plurality of scanning signal lines GL are arranged in the row direction.
The video signal lines DL extend in the row direction and a plurality of video signal lines DL are arranged in the column direction.

The thin film transistor TFT of each pixel is divided into three (plural) within the pixel, and thin film transistors (divided thin film transistors) TFT1, TFT2, and TF.
It is composed of T3. Thin film transistors TFT1 to T
Each of the FT3s has substantially the same size. The divided thin film transistors TFT1 to TFT
Each of 3 is mainly composed of a gate electrode GT, an insulating film GI, an i-type semiconductor layer AS, a pair of a source electrode SD1 and a drain electrode SD2.

The gate electrode GT is projected in the row direction (downward in FIGS. 1 and 4) from the scanning signal line GL, as shown in detail in FIG. 4 (plan view of the main part in a predetermined manufacturing process). Is configured. That is, the gate electrode G
T is configured to extend substantially parallel to the video signal line DL. The gate electrode GT is configured to project to the respective formation regions of the thin film transistors TFT1 to TFT3. Thin film transistors TFT1 to TFT
The respective gate electrodes GT of 3 are integrally configured (as a common electrode) and are connected to the same scanning signal line GL. The gate electrode GT is composed of a single-layer first conductive film g1 so as to prevent the step shape from growing as much as possible in the formation region of the thin film transistor TFT. First conductive film g1
Is formed using a chromium (Cr) film formed by sputtering, for example, with a film thickness of about 1000 [Å].

The scanning signal line GL is composed of a composite film composed of a first conductive film g1 and a second conductive film g2 provided on the first conductive film g1. The first conductive film g of the scanning signal line GL
1 is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT and is integrally formed. The second conductive film g2 is formed of, for example, an aluminum (Al) film formed by sputtering and has a film thickness of about 2000 to 4000 [Å]. The second conductive film g2 is configured to significantly reduce the resistance value of the scanning signal line GL itself, thereby increasing the signal transmission speed (pixel selection speed).

The scanning signal line GL is connected to the first conductive film g1.
The width of the second conductive film g2 is smaller than that of the second conductive film g2. That is, since the scanning signal line GL can reduce the step shape of the side wall thereof, the scanning signal line GL is configured to flatten the surface of the insulating film GI above it.

The insulating film GI is made of a thin film transistor TFT1
~ Used as a gate insulating film for each of the TFTs 3. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. The insulating film GI is, for example, plasma C
A silicon nitride film formed by VD is used to form a film having a thickness of about 3000 [Å]. In this case, the film transistor TF
Gate electrodes GT of T1 to TFT3 and scanning signal lines GL
With the above-described configuration, the surface of the insulating film GI is configured to be flattened in the respective formation regions of the thin film transistors TFT1 to TFT3 and the scanning signal line GL formation region.

The i-type semiconductor layer AS is used as a channel forming region of each of the plurality of thin film transistors TFT1 to TFT3, as shown in detail in FIG. 5 (plan view of an essential part in a predetermined manufacturing process). The i-type semiconductor layer AS of each of the plurality of thin film transistors TFT1 to TFT3 is integrally formed in the pixel. That is, a plurality of thin film transistors TF in which pixels are divided
Each of T1 to TFT3 is composed of one (common) island region of the i-type semiconductor layer AS. i-type semiconductor layer AS
Is formed of an amorphous silicon film or a polycrystalline silicon film and has a film thickness of about 200 to 3000 [Å].

In this way, the thin film transistor T is formed by integrally forming the i-type semiconductor layers AS of the thin film transistors TFT1 to TFT3 divided into a plurality of pixels.
The drain electrode SD2 common to the FT1 to TFT3 is the i-type semiconductor layer AS (actually, the film thickness of the first conductive film g1 and i
The step difference corresponding to the film thickness obtained by adding the film thickness of the type semiconductor layer AS) is only passed once from the drain electrode SD2 side to the i type semiconductor layer AS side. The probability of occurrence can be reduced. That is, when the drain electrode SD2 goes over the step of the i-type semiconductor layer AS, the point defects generated in the pixel can be reduced to 1/3.

Further, although different from the layout of the embodiment I, when the video signal line DL directly goes over the i-type semiconductor layer AS and the video signal line DL of this overriding portion is formed as the drain electrode SD2, the video signal line It is possible to reduce the probability of occurrence of line defects due to disconnection when the DL (drain electrode SD2) crosses over the i-type semiconductor layer AS. That is, by integrally forming the i-type semiconductor AS of each of the thin film transistors TFT1 to TFT3 divided into a plurality of pixels, the video signal line DL (drain electrode S
This is because D2) can get over the i-type semiconductor layer AS only once (actually, it is two times at the beginning and at the end of riding).

As shown in detail in FIGS. 1 and 5, the i-type semiconductor layer AS is provided so as to extend between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. Has been. The extended i-type semiconductor layer AS is configured to reduce the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

The source electrode SD1 and the drain electrode SD2 of each of the thin film transistors TFT1 to TFT3 divided into a plurality of pixels are shown in detail in FIG. 1, FIG. 2 and FIG. 6 (plan view of the main part in a predetermined manufacturing process). As described above, the i-type semiconductor layers AS are provided separately from each other. Each of the source electrode SD1 and the drain electrode SD2 is configured such that the source and the drain are switched in operation when the bias polarity of the circuit changes. That is, the thin film transistor TF
T is bidirectional, similar to a FET.

Each of the source electrode SD1 and the drain electrode SD2 is a first layer from the lower layer side in contact with the i-type semiconductor layer AS.
The conductive film d1, the second conductive film d2, and the third conductive film d3 are sequentially stacked. The first conductive film d1, the second conductive film d2, and the third conductive film d3 of the source electrode SD1 are formed in the same manufacturing process as that of the drain electrode SD2.

The first conductive film d1 is a chromium film formed by sputtering and is formed to have a film thickness of 500 to 1000 [Å] (in this embodiment, a film thickness of about 600 [Å]). The chrome film is formed in a range not exceeding a film thickness of about 2000 [Å] because stress increases as the film thickness increases. The chromium film has good contact with the i-type semiconductor layer AS. The chromium film constitutes a so-called barrier layer that prevents aluminum of the second conductive film d2 described later from diffusing into the i-type semiconductor layer AS. As the first conductive film d1, a refractory metal (Mo, Ti, Ta, W) film, a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi) other than the chromium film.
₂ , WSi ₂ ) film may be used.

The second conductive film d2 is an aluminum film formed by sputtering and is formed to have a film thickness of 3000 to 4000 [Å] (in this embodiment, a film thickness of about 3000 [Å]). The aluminum film has less stress than the chromium film and can be formed to have a large film thickness.
The resistance values of D1, the drain electrode SD2, and the video signal line DL are reduced. That is, the second conductive film d2 increases the operating speed of the thin film transistor TFT,
Also, the signal transmission speed of the video signal line DL can be increased. As the second conductive film d2, in addition to the aluminum film, silicon (Si) or copper (C
It may be formed of an aluminum film containing u) as an additive.

As the third conductive film d3, a transparent conductive film (ITO: Nesa film) formed by sputtering is used, and 1000 to 20 is used.
It is formed with a film thickness of 00 [Å] (in this embodiment, a film thickness of about 1200 [Å]). The third conductive film d3 constitutes the source electrode SD1, the drain electrode SD2 and the video signal line DL, and also constitutes the transparent pixel electrode ITO.

Each of the first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 is the upper second film.
The channel formation region side has a larger size than the conductive film d2 and the third conductive film d3. That is, even if the first conductive film d1 is misaligned with the mask in the manufacturing process between the first conductive film d1, the second conductive film d2, and the third conductive film d3, the second conductive film d2 and the third conductive film d1 are formed. The size is larger than that of the film d3 (each of the first conductive film d1 to the third conductive film d3 may be on-the-line on the channel formation region side). The first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 are respectively
The gate length L of the thin film transistor TFT is defined.

As described above, in the thin film transistors TFT1 to TFT3 divided into a plurality of pixels, the second conductive film d2 and the third conductive film are formed on the channel formation region side of the first conductive film d1 of each of the source electrode SD1 and the drain electrode SD2. Membrane d
3 is larger than the first conductive film d of the source electrode SD1 and the drain electrode SD2.
The dimension between 1 can define the gate length L of the thin film transistor TFT. The separation dimension (gate length L) between the first conductive films d1 can be defined by the processing accuracy (patterning accuracy).
~ The gate length L of each of the TFTs 3 can be made uniform.

The source electrode SD1 is connected to the transparent pixel electrode ITO as described above. Source electrode SD1
Are formed along the step shape of the i-type semiconductor layer AS (the step corresponding to the film thickness obtained by adding the film thickness of the first conductive film gl and the film thickness of the i-type semiconductor layer AS). Specifically, the source electrode SD1 is connected to the first conductive film d1 formed along the step shape of the i-type semiconductor layer AS and the transparent pixel electrode ITO on the upper part of the first conductive film d1 as compared with the first conductive film d1. The second conductive film d2 having a small size on the opposite side and a third conductive film d3 connected to the first conductive film d1 exposed from the second conductive film. The first conductive film d1 of the source electrode SD1 has good adhesiveness to the i-type semiconductor layer AS,
In addition, it is mainly configured as a barrier layer against a diffused substance from the second conductive film d2. The second conductive film d2 of the source electrode SD1 cannot be formed thick because the chromium film of the first conductive film d1 cannot be formed thickly due to the increase in stress, and cannot overcome the step shape of the i-type semiconductor layer AS. Configured to get over.

That is, the second conductive film d2 is formed thick to improve the step coverage. Since the second conductive film d2 can be formed thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL). The third conductive film d3 is
Since the step shape of the second conductive film d2 caused by the i-type semiconductor layer AS cannot be overcome, the second conductive film d2 is configured to be connected to the exposed first conductive film d1 by reducing the size thereof. There is. The first conductive film d1 and the third conductive film d3 not only have good adhesiveness, but also have a small step difference in the connecting portion between them, so that they can be reliably connected.

As described above, the source electrode SD1 of the thin film transistor TFT is formed at least on the first conductive film d1 as a barrier layer formed along the i-type semiconductor layer AS and on the first conductive film d1. The second conductive film d2 has a smaller specific resistance value than the first conductive film and a smaller size than the first conductive film.
By connecting the third conductive film d3, which is the transparent pixel electrode ITO, to the first conductive film d1 exposed from 2, it is possible to reliably connect the thin film transistor TFT and the transparent pixel electrode ITO, thus reducing point defects. be able to. Moreover, since the source electrode SD1 can use the second conductive film d2 (aluminum film) having a small resistance value due to the barrier effect of the first conductive film d1, the resistance value can be reduced.

The drain electrode SD2 is formed integrally with the video signal line DL and is formed in the same manufacturing process. The drain electrode SD2 is formed in an L shape protruding in the column direction intersecting with the video signal line DL. That is,
Thin film transistors TFT1 to T divided into a plurality of pixels
The drain electrodes SD2 of the FT3 are connected to the same video signal line DL.

The transparent pixel electrode ITO is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode ITO corresponds to each of the thin film transistors TFT1 to TFT3 divided into a plurality of pixels
One transparent pixel electrode (divided transparent pixel electrode) ITO1, IT
It is divided into O2 and IT03. Transparent pixel electrode IT
O1 is a source electrode SD1 of the thin film transistor TFT1
It is connected to the. The transparent pixel electrode ITO2 is connected to the source electrode SD1 of the thin film transistor TFT2. The transparent pixel electrode ITO3 is a thin film transistor TFT
3 of the source electrodes SD1.

Each of the transparent pixel electrodes ITO1 to ITO3 has substantially the same size as each of the thin film transistors TFFT1 to TFT3. Each of the transparent pixel electrodes ITO1 to ITO3 is a thin film transistor T.
Since the i-type semiconductor layers AS of FT1 to TFT3 are integrally configured, they are L-shaped.

As described above, two adjacent scanning signal lines G
The thin film transistor TFT of the pixel arranged in the intersecting region between the L and the two adjacent video signal lines DL is divided into a plurality of thin film transistors TFT1 to TFT3, and a plurality of thin film transistors TFT1 to TFT3 are provided. By connecting the divided transparent pixel electrodes ITO1 to ITO3 to each other, only the divided part of the pixel (for example, TFT1) becomes a point defect, and the pixel as a whole does not become a point defect (TFT2 and TFT3 Since it is not a defect), the point defect of the pixel itself can be reduced.

Further, since some of the divided point defects of the pixel are smaller than the entire area of the pixel (in this embodiment, the area is one-third of the pixel), it is difficult to see the point defect. However, it is possible to make it difficult to recognize the point defect of the pixel itself.

Further, by forming the transparent pixel electrodes ITO1 to ITO3, which are the divided pixels, to have substantially the same size, the area of point defects in the pixel can be made uniform.

Further, by forming the divided transparent pixel electrodes ITO1 to ITO3 of the pixel in substantially the same size, the respective capacitances of the transparent pixel electrodes ITO1 to ITO3 and the transparent pixel electrodes ITO1 to ITO3. It is possible to make uniform the capacitance generated by the overlap with the gate electrode GT added to each of the above. That is, since the respective capacitances of the transparent pixel electrodes ITO1 to ITO3 can be made uniform, it is possible to prevent the direct current component from being applied to the liquid crystal molecules of the liquid crystal LD and prevent the deterioration of the liquid crystal molecules.

A protective film PSV1 is provided on the thin film transistor TFT and the transparent pixel electrode ITO. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like, and a film having high transparency and good moisture resistance is used. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a film thickness of about 8000 [Å].

Protective film PSV on thin film transistor TFT
The shielding film L is formed on the upper part of the shield film 1 so that external light does not enter the i-type semiconductor layer AS used as a channel formation region.
S is provided. As shown in FIG. 1, the shielding film LS
Are configured within the area surrounded by the dotted line. Shielding film L
S is formed of, for example, an aluminum film or a chrome film having a high light shielding property, and is 1000
It is formed to a film thickness of about [Å].

The thin film transistor TFT has a gate electrode G
When a positive bias is applied to T, the channel resistance between the source and the drain is reduced, and when the bias is zero, the channel resistance is increased. That is, the thin film transistor TFT is configured to control the voltage applied to the transparent pixel electrode ITO.

The liquid crystal LC is a lower transparent glass substrate SUB1.
In the space formed between the upper transparent glass substrate SUB2 and the upper transparent glass substrate SUB2, a lower alignment film ORI1 and an upper alignment film ORI2 that set the orientation of the liquid crystal molecules are defined and enclosed.

The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

A color filter FIL and a protective film PSV are provided on the inner (liquid crystal side) surface of the upper transparent glass substrate SUB2.
2. Common transparent pixel electrode ITO and the upper alignment film ORI
2 are sequentially stacked.

The common transparent pixel electrode ITO opposes the transparent pixel electrode ITO provided for each pixel on the lower transparent glass substrate SUB1 side and is adjacent to the other common transparent pixel electrode IT.
It is integrated with O.

The color filter FIL is formed by coloring a dyeing base material made of a resin material such as acrylic resin with a dye. The color filter FIL is formed and dyed separately for each pixel at a position facing the pixel. That is, the color filter FIL, like the pixel, includes the two adjacent scanning signal lines GL and the two adjacent video signal lines D.
It is configured in the area of intersection with L. Each pixel is divided into a plurality of pixels within each predetermined color filter of the color filter FIL.

The color filter FIL can be formed as follows. First, the upper transparent glass substrate SUB2
A dyeing base material is formed on the surface of and the dyeing base material other than the red filter forming region is removed by photolithography technology. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

As described above, by forming each color filter of the color filter FIL in the intersection area facing each pixel, the color filters of the color filter FIL are provided between the color filters.
Since the scanning signal line GL and the video signal line DL are respectively present, an alignment margin dimension between each pixel and each color filter of the color filter FIL is secured (increasing the alignment margin) by an amount corresponding to their presence. be able to. Further, when forming each color filter of the color filter FIL, it is possible to secure a positioning margin dimension between different color filters.

That is, according to the present invention, a pixel is formed in an intersecting area between two adjacent scanning signal lines GL and two adjacent video signal lines DL, and the pixel is divided into a plurality of pixels. By forming each color filter of the color filter FIL at the facing position, it is possible to reduce the above-mentioned point defect and to secure an alignment margin dimension between each pixel and each color filter.

The protective film PSV2 is the color filter F.
It is provided in order to prevent the dyes obtained by dyeing the ILs in different colors from getting wet with the liquid crystal LC. Protective film PSV2
Is formed of a transparent resin material such as acrylic resin or epoxy resin.

In this liquid crystal display device, the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side are separately formed, and then the upper and lower transparent glass substrate SUB1.
And SUB2 are superposed on each other, and a liquid crystal LC is sealed between them to assemble.

As shown in FIG. 3, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal line GL extends, and the pixel columns X ₁ , X ₂ , X ₃ , X ₄ are arranged. ,, ..., respectively. The respective pixels of each pixel row X ₁ , X ₂ , X ₃ , X ₄ , ... Have the same arrangement positions of the thin film transistors TFT1 to TFT3 and the transparent pixel electrodes ITO1 to ITO3. That is, each pixel in the pixel row X ₁ , X ₃ , ...
The thin film transistors TFT1 to TFT3 are arranged on the left side, and the transparent pixel electrodes ITO1 to ITO3 are arranged on the right side. Pixel column X _1, X _3, ... of the next stage each pixel in the row direction column X _2, X _4, ... the pixel of each of the pixel rows X _1, X _3, ... the video signal to each pixel of the It is composed of pixels arranged in line symmetry with respect to the line DL. That is,
Each pixel of the pixel row X ₂ , X ₄ , ... Has the transparent pixel electrode I on the right side of the arrangement position of the thin film transistors TFT1 to TFT3.
The TO1-ITO3 are arranged on the left side. The pixels of the pixel rows X ₂ , X ₄ , ... Are arranged so as to be moved (shifted) by a half pixel interval in the column direction with respect to the pixels of the pixel rows X ₁ , X ₃ ,. . That is, when the pixel interval of the pixel row X is 1.0 (1.0 pitch),
The pixel pitch of the next-stage pixel row X is 1.0, and the pixel pitch is 0.5 pixel intervals (0.5 pitch) in the column direction with respect to the pixel row X of the preceding stage. The video signal lines DL extending in the row direction between the pixels are arranged such that a half pixel interval (0.
It is configured to extend in the column direction (for 5 pitches).

As described above, in the liquid crystal display portion, a plurality of pixels having the same arrangement position of the thin film transistor TFT and the transparent pixel electrode ITO are arranged in the column direction to form the pixel column X,
The pixel row X of the next stage of the pixel row X is configured by pixels in which the pixels of the pixel row X of the previous stage are arranged in line symmetry with respect to the video signal line DL, and the pixel row of the next stage is compared with the pixel row of the previous stage. By moving by a half pixel interval, as shown in FIG. 7 (a plan view of a main part in a state where the pixel and the color filter are overlapped), the pixel ( For example, a pixel in the pixel row X _{3 in which} the red filter R is formed and a pixel in the next pixel row X in which the same color filter is formed (for example, a pixel in the pixel row X _{4 in which} the red filter R is formed). Can be separated by 1.5 pixels (1.5 pitch). That is, the pixel of the pixel row X in the previous stage is configured to be always separated by 1.5 pixel intervals from the pixel in the nearest pixel row of the next stage in which the same color filter is formed, and the color filter FIL is RGB. The triangular arrangement structure of can be configured. Since the RGB triangular arrangement structure of the color filter FIL can improve the color mixture of each color, the resolution of the color image can be improved.

Further, since the video signal lines DL extend in the column direction only by a half pixel interval between the pixel columns X, they do not intersect with the adjacent video signal lines DL. Therefore,
The area occupied by the video signal line DL is reduced, and the video signal line DL is reduced.
The multi-layer wiring structure can be eliminated.

The circuit configuration of this liquid crystal display section is as follows:
As shown in FIG. 9 (equivalent circuit diagram of the liquid crystal display unit). XiG, Xi + 1G, ... Shown in FIG.
Is the video signal line DL connected to the pixel in which the pixel is formed.
XiB, Xi + 1B, ... Are video signal lines DL connected to the pixels where the blue filter B is formed. Xi + 1
R, Xi + 2R, ... Are video signal lines DL connected to the pixels in which the red filter R is formed. These video signal lines DL are selected by the video signal drive circuit. Yi is a scanning signal line GL for selecting the pixel column X ₁ shown in FIGS. 3 and 7. Similarly, each of Yi + 1, Yi + 2, ... Is a scanning signal line GL that selects each of the pixel columns X ₂ and X ₃ . These scanning signal lines GL are connected to the vertical scanning circuit.

The central portion of FIG. 2 shows a cross section of one pixel portion, but the left portions are transparent glass substrates SUB1 and SUB.
2 shows a cross section of the left edge portion of No. 2 where the lead wiring exists. The right side shows transparent glass substrates SUB1 and SUB2
3 shows a cross section of a portion on the right-hand side edge where the lead-out wiring does not exist.

Sealing material S shown on the left and right sides of FIG. 2, respectively.
L is configured to seal the liquid crystal LC, and is a transparent glass substrate SUB excluding the liquid crystal sealing port (not shown).
1 and SUB2 along the entire periphery of the edge.
The seal material SL is formed of, for example, an epoxy resin.

The common transparent pixel electrode ITO on the side of the upper transparent glass substrate SUB2 is made of a silver paste material SIL at least at one place by the lower transparent glass substrate SUB.
It is connected to the lead-out wiring layer formed on the first side. The lead-out wiring layer includes the gate electrode GT and the source electrode SD described above.
1 and the drain electrode SD2 are formed in the same manufacturing process.

Alignment films ORI1 and ORI2, transparent pixel electrode ITO, common transparent pixel electrode ITO, protective film PSV
1 and PSV2, and the insulating film GI are each made of a sealing material S.
It is formed inside L. The polarizing plate POL is formed on the outer surface of each of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2.

(Example II) Example II is another example of the present invention in which the aperture ratio of each pixel of the liquid crystal display portion of the liquid crystal display device is improved.

FIG. 8 (main part plan view) shows one pixel of the liquid crystal display portion of the liquid crystal display device which is Embodiment II of the present invention.

As shown in FIG. 8, the liquid crystal display device of Example II is configured by dividing the i-type semiconductor layer AS in each pixel of the liquid crystal display portion into thin film transistors TFT1 to TFT3. That is, each of the thin film transistors TFT1 to TFT3, which is divided into a plurality of pixels, is formed of an independent island region of the i-type semiconductor layer AS.

The pixels configured as described above are arranged in the thin film transistors TFT1 to TFT1 in the row direction in which the video signal lines DL extend.
Since each of the TFTs 3 can be evenly arranged, each of the transparent pixel electrodes ITO1 to ITO3 connected to each of the thin film transistors TFT1 to TFT3 can be formed in a rectangular shape. Transparent pixel electrode I having a rectangular shape
Since each of TO1 to ITO3 can reduce the separation area in the row direction between the adjacent transparent pixel electrodes ITO in the pixel (reduce the area corresponding to the shaded area in FIG. 1), (Aperture ratio) can be improved.

Further, as shown by the reference numeral A in FIG. 8 surrounded by a dotted line, when the respective shapes of the transparent pixel electrodes ITO1 to ITO3 are changed, they are inclined with respect to the scanning signal line GL or the video signal line DL. A line with an angle (eg 45
Change with the angle line). That is, the transparent pixel electrode I
Each of TO1 to ITO3 can reduce the separation area between the transparent pixel electrodes ITO as compared with the case where the shape is changed by a line parallel or orthogonal to the scanning signal line GL or the video signal line DL. Therefore, the aperture ratio can be improved.

Further, each of the transparent pixel electrodes ITO1 to ITO3 is superposed on the scanning signal line GL at the next stage in the row direction on the side opposite to the side connected to the thin film transistor TFT. The scanning signal line GL is composed of the first conductive film g1. Transparent pixel electrode ITO1 overlapped
~ Each of the ITO3 and the next scanning signal line GL constitutes a capacitance element, and the transparent pixel electrode ITO1 of the selected pixel
Each of the ITO3 to ITO3 is configured so that the applied potential can be reliably retained. A potential of about 25 [V] is applied to each of the transparent pixel electrodes ITO1 to ITO3 of the selected pixel. At this time, the scanning signal line GL of the next stage is in a non-selected state and is about −20 [V]. Is configured to be applied.

Transparent pixel electrode ITO1 to be overlapped
The scanning signal line GL is provided in a part between each of the ITO3 to the scanning signal line GL of the next stage, similarly to the source electrode SD1.
An island region formed of the first conductive film d1 and the second conductive film d2 is provided so that the transparent pixel electrode ITO will not be broken when overcoming the stepped shape. This island region does not reduce the area (aperture ratio) of the transparent pixel electrode ITO,
Make it as small as possible.

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, according to the present invention, each pixel of the liquid crystal display portion of the liquid crystal display device can be divided into two or four.
However, if the number of divisions of the pixel is too large, the aperture ratio is lowered, and thus, as described above, about 2 to 4 divisions are appropriate.

[0086]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

Point defects and line defects of pixels in the liquid crystal display portion of the liquid crystal display device can be reduced.

[Brief description of drawings]

FIG. 1 is a main part plan view showing one pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device which is Embodiment I of the present invention.

FIG. 2 is a sectional view taken along the line II-II of FIG.

FIG. 3 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 1 are arranged.

4 is a plan view showing a gate electrode GT and a scanning signal line GL of the pixel shown in FIG.

5 is a plan view showing a gate electrode GT and an i-type semiconductor layer AS of the pixel shown in FIG.

6 is a plan view showing a state where a source electrode SD1 and a drain electrode SD2 of the pixel shown in FIG. 1 are completed.

7 is a plan view of a main part in a state where the pixel and the color filter shown in FIG. 3 are overlapped with each other.

FIG. 8 is a main part plan view showing one pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device which is Embodiment II of the present invention.

FIG. 9 is an equivalent circuit diagram showing one pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device according to each of Examples I and II of the present invention.

[Explanation of symbols]

SUB ... Transparent glass substrate, GL ... Scan signal line, DL ... Video signal line, GI ... Insulating film, GT ... Gate electrode, AS ... i
-Type semiconductor layer, SD ... Source electrode or drain electrode, PS
V ... Protective film, LS ... Light-shielding film, LC ... Liquid crystal, TFT ... Thin film transistor, ITO ... Transparent pixel electrode, g, d ... Conductive film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuhiko Kuchida 3300, Hayano, Mobara, Chiba Prefecture, within the Mobara Plant, Hitachi, Ltd. (72) Shinji Matsumoto, 3300, Hayano, Mobara, Chiba, Ltd., within the Mobara Plant, Hitachi, Ltd.

Claims (3)

[Claims] 1. Two adjacent scan signal lines and two adjacent scan signal lines
In a liquid crystal display device having a pixel composed of a thin film transistor and a pixel electrode in an area intersecting with two video signal lines, the thin film transistor is electrically connected to one scanning signal line of the two scanning signal lines. A gate electrode to be connected,
A gate insulating film provided on the gate electrode, a semiconductor layer provided on the gate insulating film, and a source electrode and a drain electrode electrically connected to the semiconductor layer, respectively. One of the drain electrodes is connected to the pixel electrode, the other is electrically connected to one of the two video signal lines, and the scanning signal line is made of a metal different from aluminum. And a second conductive film made of aluminum, and the gate electrode is formed of a single-layer film made of the same conductive film as the first conductive film. One of the two scanning signal lines is scanned. The pixel electrode of the pixel selected by the signal line is one electrode, the electrode electrically connected to the other scanning signal line of the two scanning signal lines is the other electrode, and the one electrode is The other A storage capacitor having a dielectric film between electrodes is formed,
The other electrode is composed of a single-layer film made of the first conductive film, and a conductive film is provided so as to overlap with the one electrode. The conductive film is formed by planarizing the one electrode with the other electrode. A liquid crystal display device, wherein the liquid crystal display device is provided in an island shape in a region overcoming a step. 2. The liquid crystal display device according to claim 1, wherein the second conductive film has a width smaller than that of the first conductive film at least at an intersection with the scanning signal line. 3. The liquid crystal display device according to claim 1, wherein the conductive film is formed of the same conductive layer as the video signal line.