JPH02148755A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the thickness of an insulating film out of a through hole without increasing the diameter of the hole and to reduce an interconnection capacity in a semiconductor device having a multilayer interconnection structure by reducing the thickness of an interlayer insulating film on the periphery of the hole as compared with that of the interlayer insulating film of the part having no hole by etching. CONSTITUTION:A plurality, e.g., 2 of through holes 14, 15 are opened in an interlayer insulating film 18, second interconnections 11, 13 passed via the holes 14, 15 are connected to an interconnection 11 of Fig. 1, disposed thereunder, and a second interconnection 12 unnecessary to be connected is disposed only on the film 18. With this structure, the thickness of the film 18 is reduced by isotropically etching near the holes 14, 15, and thin film holes 16, 17 having a size approx. twice-three times as large as the diameters of the holes 14, 15 are formed. Thus, the thickness of the insulating film is reduced near the interconnections 11, 15 to reduce interconnection capacity, thereby improving the propagation speed of a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure of a semiconductor device, and particularly to the structure of a through-hole portion.

BACKGROUND ART Conventionally, as shown in FIG. 3, in the structure of a through-hole portion of a semiconductor device, the thickness of the interlayer insulating film 28 is uniform in the through-hole portions 24 and 25 and in portions other than the through-hole portion. was.

Problems to be Solved by the Invention In general, wiring delay in a semiconductor device is determined by the wiring area, the dielectric constant of the interlayer insulating film, and the thickness of the interlayer insulating film.

Among these, the thickness of the interlayer insulating film becomes -i)X,
On the other hand, when the interlayer film thickness is increased, the wiring capacitance with the upper layer wiring decreases and the current propagation speed of the semiconductor two-layer circuit increases due to wiring delay.On the other hand, when the interlayer film thickness is increased, the through hole for connecting the upper layer wiring and the lower layer wiring increases. If the diameter is not increased, the through-hole resistance will increase, and the propagation speed will not be improved by increasing the thickness of the interlayer insulating film.

However, increasing the diameter of the through hole reduces the degree of integration, and the film thickness is ultimately limited to a value commensurate with the diameter of the through hole determined from the degree of integration.

The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to solve the above-mentioned problems inherent in the conventional technology, and to provide a novel semiconductor device that makes it possible to increase the thickness of the interlayer insulating film and reduce the wiring capacitance without increasing the diameter of the through hole. It is about providing.

Difference of the Invention from the Prior Art The semiconductor device of the present invention differs from the conventional semiconductor device described above in that the interlayer insulating film around the through-hole portion is made thinner.

Means for Solving the Problems In order to achieve the above object, a semiconductor device according to the present invention includes:
It has a structure in which the interlayer insulation around the through hole is made thinner and the other parts are made thicker.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

Figure 1 is a pattern diagram (plan view) showing one embodiment of the present invention.
FIG. 2 is a sectional view taken along the line AA' in FIG. 1 and viewed in the direction of the arrow.

Referring to FIGS. 1 and 2, from the first wiring 10 to the second
Connections to wiring 11 and 13 are through holes 14 and 15.
It is done through.

Thin film holes 16 and 17, which are essential parts of the present invention, are opened around the through holes 14 and 15.

That is, the through-hole portion is formed by isotropic etching into a thin film hole 16.17 that is about 2 to 3 times larger than the diameter of the through hole 14.15 and does not reach the first wiring IO. After reducing the thickness, through holes 14, 15 similar to conventional through holes are drilled.

As described in detail, according to the present invention, by thinning the interlayer insulating film around the through-hole portion, the thickness of the interlayer insulating film can be increased without increasing the through-hole diameter, and the wiring capacitance can be increased. This has the effect of reducing

[Brief explanation of the drawing]

(Figure 1 is a plan view of a pattern showing one embodiment of the present invention)
, FIG. 2 is a sectional view taken along the line AA' in FIG. 1 and viewed in the direction of the arrow, and FIG. 3 is a sectional view showing an example of the conventional technique. 10.20...first wiring, 11.12.13.21
．． 22.23...Second wiring, 14.15.24.2
5...Through hole, 16.17...Thin film hole, 18.28...Interlayer insulating film patent applicant NEC Co., Ltd. representative Patent attorney Yutabe Kumagai

Claims (1)

[Claims] 1. A semiconductor device having a multilayer wiring structure, characterized in that an interlayer insulating film around a through-hole portion has a thin structure.