JPH0212055B2 - - Google Patents

Info

Publication number
JPH0212055B2
JPH0212055B2 JP56177413A JP17741381A JPH0212055B2 JP H0212055 B2 JPH0212055 B2 JP H0212055B2 JP 56177413 A JP56177413 A JP 56177413A JP 17741381 A JP17741381 A JP 17741381A JP H0212055 B2 JPH0212055 B2 JP H0212055B2
Authority
JP
Japan
Prior art keywords
latch circuit
transmission gate
unit latch
input
racing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56177413A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5879328A (ja
Inventor
Hiromasa Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56177413A priority Critical patent/JPS5879328A/ja
Publication of JPS5879328A publication Critical patent/JPS5879328A/ja
Publication of JPH0212055B2 publication Critical patent/JPH0212055B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
JP56177413A 1981-11-04 1981-11-04 マスタ・スレ−ブ形ラツチ回路 Granted JPS5879328A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56177413A JPS5879328A (ja) 1981-11-04 1981-11-04 マスタ・スレ−ブ形ラツチ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56177413A JPS5879328A (ja) 1981-11-04 1981-11-04 マスタ・スレ−ブ形ラツチ回路

Publications (2)

Publication Number Publication Date
JPS5879328A JPS5879328A (ja) 1983-05-13
JPH0212055B2 true JPH0212055B2 (enrdf_load_stackoverflow) 1990-03-16

Family

ID=16030485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56177413A Granted JPS5879328A (ja) 1981-11-04 1981-11-04 マスタ・スレ−ブ形ラツチ回路

Country Status (1)

Country Link
JP (1) JPS5879328A (enrdf_load_stackoverflow)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60189136U (ja) * 1984-05-28 1985-12-14 日本電気株式会社 ラツチ回路
FR2578125B1 (fr) * 1985-02-28 1987-04-10 Efcis Bascule bistable statique en technologie cmos
JPH088473B2 (ja) * 1986-05-06 1996-01-29 松下電器産業株式会社 相補形ｄ形フリツプフロツプ回路
DE3863731D1 (de) * 1987-09-17 1991-08-22 Siemens Ag Synchronisier-flipflop-schaltungsanordnung.
JP2946658B2 (ja) * 1990-06-29 1999-09-06 日本電気株式会社 フリップフロップ回路
US5130568A (en) * 1990-11-05 1992-07-14 Vertex Semiconductor Corporation Scannable latch system and method
US5789956A (en) * 1995-05-26 1998-08-04 Texas Instruments Incorporated Low power flip-flop

Also Published As

Publication number Publication date
JPS5879328A (ja) 1983-05-13

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