JPH02105449A - 半導体装置用リードフレーム - Google Patents

半導体装置用リードフレーム

Info

Publication number
JPH02105449A
JPH02105449A JP63258673A JP25867388A JPH02105449A JP H02105449 A JPH02105449 A JP H02105449A JP 63258673 A JP63258673 A JP 63258673A JP 25867388 A JP25867388 A JP 25867388A JP H02105449 A JPH02105449 A JP H02105449A
Authority
JP
Japan
Prior art keywords
island
lead frame
semiconductor device
semiconductor element
island part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63258673A
Other languages
English (en)
Inventor
Kiyoshi Tsuji
辻　清志
Seiichi Nishino
西野　誠一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63258673A priority Critical patent/JPH02105449A/ja
Publication of JPH02105449A publication Critical patent/JPH02105449A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用リードフレームに関し、特に樹脂
封止型の半導体装置用リードフレームに関する。
〔従来の技術〕
従来、樹脂封止型の半導体装置用リードフレームは、Ｆ
ｅ−Ｎｉ合金やＣｕ材をプレス法又は、エツチング法に
て型抜きされ、その板厚は一般的に０．１５〜０．３＋
ａｍである。
〔発明が解決しようとする課題〕
上述した従来のリードフレームは、半導体素子搭載用の
アイランド部表面が平坦かつ滑らかな構造を有している
為、半導体用接着材とアイランド部との密着性が悪く、
多少の振動や衝撃によって接着界面にひびが入ったり、
界面がら剥がれるどう欠点がある。
〔課題を解決するための手段〕
本発明の半導体装置用リードフレームは、半導体素子搭
載用のアイランド部表面が多数の溝によって仕切られた
複数の凸部からなる。
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
。
第１図（ａ）及び（ｂ）はそれぞれ本発明の第１の実施
例のアイランド部の斜視図及びＡ−Ａ’線断面図である
。
この実施例のアイランド部は、表面に、既存のエツチン
グ法（ハーフエツチング法）により形成された行と列に
直交する多数の溝によって仕切られた面積３〜５　ｍｎ
ｆで高さ２０〜６０μｍの複数の凸部が形成されである
。
ここで、凸部のサイズは、表面積３−〜５−で高さは２
０μｍ〜６０μｍがよい。これよりサイズが大きいと、
アイランド部と銀ペーストとの界面でクラックが発生し
易くなり、又、サイズを小さ目にすると効果があまり望
めなくなる。
又、従来構造のリードフレームと本実施例との、アイラ
ンド部へ素子を搭載した場合の密着強度を比較してみる
と従来構造では８〜１０ｋｇであるが、本実施例では１
２〜１５ｋｇであった。
第２図は本実施例を使った半導体装置の断面図である。
この半導体装置は、アイランド部６の上に半導体素子４
を樹脂銀ペースト５を介して固着し、金属細線２でリー
ド部３へ電気的に接続し、これらを覆うように封止樹脂
１が設けられる。
第３図（ａ）及び（ｂ）はそれぞれ本発明の第２の実施
例のアイランド部の斜視図、及びＢ−Ｂ′線断面図であ
る。
この実施例の凸部７′の形成法としては、リードフレー
ムのアイランド部表面へ部分的にマスクを施しメツキ法
により凸部を形成する方法がある。この実施例の形成法
に於いてはＣｕメツキやＮｉメツキは析出速度が速いの
で好ましい。
その他、スクリーン印刷法を用いてガラスペーストで凸
部を形成する方法がある。
これらの方法によれば、リードフレームをプレスで作っ
た後に凸部を形成できるので安価に出来る利点がある。
又、メツキによる析出法で凸部を形成すると、凸部の形
状がきのこ型になるので、接着部のくさび効果によって
接着強度はより大きくなる。
更に又、本発明では、凸部の形状は、特に限定されず、
四角柱、三角柱１円柱、六角柱等、いすに於いても効果
がある。
〔発明の効果〕
以上説明した様に本発明は、ハーフエツチング法やメツ
キ法、スクリーン印刷法等によってリードフレームのア
イランド部表面に多数の凸部を形成する事により、接着
材との接着面積を増加させ半導体素子とアイランド部と
の密着性が向上するという効果がある。
／ ７凸が
【図面の簡単な説明】
第１図（ａ）及び（ｂ）はそれぞれ本発明の第１の実施
例のアイランド部の斜視図及びＡ−Ａ’線線断断面図第
２図は本実施例を使った半導体装置の断面図、第３図（
ａ＞及び（ｂ）はそれぞれ本発明の第２実施例のアイラ
ンド部の斜視面図、及びＢ−Ｂ’’断面図である。 １・・・封止樹脂、２・・・金属細線、３・・・リード
部、４・・・半導体素子、５・・・樹脂銀ペースト、６
・・・アイランド部、７，７′・・・凸部。 気　　１　　図 男　２　図

Claims (1)

    【特許請求の範囲】
  1. 半導体素子搭載用のアイランド部表面が多数の溝によっ
    て仕切られた複数の凸部からなることを特徴とする半導
    体装置用リードフレーム。
JP63258673A 1988-10-13 1988-10-13 半導体装置用リードフレーム Pending JPH02105449A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63258673A JPH02105449A (ja) 1988-10-13 1988-10-13 半導体装置用リードフレーム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63258673A JPH02105449A (ja) 1988-10-13 1988-10-13 半導体装置用リードフレーム

Publications (1)

Publication Number Publication Date
JPH02105449A true JPH02105449A (ja) 1990-04-18

Family

ID=17323512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63258673A Pending JPH02105449A (ja) 1988-10-13 1988-10-13 半導体装置用リードフレーム

Country Status (1)

Country Link
JP (1) JPH02105449A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106498A (ja) * 1993-10-05 1995-04-21 Nec Corp 樹脂封止型半導体装置用リードフレームとその製造方法 および樹脂封止型半導体装置
WO2001059828A2 (de) * 2000-02-14 2001-08-16 Epcos Ag Bauelement mit konstant verspannter verklebung und verfahren zur verklebung
DE10139681A1 (de) * 2001-08-11 2003-03-06 Infineon Technologies Ag Bauelement mit einem auf einem Träger montierten Halbleiterkörper
JP2007134394A (ja) * 2005-11-08 2007-05-31 Rohm Co Ltd 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106498A (ja) * 1993-10-05 1995-04-21 Nec Corp 樹脂封止型半導体装置用リードフレームとその製造方法 および樹脂封止型半導体装置
WO2001059828A2 (de) * 2000-02-14 2001-08-16 Epcos Ag Bauelement mit konstant verspannter verklebung und verfahren zur verklebung
WO2001059828A3 (de) * 2000-02-14 2002-02-28 Epcos Ag Bauelement mit konstant verspannter verklebung und verfahren zur verklebung
DE10139681A1 (de) * 2001-08-11 2003-03-06 Infineon Technologies Ag Bauelement mit einem auf einem Träger montierten Halbleiterkörper
JP2007134394A (ja) * 2005-11-08 2007-05-31 Rohm Co Ltd 半導体装置

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