JPH0191439A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0191439A
JPH0191439A JP15223987A JP15223987A JPH0191439A JP H0191439 A JPH0191439 A JP H0191439A JP 15223987 A JP15223987 A JP 15223987A JP 15223987 A JP15223987 A JP 15223987A JP H0191439 A JPH0191439 A JP H0191439A
Authority
JP
Japan
Prior art keywords
layer
nitride film
pad
semiconductor device
plasma nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15223987A
Other languages
English (en)
Other versions
JP2694252B2 (ja
Inventor
Yutaka Saito
豊 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP62152239A priority Critical patent/JP2694252B2/ja
Publication of JPH0191439A publication Critical patent/JPH0191439A/ja
Application granted granted Critical
Publication of JP2694252B2 publication Critical patent/JP2694252B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線を有する半導体装置の眉間絶縁層の構
造及び１！極用パツドの形成に関する。
〔発明の概要〕
本発明は半導体装置にかかり、とくに能動領域上にワイ
ヤーボンディング用パッドの形成を可能としたものであ
る。
〔従来の技術〕
従来、能動領域上に電極を有する半導体装置としては眉
間にポリマー系の樹脂材や気相成長酸化膜等を使用して
おり、バンプ電極を形成したものなどは実用化されてい
た。しかし、ワイヤーボンディング用のバンドとしては
、ボンディング時のダメージ等に耐えられず、実用化は
されていない。
〔発明が解決しようとする問題点〕
ワイヤーボンディングやテスターでのブロービングに充
分耐えられる、素子の劣化のない眉間絶縁層の形成が課
題であった。また、単に層間絶縁層の厚みを増やしただ
けでは、強度はでるが第１層目の配線と第２層目の配線
を接続するコンタクトホール、以下これをスルーホール
と称する、において第２層目の配線用Ａ２が断線すると
いう問題があった。
〔問題点を解決するための手段〕
前記問題点を解決するため本発明は層間絶縁層の構造を
第１層目をプラズマ窒化膜、第２層目を気相成長酸化膜
、第３層目を不純物を導入した気相成長酸化膜とからな
る３層積層構造とした。
〔作用〕
前記のようにプラズマ窒化膜の上に気相成長酸化膜を積
層することで、ワイヤーボンディングやブロービングに
も耐えうる充分な強度が得られる。
又、第３層目に不純物を導入した気相成長酸化膜を積層
することで、スルーホールのエツチング時にテーパーが
つき、第２層Ａ１のステップカバーの良好なものが得ら
れる。
〔実施例〕
第１図が本発明の半導体装置の断面図である。
第１図でわかるように基板１上の１層目ＡＡＺ上に中間
絶縁層Ｐ−ＳｉＮ３とＮ５Ｇ４とを形成し、その上層に
２層目Ａ１６を形成し能動領域上にパッド開花部１０を
得ている。
第２図はスルーホール部の拡大図である。層間絶縁膜は
まずプラズマ窒化膜３をデボし、写真食刻法にてスルー
ホールのバターニングを行う、この際、プラズマ窒化膜
３は充分オーバーエッチさせると良好なテーパー角７が
得られる。次にＮ５Ｇ３をデボし、続いてＰＳＧ４をデ
ボする。その後、やはり写真食刻法にて再度バターニン
グとエツチングを行うと良好なテーパー角８が得られる
。
〔発明の効果〕
本発明は以上説明したように、能動領域上へのパッド形
成を可能としたものであり、素子の高集積化や半導体装
置サイズの縮小化や実装の自由変向上等が図れる。
【図面の簡単な説明】
第１図は本発明を用いた半導体装置の断面図、第２図は
本発明を用いて作られたスルーホール部の拡大断面図で
ある。 １・・・Ｓｉ基板 ２・・・１層目Ａｊ！配線層 ３・・・プラズマ窒化膜 ４・・・ＣＶＤで作られたＮ５Ｃ ５・・・ＣＶＤで作られたＰＳＧ ６・・・２層目Ａｆ配線 ７・・・最終パシベーション膜 ８・・・プラズマ窒化膜開孔部のテーバ９・・・ＣＶＤ
で作られたＮＳＧ及びＰＳＧ膜開孔開孔部−バ １０・・・パッド開花部 以上 出願人　セイコー電子工業株式会社 本光Ｂハの半導イ本表置の断面図 第　１　図 本発Ｂ月の半導体装置のスルーホール部の杯↑面図第　
２　図 手続補正書動ヱ０　　在 昭和／３年／７月ｌダロ

Claims (2)

    【特許請求の範囲】
  1. （１）多層配線構造を有する半導体装置において、層間
    絶縁膜が第１層目プラズマ窒化膜、第２層目気相成長酸
    化膜、第３層目不純物を導入した気相成長酸化膜とを有
    する３層積層構造となっていることを特徴とする半導体
    装置。
  2. （２）前記層間絶縁層を有する半導体装置において、能
    動領域上に電極用パッドを有することを特徴とする特許
    請求の範囲第１項記載の半導体装置。
JP62152239A 1987-06-18 1987-06-18 半導体装置 Expired - Lifetime JP2694252B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62152239A JP2694252B2 (ja) 1987-06-18 1987-06-18 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62152239A JP2694252B2 (ja) 1987-06-18 1987-06-18 半導体装置

Publications (2)

Publication Number Publication Date
JPH0191439A true JPH0191439A (ja) 1989-04-11
JP2694252B2 JP2694252B2 (ja) 1997-12-24

Family

ID=15536130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62152239A Expired - Lifetime JP2694252B2 (ja) 1987-06-18 1987-06-18 半導体装置

Country Status (1)

Country Link
JP (1) JP2694252B2 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0384927A (ja) * 1989-08-29 1991-04-10 Nec Corp 半導体装置の製造方法
US6441467B2 (en) 1997-04-24 2002-08-27 Sharp Kabushiki Kaisha Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56153751A (en) * 1980-04-28 1981-11-27 Nec Corp Semiconductor device
JPS57149752A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Structure of multilayer wiring
JPS60154625A (ja) * 1984-01-25 1985-08-14 Hitachi Ltd 多層絶縁膜のスルホ−ル形成方法
JPS61196552A (ja) * 1985-02-26 1986-08-30 Nec Corp 半導体集積回路装置
JPS6232617A (ja) * 1985-08-02 1987-02-12 Matsushita Electronics Corp 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56153751A (en) * 1980-04-28 1981-11-27 Nec Corp Semiconductor device
JPS57149752A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Structure of multilayer wiring
JPS60154625A (ja) * 1984-01-25 1985-08-14 Hitachi Ltd 多層絶縁膜のスルホ−ル形成方法
JPS61196552A (ja) * 1985-02-26 1986-08-30 Nec Corp 半導体集積回路装置
JPS6232617A (ja) * 1985-08-02 1987-02-12 Matsushita Electronics Corp 半導体装置およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0384927A (ja) * 1989-08-29 1991-04-10 Nec Corp 半導体装置の製造方法
US6441467B2 (en) 1997-04-24 2002-08-27 Sharp Kabushiki Kaisha Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film
US6650002B1 (en) 1997-04-24 2003-11-18 Sharp Kabushiki Kaishi Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film
US6864562B1 (en) 1997-04-24 2005-03-08 Sharp Kabushiki Kaisha Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film

Also Published As

Publication number Publication date
JP2694252B2 (ja) 1997-12-24

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