JPH0142537B2 - - Google Patents

Info

Publication number
JPH0142537B2
JPH0142537B2 JP58046343A JP4634383A JPH0142537B2 JP H0142537 B2 JPH0142537 B2 JP H0142537B2 JP 58046343 A JP58046343 A JP 58046343A JP 4634383 A JP4634383 A JP 4634383A JP H0142537 B2 JPH0142537 B2 JP H0142537B2
Authority
JP
Japan
Prior art keywords
phase
phase shifter
clock
output
identification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58046343A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59171233A (ja
Inventor
Tadashi Fujino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58046343A priority Critical patent/JPS59171233A/ja
Publication of JPS59171233A publication Critical patent/JPS59171233A/ja
Publication of JPH0142537B2 publication Critical patent/JPH0142537B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58046343A 1983-03-17 1983-03-17 自動クロツク位相設定回路 Granted JPS59171233A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58046343A JPS59171233A (ja) 1983-03-17 1983-03-17 自動クロツク位相設定回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58046343A JPS59171233A (ja) 1983-03-17 1983-03-17 自動クロツク位相設定回路

Publications (2)

Publication Number Publication Date
JPS59171233A JPS59171233A (ja) 1984-09-27
JPH0142537B2 true JPH0142537B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-09-13

Family

ID=12744489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58046343A Granted JPS59171233A (ja) 1983-03-17 1983-03-17 自動クロツク位相設定回路

Country Status (1)

Country Link
JP (1) JPS59171233A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2655454B2 (ja) * 1991-03-28 1997-09-17 日本電気株式会社 アイパターン識別再生回路
US5432480A (en) * 1993-04-08 1995-07-11 Northern Telecom Limited Phase alignment methods and apparatus
KR100458106B1 (ko) 2000-07-10 2004-11-26 인터내셔널 비지네스 머신즈 코포레이션 디지털 신호의 품질을 결정하기 위한 장치 및 방법
JP4196657B2 (ja) 2002-11-29 2008-12-17 株式会社日立製作所 データ再生方法およびデジタル制御型クロックデータリカバリ回路
JP5259074B2 (ja) * 2006-11-10 2013-08-07 株式会社日立製作所 半導体集積回路装置
JP5174493B2 (ja) * 2008-03-06 2013-04-03 株式会社日立製作所 半導体集積回路装置及びアイ開口マージン評価方法
JP5166924B2 (ja) * 2008-03-11 2013-03-21 株式会社日立製作所 信号再生回路
WO2010125610A1 (ja) 2009-04-30 2010-11-04 株式会社アドバンテスト クロック生成装置、試験装置およびクロック生成方法
JP2013219641A (ja) * 2012-04-11 2013-10-24 Mitsubishi Electric Corp データ伝送装置

Also Published As

Publication number Publication date
JPS59171233A (ja) 1984-09-27

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