JPS59171233A - 自動クロツク位相設定回路 - Google Patents

自動クロツク位相設定回路

Info

Publication number
JPS59171233A
JPS59171233A JP58046343A JP4634383A JPS59171233A JP S59171233 A JPS59171233 A JP S59171233A JP 58046343 A JP58046343 A JP 58046343A JP 4634383 A JP4634383 A JP 4634383A JP S59171233 A JPS59171233 A JP S59171233A
Authority
JP
Japan
Prior art keywords
phase shifter
phase
output
circuit
identification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58046343A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0142537B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Tadashi Fujino
藤野　忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58046343A priority Critical patent/JPS59171233A/ja
Publication of JPS59171233A publication Critical patent/JPS59171233A/ja
Publication of JPH0142537B2 publication Critical patent/JPH0142537B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58046343A 1983-03-17 1983-03-17 自動クロツク位相設定回路 Granted JPS59171233A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58046343A JPS59171233A (ja) 1983-03-17 1983-03-17 自動クロツク位相設定回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58046343A JPS59171233A (ja) 1983-03-17 1983-03-17 自動クロツク位相設定回路

Publications (2)

Publication Number Publication Date
JPS59171233A true JPS59171233A (ja) 1984-09-27
JPH0142537B2 JPH0142537B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-09-13

Family

ID=12744489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58046343A Granted JPS59171233A (ja) 1983-03-17 1983-03-17 自動クロツク位相設定回路

Country Status (1)

Country Link
JP (1) JPS59171233A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04301942A (ja) * 1991-03-28 1992-10-26 Nec Corp アイパターン識別再生回路
WO1994024792A1 (en) * 1993-04-08 1994-10-27 Northern Telecom Limited Phase alignment methods and apparatus
US7016403B2 (en) 2000-07-10 2006-03-21 International Business Machines Corporation Apparatus and method for determining the quality of a digital signal
JP2008124714A (ja) * 2006-11-10 2008-05-29 Hitachi Ltd 半導体集積回路装置
US7474720B2 (en) 2002-11-29 2009-01-06 Hitachi, Ltd. Clock and data recovery method and digital circuit for the same
JP2009212992A (ja) * 2008-03-06 2009-09-17 Hitachi Ltd 半導体集積回路装置及びアイ開口マージン評価方法
JP2009218946A (ja) * 2008-03-11 2009-09-24 Hitachi Ltd 信号再生回路
JP5232913B2 (ja) * 2009-04-30 2013-07-10 株式会社アドバンテスト クロック生成装置、試験装置およびクロック生成方法
JP2013219641A (ja) * 2012-04-11 2013-10-24 Mitsubishi Electric Corp データ伝送装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04301942A (ja) * 1991-03-28 1992-10-26 Nec Corp アイパターン識別再生回路
WO1994024792A1 (en) * 1993-04-08 1994-10-27 Northern Telecom Limited Phase alignment methods and apparatus
US5432480A (en) * 1993-04-08 1995-07-11 Northern Telecom Limited Phase alignment methods and apparatus
US7016403B2 (en) 2000-07-10 2006-03-21 International Business Machines Corporation Apparatus and method for determining the quality of a digital signal
US7474720B2 (en) 2002-11-29 2009-01-06 Hitachi, Ltd. Clock and data recovery method and digital circuit for the same
JP2008124714A (ja) * 2006-11-10 2008-05-29 Hitachi Ltd 半導体集積回路装置
JP2009212992A (ja) * 2008-03-06 2009-09-17 Hitachi Ltd 半導体集積回路装置及びアイ開口マージン評価方法
JP2009218946A (ja) * 2008-03-11 2009-09-24 Hitachi Ltd 信号再生回路
JP5232913B2 (ja) * 2009-04-30 2013-07-10 株式会社アドバンテスト クロック生成装置、試験装置およびクロック生成方法
US8897395B2 (en) 2009-04-30 2014-11-25 Advantest Corporation Clock generating apparatus, test apparatus and clock generating method
JP2013219641A (ja) * 2012-04-11 2013-10-24 Mitsubishi Electric Corp データ伝送装置

Also Published As

Publication number Publication date
JPH0142537B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-09-13

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