JPH01218095A - High density multilayer wiring board - Google Patents
High density multilayer wiring boardInfo
- Publication number
- JPH01218095A JPH01218095A JP4501988A JP4501988A JPH01218095A JP H01218095 A JPH01218095 A JP H01218095A JP 4501988 A JP4501988 A JP 4501988A JP 4501988 A JP4501988 A JP 4501988A JP H01218095 A JPH01218095 A JP H01218095A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide film
- layer
- filler polyimide
- filler
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000945 filler Substances 0.000 claims abstract description 33
- 229920001721 polyimide Polymers 0.000 claims abstract description 33
- 239000004094 surface-active agent Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract 8
- 239000011229 interlayer Substances 0.000 claims abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000004642 Polyimide Substances 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 230000000630 rising effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 10
- 238000004528 spin coating Methods 0.000 description 4
- 230000008961 swelling Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高密度多層配線基板に関し、特にコンピュータ
等電子機器に使用されるLSI実装用高密度多層配線基
板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-density multilayer wiring board, and particularly to a high-density multilayer wiring board for LSI mounting used in electronic devices such as computers.
従来、この種の高密度多層配線基板の眉間絶縁層は、第
2図に示されるように、通常のフィラーポリイミド膜の
みからなる有機絶縁層が使用されており、電気的絶縁性
のために2層以上繰返し形成されていた。第2図を参照
すると、基板1と下層配線パターン2の表面にSiO2
などが含まれ耐クラツク性にすぐれているフィラーポリ
イミド膜3が2層で20〜30μ形成されていた。Conventionally, the insulating layer between the eyebrows of this type of high-density multilayer wiring board has been an organic insulating layer consisting only of an ordinary filler polyimide film, as shown in Fig. 2. More than one layer was formed repeatedly. Referring to FIG. 2, SiO2 is formed on the surfaces of the substrate 1 and the lower wiring pattern 2.
The filler polyimide film 3, which contains the following materials and has excellent crack resistance, was formed in two layers with a thickness of 20 to 30 μm.
ところが、第2図のように通常のフィラーポリイミドを
スピンコーティングすると厚塗りの膜が必要な場合、基
板端部の膜が盛り上り、基板端部の現像性が著しく悪く
なり、現像時にビィアホールの抜は残りの発生原因とな
り、第3図のように界面活性剤入りフィラーポリイミド
をスピンコーティングすると、基板端部の盛り上りは大
幅になくなるが、現像時にビィアホールの底が抜けない
という欠点がある。However, as shown in Figure 2, when a thick film is required when spin-coating ordinary filler polyimide, the film swells up on the edges of the substrate, significantly worsening the developability of the edges of the substrate, and making it difficult to pull out via holes during development. is the cause of the residual formation, and spin-coating a surfactant-containing filler polyimide as shown in FIG. 3 largely eliminates the swelling at the edge of the substrate, but has the disadvantage that the bottom of the via hole cannot be removed during development.
本発明による高密度多層配線基板は、多層配線基板の眉
間絶縁層が第1層目にフィラーポリイミド膜、そして第
2層目に界面活性剤入りフィラーポリイミド膜との組合
せ構造を有し、スピンコーティングによる基板端部の盛
り上りを防ぎ、平坦な膜ができるため、現像性、耐クラ
ック性、絶縁性に優れていることを特徴としている。In the high-density multilayer wiring board according to the present invention, the glabellar insulating layer of the multilayer wiring board has a combination structure in which the first layer is a filler polyimide film and the second layer is a surfactant-containing filler polyimide film, and spin coating is applied. It is characterized by excellent developability, crack resistance, and insulation properties because it prevents the edges of the substrate from bulging and forms a flat film.
次に、本発明の一実施例について、図面を参照にして説
明する。Next, an embodiment of the present invention will be described with reference to the drawings.
第1図を参照すると、基板1と下層配線パターン2の表
面に第1層目にSiO2を含むフィラーポリイミド膜3
、そして、第2層目に界面活性剤入りフィラーポリイミ
ド膜4の眉間絶縁層が形成されている。このように形成
された高密度多層配線基板によると、基板端部の盛り上
りを防ぎ、平坦な膜ができるため、現像性、耐クラツク
性に優れた眉間絶縁層が可能となる。Referring to FIG. 1, a filler polyimide film 3 containing SiO2 in the first layer is formed on the surface of the substrate 1 and the lower wiring pattern 2.
, and a glabellar insulating layer of a surfactant-containing filler polyimide film 4 is formed as the second layer. According to the high-density multilayer wiring board formed in this way, swelling at the edges of the board can be prevented and a flat film can be formed, thereby making it possible to form a glabellar insulating layer with excellent developability and crack resistance.
第4図(a)〜(e)を参照すると、第1図の絶縁層の
構造の一製造方法が示されている。まず、基板1上に下
層配線パターン2が形成されている(第4図(a))。Referring to FIGS. 4(a) to 4(e), one method of manufacturing the structure of the insulating layer of FIG. 1 is shown. First, a lower wiring pattern 2 is formed on a substrate 1 (FIG. 4(a)).
この裏面全面に、第1N目にフィラーポリイミド膜3′
、そして、第2層目に界面活性剤入りフィラーポリイミ
ド膜4′をスピンコーティングし、低温乾燥する(第4
図(b))。従って、この状態ではフィラーポリイミド
膜3″及び界面活性剤入りフィラーポリイミド膜4′は
イミド化していない。Filler polyimide film 3' is applied to the entire back surface at the 1N position.
Then, a surfactant-containing filler polyimide film 4' is spin-coated as the second layer and dried at low temperature (fourth layer).
Figure (b)). Therefore, in this state, the filler polyimide film 3'' and the surfactant-containing filler polyimide film 4' are not imidized.
そしてフィラーポリイミド膜3′での基板端部の盛り上
りを第2層目の界面活性剤入りフィラーポリイミド膜4
′で基板端部の盛り上りを防ぐ。Then, the bulge at the edge of the substrate on the filler polyimide film 3' is replaced with a second layer of surfactant-containing filler polyimide film 4.
' to prevent the edges of the board from swelling.
次に、ガラスマスク5を通して紫外線露光し、低温乾燥
する(第4図(C))。次に、現像すると、紫外線が照
射されない部分が除去される(第4図(D))。最後に
、上記乾燥状態のイミド化されていないフィラーポリイ
ミド膜3及び界面活性剤入りポリイミド膜4をキュアし
てイミド化させる(第4図(e))。Next, it is exposed to ultraviolet light through a glass mask 5 and dried at a low temperature (FIG. 4(C)). Next, when it is developed, the portions that are not irradiated with ultraviolet rays are removed (FIG. 4(D)). Finally, the dry unimidized filler polyimide film 3 and surfactant-containing polyimide film 4 are cured and imidized (FIG. 4(e)).
以上説明したように本発明は、高密度多層配線基板の眉
間絶縁層の構造を、第1層目にフィラーポリイミド膜そ
して第2層目に界面活性剤入りフィラーポリイミド膜と
の組合せをすることにより、スピンコーティングによる
基板端部の盛り上りを防ぎ、現像性、耐クラツク性に優
れた眉間絶縁層を形成できる効果がある。As explained above, the present invention combines the structure of the glabella insulating layer of a high-density multilayer wiring board with a filler polyimide film as the first layer and a surfactant-containing filler polyimide film as the second layer. This has the effect of preventing swelling at the edge of the substrate due to spin coating and forming a glabellar insulating layer with excellent developability and crack resistance.
第1図は本発明による絶縁層の構造の一実施例を示した
断面図、第2図は絶縁層の構造の他の一例を示した断面
図、第3図(a)〜(e)は第1図の絶縁層の構造の一
製造方法を示した断面図、第4図は従来の絶縁層の構造
の一例を示した断面図である。
1・・・基板、2・・・配線パターン、3・・・フィラ
ーポリイミド膜、3′・・・イミド化してないフィラー
ポリイミド膜、4・・・界面活性剤入りフィラーポリイ
ミド膜、4′・・・イミド化してない界面活性剤入りフ
ィラーポリイミド膜、5・・・ガラスマスク。FIG. 1 is a cross-sectional view showing one embodiment of the structure of the insulating layer according to the present invention, FIG. 2 is a cross-sectional view showing another example of the structure of the insulating layer, and FIGS. 3(a) to (e) are FIG. 1 is a cross-sectional view showing one method of manufacturing the insulating layer structure, and FIG. 4 is a cross-sectional view showing an example of the conventional insulating layer structure. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Wiring pattern, 3... Filler polyimide film, 3'... Filler polyimide film that is not imidized, 4... Filler polyimide film containing surfactant, 4'... - Filler polyimide film containing surfactant that is not imidized, 5...Glass mask.
Claims (3)
して、第2層目に界面活性剤入りフィラーポリイミド膜
との組合せを有することを特徴とする高密度多層配線基
板。1. A high-density multilayer wiring board characterized in that an interlayer insulating layer has a combination of a filler polyimide film as a first layer and a surfactant-containing filler polyimide film as a second layer.
_2である請求項1記載の高密度多層配線基板。2. The filler component of the filler polyimide film is SiO
The high-density multilayer wiring board according to claim 1, which is _2.
ィラーポリイミド膜が感光性フィラーポリイミド膜およ
び感光性界面活性剤入りフィラーポリイミド膜である請
求項1記載の高密度多層配線基板。3. 2. The high-density multilayer wiring board according to claim 1, wherein the filler polyimide film and the surfactant-containing filler polyimide film are a photosensitive filler polyimide film and a photosensitive surfactant-containing filler polyimide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4501988A JPH01218095A (en) | 1988-02-26 | 1988-02-26 | High density multilayer wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4501988A JPH01218095A (en) | 1988-02-26 | 1988-02-26 | High density multilayer wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01218095A true JPH01218095A (en) | 1989-08-31 |
Family
ID=12707633
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4501988A Pending JPH01218095A (en) | 1988-02-26 | 1988-02-26 | High density multilayer wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01218095A (en) |
-
1988
- 1988-02-26 JP JP4501988A patent/JPH01218095A/en active Pending
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