JPS6220399A - Formation of multilayer interconnection - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a method for forming multilayer wiring using an interlayer insulating film having a two-layer laminated structure of photosensitive heat-resistant resin. The method of forming multilayer interconnections is an important technology that influences the improvement of the degree of integration and performance of semiconductor devices and thin film devices. [Background of the Invention] -1: When forming multilayer wiring, in the conventional method, as shown in the figure, a first wiring layer 2 of aluminum or the like is formed on a substrate 1, and a polyimide layer is formed on top of the first wiring layer 2. An interlayer insulating layer 3 is formed. Next, through holes 4 are formed in this insulating layer by first etching, and a second wiring layer is formed through the through holes.In the above conventional method, as shown in the figure, the insulating layer When forming through-holes by etching 3-4-, an exposed portion 6 of the substrate base is generated due to positional deviation of the through-hole, variation in dimensions, etc., and the boundary 7 of the insulating layer base is formed.
There is a problem that the withstand voltage deteriorates and the reliability decreases. Therefore, in the past, as a method of preventing the substrate base exposed portion 6, a band larger than the diameter of the through hole was formed in the through hole portion of the first wiring layer as shown in the figure, but this method reduces the degree of integration of multilayer wiring. There was a problem. On the other hand, there is a method as shown in the figure described in Japanese Patent Application Laid-Open No. 59-36943. In this method, an insulating layer is formed from a heat-resistant resin layer 3 and a photosensitive heat-resistant resin layer 8 to prevent an exposed portion 6 of the substrate base shown in the figure. However, in this method, since different resins are used for the insulating layer, the adhesion reliability between the resin layers decreases, and since the diameter 4 of the through balls is increased, the dimensions of the adjacent first wiring layer 9 and second wiring layer 5 No consideration was given to the fact that there would be no margin for this, which would reduce the degree of integration of multilayer wiring, and that the two-layer structure of the insulating layer would increase the number of work steps. A related technique is JP-A-59-3FI943. [Object of the Invention] An object of the present invention is to provide a method for forming multilayer wiring that allows high integration and requires a small number of steps. [Summary of the Invention] In order to achieve the above object, the present invention sets the wiring width and the through-hole diameter to be the same size so that high integration can be achieved in any wiring layer of multilayer wiring, and the through-hole diameter can be adjusted without variation. By making the insulating layer a two-layer structure made of the same photosensitive heat-resistant resin, even when the size of This is a method of forming wiring. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to cross-sectional views of main process parts shown in FIGS. 1 to 4. In FIG. 1, a thin film of metal such as aluminum with a thickness of about 1βm is formed on a semiconductor substrate 1+ by ordinary sputtering or vapor deposition, a first wiring layer 2 is formed by ordinary photoetching, and a photosensitive ml heat-resistant resin is formed. layer 10 and

[For example, Photo
-PAL (manufactured by Hitachi Chemical Co., Ltd.) is used to pre-bake (85° C., 15 minutes) after application. Next, as shown in FIG. 2, the thickness of the first wiring layer is reduced by development until the surface of the first wiring layer is exposed, and then thermal processing is carried out at 180 DEG C. for 30 minutes. If patterning is required in this process, patterning at 100 m, y/cd (
At 365 +am), the current 1#!
I do. It should be noted that since the Photo-PAL Ii exposed area is also characterized by a large reduction in the developed film on the surface side, it has the advantage that the first wiring layer can be exposed and the required patterning can be done at the same time. Next, as shown in FIG.
Pre-bake for 5 minutes and apply 100% through a photomask.
Through holes 4 are formed by exposure to light of m J/ctl (at 365 degrees) and development. At this time, since the photosensitive heat-resistant resin layer 10 is temporarily coated, it is insoluble in the current liquid, and even if the photosensitive heat-resistant resin layer 10 is exposed due to the positional shift of the through holes, no film loss will occur. A step cure is performed, and heat treatment is performed for 60 minutes in N2 at a final treatment temperature of 400° C. to harden the photosensitive heat-resistant resin layer 10.11. Next, as shown in FIG. 4, a second wiring layer 5 is formed using a metal thin film such as aluminum through the through hole 4. Then, as shown in FIG. According to this embodiment, the first wiring layer 2 is flattened by the photosensitive heat-resistant resin layer 0, and by using the photosensitive heat-resistant resin layer 11, wrinkles are created in the through holes 4 and the first wiring layer 2 due to dimensional variations. Since there is no need to expose the underlying layer even when the wiring is applied, and there is no need to increase either the through-hole dimension or the first wiring layer dimension, it is possible to achieve high integration of multilayer wiring, and the number of steps can be reduced. [Effects of the Invention] According to the present invention, there is no need to provide a wiring connection pattern larger than the diameter of the through holes in the first wiring layer, and there is no need to make the through holes larger than the first wiring layer. High integration of multilayer wiring becomes possible, and significant effects such as easing through-hole processing accuracy, improving adhesion reliability between two insulating layers, and reducing processing man-hours can be obtained. Note that the present invention is also applicable to multilayer wiring of three or more layers.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 to 4 are cross-sectional views of main steps of an embodiment of the present invention;
FIGS. 5 to 7 are cross-sectional views of main parts obtained by the conventional method. 1... Board 2... First wiring layer 3...
Evidence 1 Thermal resin I@4...Through hole 5...Second wiring layer 6...Board base protrusion 7...Insulating layer F ground boundary 8...Photosensitive heat resistant resin 9...bj・L Netsuki Jli
¥ 10... Photosensitive heat-resistant resin 11... Photosensitive heat-resistant resin

Claims (1)

[Claims] 1. Coat a photosensitive heat-resistant resin on the board on which the first wiring layer is provided, temporarily cure it, then expose it to ultraviolet light, and then develop the surface side of the photosensitive heat-resistant resin layer until the surface of the first wiring layer appears. A process of curing the photosensitive heat resistant resin layer after removing it, further applying a photosensitive heat resistant resin on the substrate and temporarily curing it, providing through holes in the portion of the photosensitive heat resistant resin layer where the first wiring layer is located, and then curing. 1. A method for forming a multilayer wiring, comprising the steps of: forming a second wiring layer thereon, and forming a connection portion via a through hole.