JPH01248597A - Multilayer interconnection board - Google Patents

Multilayer interconnection board

Info

Publication number
JPH01248597A
JPH01248597A JP7714188A JP7714188A JPH01248597A JP H01248597 A JPH01248597 A JP H01248597A JP 7714188 A JP7714188 A JP 7714188A JP 7714188 A JP7714188 A JP 7714188A JP H01248597 A JPH01248597 A JP H01248597A
Authority
JP
Japan
Prior art keywords
layer
film thickness
polyimide film
insulating layer
filler polyimide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7714188A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Tamura
田村 浩悦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7714188A priority Critical patent/JPH01248597A/en
Publication of JPH01248597A publication Critical patent/JPH01248597A/en
Pending legal-status Critical Current

Links

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To avoid crackings developed from the edge of a film thickness measuring window composed of a laminated multilayer structure by a stress or the like by a method wherein a lower insulating layer is always covered with an upper insulating layer. CONSTITUTION:An insulating film thickness measuring window 2 of a multilayer interconnection board 1 is composed of a laminated multilayer structure of insulating layers 4-6. In other words, a first layer filler polyimide film 4 is covered with a second layer filler polyimide film 5 and, further, the second layer filler polyimide film 5 is covered with a third filler polyimide film 6 to form the film thickness measuring window 2. Since the insulating film thickness measuring window 2 of the multilayer interconnection board 1 is composed of the multilayer structure and the lower insulating layer is always covered with the upper insulating layer, crackings from the edge developed by a stress caused by curing or the like can be avoided.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多層配線基板に関し、特にコンピュータ等電
子機器に使用されるLSI実装用高密度度多層配線基板
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer wiring board, and particularly to a high-density multilayer wiring board for LSI mounting used in electronic devices such as computers.

〔従来の技術〕[Conventional technology]

従来、この種の高密度多層配線基板は、通常、膜厚管理
方法の必要から第2図に示されるように、配線パターン
3が設けられた基板1の端面に膜厚測定用窓2′が多層
について重なって設けられ、各膜層(第1層目、第2層
目、第3層目のフィラーポリイミド膜4,5.6)の端
面の位置が一致するように設けられていた。
Conventionally, this type of high-density multilayer wiring board usually has a film thickness measurement window 2' on the end surface of the board 1 on which the wiring pattern 3 is provided, as shown in FIG. 2 due to the need for a film thickness control method. Multiple layers were provided to overlap each other, and the end faces of each film layer (first, second, and third filler polyimide films 4, 5, and 6) were provided in the same position.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、第2図のように、各絶縁層の端面の位置が一
致するように重ねられた膜厚測定用窓の形成方法の場合
、第3図に示す膜厚測定用窓2″のように露光時の位置
ずれが原因で、下層が常に外部にさらされていると、キ
ュア工程にいおいて、サーマルストレス等によりクラッ
クが発生しやすく、配線パターンまでクラックが進行し
、パターンショート、オープンになることがあるという
欠点がある。
However, in the case of the method of forming film thickness measurement windows in which the end faces of each insulating layer are overlapped so that the positions of the end surfaces coincide with each other as shown in FIG. 2, the film thickness measurement windows 2'' shown in FIG. If the lower layer is constantly exposed to the outside due to misalignment during exposure, cracks are likely to occur during the curing process due to thermal stress, etc., and the cracks can progress to the wiring pattern, resulting in pattern shorts and opens. The disadvantage is that it can sometimes happen.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の多層配線基板は、多層について重ねられた膜厚
測定窓において、常に上層の絶縁層が下層の絶縁層を覆
うことを特徴とする。
The multilayer wiring board of the present invention is characterized in that the upper insulating layer always covers the lower insulating layer in the film thickness measurement windows stacked for multiple layers.

〔実施例〕〔Example〕

次に、本発明の一実施例について、図面を参照して詳細
に説明する。
Next, one embodiment of the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例の断面図であり、基板1に、
膜厚7測定用窓2が第1層目にフィラーボt゛ リイミド膜4を第2層目のフィラーポリイミド膜5が覆
い、さらに、第3層目のフィラーポリイミド膜6が覆う
構造で設けられ、端面からのクラック発生の防止が可能
となる、 第4図(a)〜(j)に第1図の絶縁層の膜厚測定窓2
の一製造方法を示す。まず、基板1上に下層配線パター
ン3が形成されている(第4図(a))。この基板1の
表面全面に、フィラーポリイミド膜4をスピンコーティ
ングし、低温乾燥する(第4図(b))。従って、この
状態では、フィラーポリイミド膜はイミド化していない
。次に、ガラスマスク7を通して紫外線露光し、低温乾
燥する(第4図(C))。次に現像すると、紫外線が照
射されない部分が除去され、最後に、上記乾燥状態のイ
ミド化されていないフィラーポリイミド膜4をキュアし
てイミド化させ、第1層目の絶縁膜が形成される(第4
図(d))。
FIG. 1 is a cross-sectional view of an embodiment of the present invention, in which a substrate 1 includes
A film thickness 7 measurement window 2 is provided in a structure in which a first layer of filler polyimide film 4 is covered with a second layer of filler polyimide film 5, and further covered with a third layer of filler polyimide film 6, Figures 4(a) to (j) show the film thickness measurement window 2 of the insulating layer shown in Figure 1, which makes it possible to prevent cracks from occurring from the end face.
One manufacturing method is shown. First, a lower wiring pattern 3 is formed on a substrate 1 (FIG. 4(a)). A filler polyimide film 4 is spin coated over the entire surface of this substrate 1 and dried at low temperature (FIG. 4(b)). Therefore, in this state, the filler polyimide film is not imidized. Next, it is exposed to ultraviolet light through a glass mask 7 and dried at a low temperature (FIG. 4(C)). Next, when development is performed, the portions not irradiated with ultraviolet rays are removed, and finally, the dry unimidized filler polyimide film 4 is cured and imidized to form the first layer of insulating film ( Fourth
Figure (d)).

次に、第2層目のフィラーポリイミドM5を基板表面に
スピンコーティングし、低温乾燥する(第4図(e))
、次にガラスマスク7の膜厚測定窓2に相当する部分の
紫外線透過面積を小さくしたガラスマスク8を通して紫
外線露光し、低温乾燥する(第4図(f))。次に現像
すると膜厚測定用窓2において第2層目のフィラーポリ
イミド膜5が第1層目のフィラーポリイミド膜4を覆い
、キュアすると第2層目の絶縁膜が形成される(第4図
(g))。
Next, a second layer of filler polyimide M5 is spin coated on the substrate surface and dried at low temperature (Fig. 4(e)).
Next, the film is exposed to ultraviolet light through a glass mask 8 whose area corresponding to the film thickness measurement window 2 of the glass mask 7 has a reduced ultraviolet transmission area, and dried at a low temperature (FIG. 4(f)). Next, when developed, the second layer of filler polyimide film 5 covers the first layer of filler polyimide film 4 in the film thickness measurement window 2, and when cured, the second layer of insulating film is formed (Fig. 4). (g)).

次に、第3層目のフィラーポリイミド膜6を基板表面に
スピンコーティングし、低温乾燥する(第4図(h))
。次にガラスマスク8の膜厚測定窓2に相当する部分の
紫外線透過面積を小さくしたガラスマスク9を通して、
紫外線露光し、低温乾燥する(第4図(i))。次に現
像すると、膜厚測定用窓2において第3層目のフィラー
ポリイミド膜6が第2層目のフィラーポリイミド膜5を
覆いキュアすると第3層目の絶縁層が形成される(第4
図(j))。
Next, a third layer of filler polyimide film 6 is spin-coated on the substrate surface and dried at low temperature (Fig. 4 (h)).
. Next, the glass mask 9 is passed through a glass mask 9 which has a small ultraviolet transmission area in the portion corresponding to the film thickness measurement window 2 of the glass mask 8.
It is exposed to ultraviolet light and dried at low temperature (Fig. 4(i)). Next, when development is performed, the third filler polyimide film 6 covers the second filler polyimide film 5 in the film thickness measurement window 2, and when cured, a third insulating layer is formed (the fourth
Figure (j)).

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、多層配線基板の絶縁膜厚
測定用窓が多層重なるような場合、常に上層の絶縁層が
下層の絶縁層を覆う構造にすることにより、キュア等に
よるストレスでの端面からのクラックを防止できる効果
がある。
As explained above, the present invention has a structure in which the upper insulating layer always covers the lower insulating layer when the windows for measuring the insulating film thickness of a multilayer wiring board are stacked in multiple layers, thereby reducing stress caused by curing, etc. This has the effect of preventing cracks from occurring from the end face.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を示した断面図、第2図は
従来の多層配線基板の膜厚測定用窓を示した断面図、第
3図は従来の多層配線基板の製造工程のうちの露光時に
位置ずれがあった場合の膜厚測定用窓を示した断面図、
第4図(a)〜(j)は第1図の実施例の製造方法を工
程順に示した断面図である。 1・・・基板、2・・・膜厚測定用窓、3・・・配線パ
ターン、4・・・第1層目のフィラーポリイミド膜、5
・・・第2層目のフィラーポリイミド膜、6・・・第3
層目のフィラーポリイミド膜、7・・・ガラスマスク、
8・・・ガラスマスク、9・・・ガラスマスク。
FIG. 1 is a cross-sectional view showing an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a film thickness measurement window of a conventional multilayer wiring board, and FIG. 3 is a conventional manufacturing process of a multilayer wiring board. A cross-sectional view showing the film thickness measurement window when there is a positional shift during exposure.
FIGS. 4(a) to 4(j) are cross-sectional views showing the manufacturing method of the embodiment shown in FIG. 1 in the order of steps. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Window for film thickness measurement, 3... Wiring pattern, 4... First layer filler polyimide film, 5
...Second layer filler polyimide film, 6...Third layer
Layer filler polyimide film, 7... glass mask,
8...Glass mask, 9...Glass mask.

Claims (1)

【特許請求の範囲】[Claims] 多層について重ねられた膜厚測定窓において、常に上層
の絶縁層が下層の絶縁層を覆うことを特徴とする多層配
線基板。
A multilayer wiring board characterized in that an upper insulating layer always covers a lower insulating layer in film thickness measurement windows stacked on multiple layers.
JP7714188A 1988-03-29 1988-03-29 Multilayer interconnection board Pending JPH01248597A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7714188A JPH01248597A (en) 1988-03-29 1988-03-29 Multilayer interconnection board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7714188A JPH01248597A (en) 1988-03-29 1988-03-29 Multilayer interconnection board

Publications (1)

Publication Number Publication Date
JPH01248597A true JPH01248597A (en) 1989-10-04

Family

ID=13625526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7714188A Pending JPH01248597A (en) 1988-03-29 1988-03-29 Multilayer interconnection board

Country Status (1)

Country Link
JP (1) JPH01248597A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8696310B2 (en) 2008-11-07 2014-04-15 Consolidated Metco, Inc. Turbo charger housing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8696310B2 (en) 2008-11-07 2014-04-15 Consolidated Metco, Inc. Turbo charger housing

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