JPH03150894A - Managing method for film thickness of multilayer thin film circuit board - Google Patents

Managing method for film thickness of multilayer thin film circuit board

Info

Publication number
JPH03150894A
JPH03150894A JP29077589A JP29077589A JPH03150894A JP H03150894 A JPH03150894 A JP H03150894A JP 29077589 A JP29077589 A JP 29077589A JP 29077589 A JP29077589 A JP 29077589A JP H03150894 A JPH03150894 A JP H03150894A
Authority
JP
Japan
Prior art keywords
film
thickness
film thickness
circuit board
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29077589A
Other languages
Japanese (ja)
Inventor
Masao Hosogai
正男 細貝
Hiroyuki Otaguro
浩幸 太田黒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP29077589A priority Critical patent/JPH03150894A/en
Publication of JPH03150894A publication Critical patent/JPH03150894A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To sufficiently manage the thickness of an insulating film by forming a film thickness checking hole simultaneously when viaholes for connecting between wiring films are formed at the film, and knowing the thickness of the film formed by measuring the depth. CONSTITUTION:Photosensitive organic insulating films 1b and a wiring film 1c are alternately laminated on a power source board 1a. When the films 1b and 1c are alternately laminated, viaholes 1bc for electrically connecting the film 1b to the film 1c are formed, and a film thickness checking hole 1d is simultaneously formed. The depth of the hole 1d, i.e., the thickness of the film 1b is measured in contact with the contact stylus, etc., of a film thickness measuring unit. If the thickness is improper, the improper film 1b is peeled at this time, and the film is reformed. Thus, the thickness of the film 1b can accurately by managed and formed.

Description

【発明の詳細な説明】 〔概要〕 多層薄膜回路基板の膜厚管理方法に関し、絶縁膜の膜厚
を十分に管理することを目的とし、基板上に感光性有機
系の絶縁膜と配線膜を交互に積層してなる多層薄膜回路
基板を製造する工程において、前記絶縁膜に前記配線膜
間を接続するビアホールを形成する際に同時に膜厚チェ
ック用ホールを形成し、該膜厚チェック用ホールの深さ
を測定して膜厚が正常なときは次工程の配線膜形成に進
み、不良のときは剥離し再度、絶縁膜形成工程に戻り積
層を行うように構成する。
[Detailed Description of the Invention] [Summary] Regarding a method for controlling the film thickness of a multilayer thin film circuit board, a photosensitive organic insulating film and a wiring film are formed on the board with the aim of sufficiently controlling the film thickness of the insulating film. In the process of manufacturing a multilayer thin film circuit board formed by alternately laminating layers, a film thickness check hole is formed at the same time as a via hole connecting the wiring films is formed in the insulating film, and the film thickness check hole is The depth is measured, and if the film thickness is normal, the process proceeds to the next step of forming a wiring film, and if it is defective, it is peeled off and the process returns to the insulating film forming process to perform lamination.

〔産業上の利用分野〕[Industrial application field]

本発明は多層薄膜回路基板の絶縁膜厚の管理方法に関す
る。
The present invention relates to a method for controlling the thickness of an insulating film on a multilayer thin film circuit board.

近年の半導体技術の進展に伴い、高集積化、高速化され
た半導体装置の特性を十分に引き出すため、高性能の半
導体装置実装用回路基板が必要とされ、無機材料からな
る基板の上に低誘電率の感光性を機系の絶縁膜と配線膜
(感体パターン)をフォトリソグラフィ技術〔感光性有
機系絶縁材塗布→プリベーク(乾燥)→露光→現像→ポ
ストベーク(乾燥)・・・〕を利用して交互に積層形成
した多N薄膜回路基板が実用化されている。
With the recent progress in semiconductor technology, high-performance circuit boards for mounting semiconductor devices are required in order to fully exploit the characteristics of highly integrated and high-speed semiconductor devices. Photolithography technology for photosensitive dielectric constant and wiring film (sensor pattern) [coating of photosensitive organic insulating material → pre-bake (drying) → exposure → development → post-bake (drying)...] A multi-N thin film circuit board formed by alternately laminating layers has been put into practical use.

その絶縁膜には配線股間を電気接続するビアホールを形
成するが、絶縁膜の厚さは回路基板の電気的特性(特性
インピーダンス)に影響を与えることから、一定厚さに
形成することが要望されている。
Via holes are formed in the insulating film to electrically connect between the wiring legs, but since the thickness of the insulating film affects the electrical characteristics (characteristic impedance) of the circuit board, it is desired that the film be formed to a constant thickness. ing.

〔従来の技術〕[Conventional technology]

第3図は従来の方法により製造された半導体装置実装用
回路基板の要部側断面図を示す。
FIG. 3 shows a sectional side view of a main part of a circuit board for mounting a semiconductor device manufactured by a conventional method.

図示するように、アルミナやガラスセラミックなどの無
機材料からなる基板を数種類の電源用配線膜11a−3
を挟んで多層に積層し、各層の電源用配線膜11a−3
はビアホール1la−2を介して表面のランド1la−
1に接続した電源基板11aの上に、さらに感光性有機
系の絶縁膜11bと配線膜(導体パターン) l1cと
をフォトリソグラフィ法により交互に積層して多層化し
所望の半導体装置実装用多層回路基板11を製造してい
る。
As shown in the figure, a substrate made of an inorganic material such as alumina or glass ceramic is connected to several types of power supply wiring films 11a-3.
The power supply wiring film 11a-3 of each layer is stacked in multiple layers with the
is the land 1la- on the surface via the via hole 1la-2.
On the power supply board 11a connected to 1, a photosensitive organic insulating film 11b and a wiring film (conductor pattern) 11c are alternately laminated by photolithography to form a multilayer circuit board for mounting a desired semiconductor device. 11 are manufactured.

絶縁膜11bには、配線膜11c間を電気接続するビア
ホール11bcを怒光性有機系絶縁材塗布−プリヘーク
(乾燥)→露光→現像→ボストベーク(乾燥)により所
定位置に形成し、絶縁膜11bの膜厚制御はスピンコー
ド法を適用した回転塗布器(図示路)による塗布工程に
おいて回転塗布器の回転数を予め、規制し行っている。
Via holes 11bc for electrically connecting the wiring films 11c are formed in predetermined positions in the insulating film 11b by applying a photosensitive organic insulating material - pre-hake (drying) -> exposure -> development -> post-bake (drying). The film thickness is controlled by regulating the number of rotations of the spin coater in advance in the coating process using a spin coater (the path shown in the figure) using the spin code method.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、このような上記絶縁膜の膜厚管理方法に
よれば、現像工程の最中に絶縁膜の厚さが減るという問
題があり、絶縁膜と配線膜を多層化した場合、絶縁膜の
膜厚のバラツキが回路基板の電気的特性(特性インピー
ダンス)に大きな影響を与えるといった問題が^った。
However, according to this method of controlling the thickness of the insulating film, there is a problem that the thickness of the insulating film decreases during the development process, and when the insulating film and wiring film are multilayered, the thickness of the insulating film decreases. There was a problem in that variations in thickness had a large effect on the electrical characteristics (characteristic impedance) of the circuit board.

上記問題点に鑑み、本発明は絶縁膜の膜厚を十分に管理
することのできる多層薄膜回路基板の絶縁膜厚の管理方
法を提供することを目的とする。
In view of the above-mentioned problems, an object of the present invention is to provide a method for controlling the thickness of an insulating film of a multilayer thin film circuit board by which the thickness of the insulating film can be sufficiently controlled.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、本発明の多層薄膜回路基板
の絶縁膜厚の管理方法においては、感光性有機系の絶縁
膜に配線膜間を接続するビアホールを形成する際に同時
に膜厚チェック用ホールを形成し、該膜厚チェック用ホ
ールの深さを測定して膜厚が正常なときは次工程の配線
膜形成に進み、不良のときは剥離し再度、絶縁膜形成工
程に戻り積層を行うように構成する。
In order to achieve the above object, in the method of controlling the insulation film thickness of a multilayer thin film circuit board of the present invention, when forming via holes connecting wiring films in a photosensitive organic insulation film, a film thickness check is simultaneously performed. A hole is formed, and the depth of the film thickness check hole is measured. If the film thickness is normal, proceed to the next process of wiring film formation. If it is defective, peel it off and return to the insulating film formation process again to continue lamination. Configure it to do so.

〔作用〕[Effect]

絶縁膜に配線膜間を接続するビアホールを形成する際に
同時に膜厚チェック用ホールを形成することにより、膜
厚チェック用ホールの深さを測定し形成された絶縁膜の
膜厚を知ることができる。
By forming a film thickness check hole at the same time as forming a via hole to connect wiring films in an insulating film, it is possible to measure the depth of the film thickness check hole and know the thickness of the formed insulating film. can.

〔実施例〕〔Example〕

以下図面に示した半導体装置実装用多層回路基板を製造
する実施例に基づいて本発明の要旨を詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention will be explained in detail below based on an embodiment of manufacturing a multilayer circuit board for mounting a semiconductor device shown in the drawings.

第1図は本発明により製造された一実施例の半導体装置
実装用回路基板の要部側断面図を示す。
FIG. 1 shows a side cross-sectional view of essential parts of a circuit board for mounting a semiconductor device according to an embodiment of the present invention.

図示するように、半導体装置実装用多層回路基板lは従
来同様に内層に数種の電源用配線膜1a−3を有しビア
ホール1a−2を介して表面のランド1a−1に接続し
たセラミックやガラスセラミックなどの無機材料からな
る基板1a、即ち電源基板の上に感光性有機系の絶縁膜
1bと配線膜(導体パターン)1cをフォトリングラフ
ィ法により交互に積層し構成する。
As shown in the figure, the multilayer circuit board 1 for mounting semiconductor devices has several kinds of power supply wiring films 1a-3 in the inner layer, as in the conventional case, and ceramic and A photosensitive organic insulating film 1b and a wiring film (conductor pattern) 1c are alternately laminated on a substrate 1a made of an inorganic material such as glass ceramic, ie, a power supply board, by photolithography.

絶縁膜1bと配線膜1cを交互に積層する際、従来同様
に絶縁膜1bには配線膜1c間を電気接続するビアホー
ル1bcを形成するが、本発明においてはビアホール1
bcの形成と同時に膜厚チェック用ホール1dを形成す
る。即ち、第2図(a)、 (bl、 (C1の絶縁膜
形成を工程順に示す側断面図のように、(a)図の絶縁
材塗布工程において、電源基板1aの上に既にランド1
a−1が形成されているのを前提に(図は第1図に示し
た電源用配線膜1a−3及びビアホール1a−2を図示
省略している)、そのランド18−1の上に厚さ40〜
50μmの絶縁膜1bを形成するポリイミド樹脂などの
感光性有機系の絶縁材1b’ をスピンコード法を適用
した回転塗布器(図示路)を用いて塗布し、プリヘーク
(80’C,1時間乾燥)する。
When the insulating films 1b and wiring films 1c are alternately laminated, via holes 1bc are formed in the insulating film 1b to electrically connect between the wiring films 1c as in the conventional method.
At the same time as forming bc, a film thickness check hole 1d is formed. That is, as shown in FIG. 2(a), (bl, (a side cross-sectional view showing the step-by-step process for forming the insulating film C1), in the insulating material coating process shown in FIG.
On the premise that the land 18-1 is formed (the figure omits the illustration of the power wiring film 1a-3 and the via hole 1a-2 shown in FIG. 1), a thick layer is formed on the land 18-1. Sa 40~
A photosensitive organic insulating material 1b' such as a polyimide resin that forms a 50 μm insulating film 1b is applied using a spin coater (as shown in the figure) using a spin code method, and pre-haked (dry at 80'C for 1 hour). )do.

つぎに、(b)図の露光・現像処理工程において、ガラ
スマスク(図示路)を用いて塗布した絶縁材1b’ に
露光・現像処理を行いビアホールIbc及び膜厚チェッ
ク用ホール1dを形成する。なお、膜厚チェック用ホー
ル1dは1■l〜21角の大きさで上、下記線膜形成外
の領域に設け、絶縁材1b’ 、即ち絶縁膜1bの膜I
7を全面的にチェックできるように複数箇所に均等配置
(図はその中の1つを示す)するのが望ましい。
Next, in the exposure and development process shown in FIG. 2B, the applied insulating material 1b' is exposed and developed using a glass mask (as shown) to form a via hole Ibc and a film thickness check hole 1d. The film thickness check hole 1d has a size of 1 cm to 21 squares, and is provided in the area outside the line film formation shown below, and is located in the area outside the line film formation, which is located above the insulating material 1b', that is, the film I of the insulating film 1b.
It is desirable to arrange them evenly at multiple locations (the figure shows one of them) so that 7 can be checked completely.

そして、この時点でTe3図の膜厚測定工程において、
膜厚チェック用ホール1dの深さ、即ち絶縁膜1bの厚
さを膜厚測定器の触針2を当てて測定する。
At this point, in the film thickness measurement process of diagram Te3,
The depth of the film thickness check hole 1d, that is, the thickness of the insulating film 1b, is measured by applying the stylus 2 of the film thickness measuring device.

(なお、ポストベーク前であるので膜厚減少分を見込む
)膜厚が不良の場合は、この時点で不良の絶縁膜を剥離
処理し再度、fa1図の絶縁材塗布工程からやり直す。
(Please note that this is before post-baking, so a reduction in film thickness is expected.) If the film thickness is defective, the defective insulating film is removed at this point and the process is repeated from the insulating material coating step shown in Figure FA1.

正常な膜厚であれば、つぎのボストベーク(400℃、
2〜3時間乾燥)を行ってビアホール1bc及び膜厚チ
ェック用ホール1dを開けた第1層の絶縁膜1bを形成
する。
If the film thickness is normal, perform the next boss bake (400℃,
A first layer insulating film 1b having via holes 1bc and film thickness check holes 1d is formed by drying for 2 to 3 hours.

つぎに、図示はしないが第2層の配線膜形成工程に移り
配線膜を形成後、第3層の絶縁膜を同様の方法で形成し
、順次、絶縁膜と配線膜を交互に積層し所望の半導体装
置実装用回路基板を得る。
Next, although not shown, the process moves to a second layer wiring film formation step, and after forming the wiring film, a third layer insulating film is formed in the same manner, and the insulating film and wiring film are sequentially laminated alternately to form the desired layer. A circuit board for mounting a semiconductor device is obtained.

このように、絶縁膜にビアホール形成と同時に膜厚チェ
ック用ホールを形成することにより、膜厚を直接、測定
するこ・とができ、従来のように回転塗布器の回転数の
規制だけで絶縁膜を形成してしまうのに比べて絶縁膜を
形成の都度、その膜厚を測定するため正確な膜厚に管理
形成することができる。
In this way, by forming a film thickness check hole in the insulation film at the same time as forming a via hole, the film thickness can be directly measured. Compared to forming a film, the thickness of the insulating film is measured each time the insulating film is formed, so the film thickness can be controlled and formed accurately.

〔発明の効果〕〔Effect of the invention〕

以上、詳述したように本発明によれば、絶縁膜の膜厚を
正確に管理形成することができ、例えば半導体装置実装
用回路基板の製造に適用して電気的特性、とくに特性イ
ンピーダンスの安定した半導体装置モジュールなどを提
供することができるといった産業上極めて有用な効果を
発揮する。
As described in detail above, according to the present invention, the thickness of the insulating film can be accurately controlled and formed, and it can be applied to, for example, the manufacture of circuit boards for mounting semiconductor devices to stabilize electrical properties, especially characteristic impedance. This has an extremely useful effect industrially, such as being able to provide semiconductor device modules and the like that are made of high-quality materials.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によりi!造された一実施例の半導体装
置実装用回路基板の要部側断面図、第2図(al、 f
bl、 telは第1図の絶縁膜形成工程を順に示す側
断面図、 第3図は従来技術による方法で製造された半導体装置実
装用回路基板の要部側断面図である。 図において、 1は半導体装置実装用多層回路基板、 1aは基板(電源基板)、 1bは絶縁膜、 tb’は絶縁材、 1bcはビアホール、 1cは配線膜(導体バ)−ン)、 1dは膜厚チェック用ホールを示す。 ゛・き (al絶縁材塗布工程 To)露光 現像処理工程
FIG. 1 shows i! according to the present invention! FIG. 2 is a side cross-sectional view of the main part of the fabricated circuit board for mounting a semiconductor device according to one embodiment (al, f).
bl and tel are side sectional views sequentially showing the insulating film forming process in FIG. 1, and FIG. 3 is a side sectional view of a main part of a circuit board for mounting a semiconductor device manufactured by a method according to the prior art. In the figure, 1 is a multilayer circuit board for mounting semiconductor devices, 1a is a substrate (power supply board), 1b is an insulating film, tb' is an insulating material, 1bc is a via hole, 1c is a wiring film (conductor bar), 1d is a The hole for checking film thickness is shown.゛・ki (Al insulation material coating process To) exposure and development process

Claims (1)

【特許請求の範囲】  基板(1a)上に感光性有機系の絶縁膜(1b)と配
線膜(1c)を交互に積層してなる多層薄膜回路基板を
製造する工程において、 前記絶縁膜(1b)に前記配線膜(1c)間を接続する
ビアホール(1bc)を形成する際に同時に膜厚チェッ
ク用ホール(1d)を形成し、該膜厚チェック用ホール
(1d)の深さを測定して膜厚が正常なときは次工程の
配線膜(1c)形成に進み、不良のときは剥離し再度、
前記絶縁膜形成工程に戻り積層を行うことを特徴とする
多層薄膜回路基板の膜厚管理方法。
[Claims] In the step of manufacturing a multilayer thin film circuit board in which a photosensitive organic insulating film (1b) and a wiring film (1c) are alternately laminated on a substrate (1a), the insulating film (1b) ) When forming the via hole (1bc) connecting between the wiring films (1c), a film thickness check hole (1d) is formed at the same time, and the depth of the film thickness check hole (1d) is measured. If the film thickness is normal, proceed to the next step of forming the wiring film (1c), if it is defective, peel it off and repeat.
A method for controlling film thickness of a multilayer thin film circuit board, characterized by returning to the insulating film forming step and performing lamination.
JP29077589A 1989-11-07 1989-11-07 Managing method for film thickness of multilayer thin film circuit board Pending JPH03150894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29077589A JPH03150894A (en) 1989-11-07 1989-11-07 Managing method for film thickness of multilayer thin film circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29077589A JPH03150894A (en) 1989-11-07 1989-11-07 Managing method for film thickness of multilayer thin film circuit board

Publications (1)

Publication Number Publication Date
JPH03150894A true JPH03150894A (en) 1991-06-27

Family

ID=17760362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29077589A Pending JPH03150894A (en) 1989-11-07 1989-11-07 Managing method for film thickness of multilayer thin film circuit board

Country Status (1)

Country Link
JP (1) JPH03150894A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07307573A (en) * 1994-05-13 1995-11-21 Nec Corp Via structure of multilayered wiring ceramic board and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07307573A (en) * 1994-05-13 1995-11-21 Nec Corp Via structure of multilayered wiring ceramic board and manufacture thereof

Similar Documents

Publication Publication Date Title
US8713769B2 (en) Embedded capacitive stack
EP0460822B1 (en) Integrated circuit packaging using flexible substrate
CN102090155B (en) Method for integrating at least one electronic component into a printed circuit board, and printed circuit board
JPS63258055A (en) Manufacture of electronic circuit device
WO2000007233A1 (en) An improved method of planarizing thin film layers deposited over a common circuit base
US6171946B1 (en) Pattern formation method for multi-layered electronic components
US20040074865A1 (en) Hybrid interconnect substrate and method of manufacture thereof
JPH03150894A (en) Managing method for film thickness of multilayer thin film circuit board
KR20130031592A (en) Method for manuracturing printed circuit board with via and fine pitch circuit and printed circuit board by the same method
RU2639720C2 (en) Printed circuit board with internal mounting of elements and method of its manufacture
JPH01175297A (en) Multilayer printed circuit board device
US6699748B2 (en) Method of fabricating capacitor having a photosensitive resin layer as a dielectric
KR101538046B1 (en) Method for manufacturing ceramic device having fine line pattern, and ceramic device having fine line pattern
JPH08340179A (en) Organic resin multilayer wiring board and manufacture thereof
JP2841888B2 (en) Multilayer wiring board and method of manufacturing the same
JPS58215094A (en) Method of producing multilayer printed circuit board
JP2001177253A (en) Manufacturing method for multilayer printed board
TW502302B (en) Method for producing substrate with conductive conical body
KR100567096B1 (en) Printed circuit board with embedded capacitor and manufacturing method for the same
JP2644847B2 (en) Multilayer wiring board and method of manufacturing the same
JPS61248534A (en) Formation of insulating film
TW423034B (en) Method for forming low-impedance high-density deposited-on-laminate structures having reduced stress
JP2003304060A (en) Method of manufacturing double-sided circuit board
JPH0236591A (en) Manufacture of multilayer substrate
US20080178464A1 (en) Method for fabricating circuit board