JPH0236591A - Manufacture of multilayer substrate - Google Patents
Manufacture of multilayer substrateInfo
- Publication number
- JPH0236591A JPH0236591A JP18553488A JP18553488A JPH0236591A JP H0236591 A JPH0236591 A JP H0236591A JP 18553488 A JP18553488 A JP 18553488A JP 18553488 A JP18553488 A JP 18553488A JP H0236591 A JPH0236591 A JP H0236591A
- Authority
- JP
- Japan
- Prior art keywords
- precursor
- thermoplastic resin
- polyimide
- layer
- polyimide precursor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000002243 precursor Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 22
- 229920005992 thermoplastic resin Polymers 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 239000007788 liquid Substances 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 abstract description 56
- 239000004642 Polyimide Substances 0.000 abstract description 55
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000013461 design Methods 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 12
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 230000009477 glass transition Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920005575 poly(amic acid) Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
概要
電子部品を実装する多層基板の製造方法に関し、基板の
電気的特性が良いとともに、部品の実装に制限の少ない
多層基板を提供することを目的とし、
絶縁基板上に導体パターンを形成し、該導体パターンの
形成された絶縁基板上に液体の熱可塑性樹脂前駆体を塗
布し、フォトリソグラフィーにより該塗布された熱可塑
性樹脂前駆体の所定箇所にビアホールを形成した後に、
加熱して前記熱可塑性樹脂を転移させ、該転移させた熱
可塑性樹脂上に導体パターンを形成し、さらに、熱可塑
性樹脂前駆体の塗布、ビアホールの形成、加熱、及び導
体パターンの形成を複数回操り返し、最上層に熱可塑性
樹脂前駆体を塗布した後に、加熱してなる多層基板の製
造方法において、前記熱可塑性樹脂前駆体の塗布をそれ
ぞれ２回に分けて行い、１回目の塗布でビアホール内に
熱可塑性樹脂前駆体を充填せしめ、２回目の塗布で所定
の層厚に形成せしめることにより、熱可塑性樹脂層が平
坦且つ均質になるように構成する。[Detailed Description of the Invention] Summary Regarding a method for manufacturing a multilayer board on which electronic components are mounted, the purpose is to provide a multilayer board that has good electrical characteristics and has fewer restrictions on mounting components. After forming a conductor pattern, applying a liquid thermoplastic resin precursor on the insulating substrate on which the conductor pattern is formed, and forming via holes at predetermined locations in the applied thermoplastic resin precursor by photolithography,
heating to transfer the thermoplastic resin, forming a conductive pattern on the transferred thermoplastic resin, and further applying a thermoplastic resin precursor, forming a via hole, heating, and forming a conductive pattern multiple times. In a method for manufacturing a multilayer board in which a thermoplastic resin precursor is applied to the top layer and then heated, the thermoplastic resin precursor is applied twice, and the via holes are formed in the first application. By filling the inside with a thermoplastic resin precursor and forming it to a predetermined layer thickness in the second application, the thermoplastic resin layer is configured to be flat and homogeneous.
産業上の利用分野
本発明は絶縁基板上に絶縁層及び配線層を積層してなる
多層基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer board in which an insulating layer and a wiring layer are laminated on an insulating substrate.
電子計算機等においては、高速性等の追求から、配線パ
スを物理的に短くするために、あるいは、民生機器にお
いては、できるだけ小型に仕上げるために、部品そのも
のの高集積化や、これを実装する基板の高密度実装化、
高多層化等が要望されている。In electronic computers, etc., in order to physically shorten the wiring path in pursuit of high speed, etc., and in consumer equipment, in order to make it as small as possible, the components themselves are highly integrated and are implemented. High-density mounting of boards,
There is a demand for high multi-layer technology.
この要望に基づき、近年、絶縁層にポリイミドを、配線
層にＣｕ（銅）を用いたＣｕポリイミド多層基板が開発
され、実用化されつつある。Ｃｕポリイミド基板は誘電
率が３〜３．５と低いポリイミド樹脂と、微細化しても
低い抵抗値を維持できるＣｕを用い、薄膜プロセスによ
る高密度化によりチップ間の配線長を大幅に短くするこ
とができることから、注目されている。Based on this demand, in recent years, a Cu polyimide multilayer substrate using polyimide for the insulating layer and Cu (copper) for the wiring layer has been developed and is being put into practical use. The Cu polyimide substrate uses a polyimide resin with a low dielectric constant of 3 to 3.5 and Cu, which maintains a low resistance value even when miniaturized, and allows the wiring length between chips to be significantly shortened by increasing density through the thin film process. It is attracting attention because of its ability to
従来の技術
以下−船釣なＣｕポリイミド多層基板の製造プロセスを
第３図乃至第５図を参照して説明することにする。A conventional manufacturing process for a Cu polyimide multilayer substrate will be described with reference to FIGS. 3 to 5.
まず、第３図を参照すると、セラミック等からなる絶縁
基板１０上に電源や接地等の粗い配線層（Ｃｕパターン
）１２を形成しておき、その上に液体のポリイミド（ポ
リイミドの前駆体、加熱によってポリイミドとなる物質
）をスピンコード法（基板を所定の速度で回転せしめ、
上からポリイミド前駆体を点滴する）により、あるいは
スクリーン印刷により塗布する。これを約８５℃で予備
加熱し、その表面を平坦化するとともに、ある程度硬化
させ、厚さ約２５〜５０μｍの絶縁層１４を形成する。First, referring to FIG. 3, a rough wiring layer (Cu pattern) 12 for power supply, grounding, etc. is formed on an insulating substrate 10 made of ceramic or the like, and a liquid polyimide (polyimide precursor, heated material that becomes polyimide) using the spin code method (the substrate is rotated at a predetermined speed,
It is applied by dripping the polyimide precursor from above) or by screen printing. This is preheated at about 85° C. to flatten the surface and harden it to some extent to form an insulating layer 14 with a thickness of about 25 to 50 μm.
この絶縁層１４にフォトレジストを塗布し、マスク露光
、現像、エツチングの工程を経てビアホール１６を形成
する。感光性ポリイミド（ポリイミド前駆体のポリアミ
ック酸の側鎖に、光架橋反応を起こす感光基を付けたも
の）を用いた場合はフォトレジスト塗布は不要である。A photoresist is applied to this insulating layer 14, and a via hole 16 is formed through mask exposure, development, and etching steps. When photosensitive polyimide (a polyimide precursor in which a photosensitive group that causes a photocrosslinking reaction is attached to the side chain of polyamic acid) is used, photoresist coating is not necessary.
これを約３５０℃で加熱処理して、ポリイミド前駆体を
ガラス転移させる。次いで、蒸着、スパッタリング等の
方法で薄膜のＣｕ配線屡１８を作る〈第４図参照）。配
線幅は約１０〜１００μｍ１層厚は約５〜１０μｍであ
る。This is heat-treated at about 350° C. to cause a glass transition of the polyimide precursor. Next, a thin film Cu wiring layer 18 is formed by a method such as vapor deposition or sputtering (see FIG. 4). The wiring width is approximately 10 to 100 μm, and the thickness of each layer is approximately 5 to 10 μm.
この配線層１８上に、前記同様に、ポリイミド前駆体２
０を塗布しく第５図参照）、予備加熱（約８５℃）、ビ
アホール形成、加熱（約３５０℃）処理した後に、配線
層２２を形成する。この作業を複数回繰り返した後に、
ポリイミド前駆体２４を塗布し、約３５０℃で加熱処理
する。最後に最上層表面にレアチップ等実装用のパター
ンを形成して、多層基板を形成している。On this wiring layer 18, a polyimide precursor 2 is applied as described above.
After preheating (approximately 85° C.), forming via holes, and heating (approximately 350° C.), the wiring layer 22 is formed. After repeating this process multiple times,
A polyimide precursor 24 is applied and heat treated at about 350°C. Finally, a pattern for mounting rare chips and the like is formed on the surface of the top layer to form a multilayer board.
発明が解決しようとする課題
絶縁層の層厚は、配線層（パターン）の幅と得たいイン
ピーダンス特性との関係で決まり、例えばスピンコード
法による塗布の場合、ポリイミド前駆体の粘度と、基板
の回転速度により調整して、所定の層厚にするようにし
ている。Problems to be Solved by the Invention The layer thickness of the insulating layer is determined by the relationship between the width of the wiring layer (pattern) and the desired impedance characteristics.For example, in the case of coating by the spin code method, the thickness of the insulating layer is determined by the viscosity of the polyimide precursor and the thickness of the substrate. The rotation speed is adjusted to obtain a predetermined layer thickness.
しかし、第６図に示すように、ビアホール２６部では、
ビアホール２６内にポリイミド前駆体２４が落ち込んで
しまい、一定の層厚にすることができない場合があり、
この上にさらに積層した場合には、内部にボイド（気泡
）が生じたり、最上層にくぼみが発生し、基板のインピ
ーダンス特性が設計どうりにならなかったり、最上層上
に部品実装用のパターンを形成することができないこと
があるという問題点がった。However, as shown in Fig. 6, in the via hole 26,
The polyimide precursor 24 may fall into the via hole 26, making it impossible to maintain a constant layer thickness.
If further layers are stacked on top of this, voids (bubbles) may occur inside the top layer, dents may occur in the top layer, the impedance characteristics of the board may not match the design, or a pattern for mounting components may be placed on the top layer. The problem is that it may not be possible to form a
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、基板の電気的特性が良いととも
に、部品の実装に制限の少ない多層基板の製造方法を提
供することである。The present invention has been made in view of these points, and its purpose is to provide a method for manufacturing a multilayer board that has good electrical characteristics and fewer restrictions on mounting components. .
課題を解決するための手段
絶縁基板上に導体パターンを形成し、該導体パターンの
形成された絶縁基板上にポリイミド前駆体を塗布し、フ
ォトリソグラフィーにより、該塗布されたポリイミド前
駆体の所定箇所にビアホールを形成した後に、加熱して
前記ポリイミドをガラス転移させ、該ガラス転移させた
ポリイミド上に導体パターンを形成する。Means for Solving the Problems A conductive pattern is formed on an insulating substrate, a polyimide precursor is applied onto the insulating substrate on which the conductive pattern is formed, and predetermined locations on the applied polyimide precursor are formed by photolithography. After the via holes are formed, the polyimide is heated to cause a glass transition, and a conductive pattern is formed on the polyimide that has undergone the glass transition.
この上に、例えばスピンコード法による場合、まず、粘
度の低いポリイミド前駆体を用いて塗布してビアホール
内にポリイミド前駆体を充填せしめ、次いで、形成すべ
き層厚に応じた粘度のポリイミド前駆体を塗布する。さ
らに、ビアホールの形成、加熱、導体パターンの形成、
ポリイミド前駆体の２回塗布を複数回繰り返し、最上層
にポリイミド前駆体を２回塗布した後に加熱する。For example, when using the spin code method, a polyimide precursor with a low viscosity is first applied to fill the via hole with the polyimide precursor, and then a polyimide precursor with a viscosity corresponding to the layer thickness to be formed is applied. Apply. Furthermore, via hole formation, heating, conductor pattern formation,
The two-time coating of the polyimide precursor is repeated multiple times, and the top layer is heated after being coated with the polyimide precursor twice.
この方法で多層基板を形成することにより、上述した問
題点を解決する。Forming a multilayer substrate using this method solves the above-mentioned problems.
作 用
本発明によれば、ポリイミド前駆体の塗布を２回に分け
て行い、１回目の塗布で、例えばスピンコード法による
場合、その粘度を通常より低く（軟らかく）シて、塗布
することにより、ビアホール内にポリイミドを充填し、
さらに２回目の塗布により必要な層厚に形成している。Function According to the present invention, the polyimide precursor is applied in two times, and in the first application, for example, when using the spin code method, the viscosity is lowered (softened) than usual and the polyimide precursor is applied in two steps. , fill the via hole with polyimide,
Furthermore, a second coating is performed to form the required layer thickness.
これにより、ビアホール上にくぼみが発生することがな
くなり、この上にさらにポリイミド層（絶縁層）等を積
層した場合でも、ポリイミド層（絶縁層）内部にボイド
（気泡）等が発生せず、ポリイミド層（絶縁層）が均質
になり、設計どうりのインピーダンス特性が得られると
ともに、最上層表面も平坦なので、部品の実装に支障を
きたすこともなくなる。This eliminates the occurrence of depressions on the via hole, and even when a polyimide layer (insulating layer) is further laminated on top of the via hole, voids (bubbles) etc. do not occur inside the polyimide layer (insulating layer), and the polyimide The layer (insulating layer) becomes homogeneous, providing impedance characteristics as designed, and the surface of the top layer is flat, so there is no problem in mounting components.
実施例
以下本発明の一実施例を第１図及び第２図を参照して詳
細に説明することにする。EXAMPLE Hereinafter, an example of the present invention will be described in detail with reference to FIGS. 1 and 2.
セラミック等からなる絶縁基板３０に電源や接地等の粗
い配線層（Ｃｕパターン） ３２を形成しておく。この
Ｃｕパターン３２の形成された絶縁基［３０を所定の速
度で回転せしめながら、絶縁基板３０上に液体のポリイ
ミド（ポリイミドの前駆体、加熱によってポリイミドと
なる物質）を点滴する（スピンコード法）等して、絶縁
体基板３０上に厚さ約２５〜５０μｍの絶縁層３４を形
成する。これを約８５℃で予備加熱し、ポリイミド前駆
体の表面を平坦化するとともに、ある程度硬化させる。A rough wiring layer (Cu pattern) 32 for power supply, grounding, etc. is formed on an insulating substrate 30 made of ceramic or the like. While rotating the insulating substrate [30 on which the Cu pattern 32 is formed] at a predetermined speed, liquid polyimide (a precursor of polyimide, a substance that becomes polyimide when heated) is dripped onto the insulating substrate 30 (spin code method). In the same manner, an insulating layer 34 having a thickness of about 25 to 50 μm is formed on the insulating substrate 30. This is preheated at about 85° C. to flatten the surface of the polyimide precursor and to harden it to some extent.
この絶縁基３４にフォトレジストを塗布し、マスク露光
、現像、エツチングの工程を経てビアホールを形成する
。感光性ポリイミド（ポリイミド前駆体のポリアミック
酸の側鎖に、光架橋反応を起こす感光基を付けたもの）
を用いた場合はフォトレジスト塗布は不要である。A photoresist is applied to this insulating base 34, and a via hole is formed through the steps of mask exposure, development, and etching. Photosensitive polyimide (a polyimide precursor with a photosensitive group attached to the side chain of polyamic acid that causes a photocrosslinking reaction)
When using , photoresist coating is not necessary.
これを約３５０℃で加熱処理して、ポリイミド前駆体を
ガラス転移させる。次いで、蒸着、スパッタリング等の
方法で薄膜のＣｕ配線１３６を形成する。配線幅は１０
〜１００μｍ、層厚は５〜１０μｍである。This is heat-treated at about 350° C. to cause a glass transition of the polyimide precursor. Next, a thin film Cu wiring 136 is formed by a method such as vapor deposition or sputtering. Wiring width is 10
~100 μm, layer thickness 5-10 μm.
この配線層３６上にポリイミド前駆体３８をスピンコー
ド法により塗布し、８５℃で予備加熱後、ビアホールを
形成し、配線層４０を形成する。この上に、粘度の低い
ポリイミド前駆体をスピンコード法により塗布し、ビア
ホール４２内にポリイミド前駆体を充填させ（第１図）
、次いで、通常粘度のポリイミド前駆体をスピンコーテ
ィングし、厚さ約２５〜５０μｍの絶縁層４４を形成す
る（第２図）。さらにこれを約３５０℃で加熱した後、
その表面にレアチップ等実装用のパターンを形成して、
多層基板を形成する。A polyimide precursor 38 is coated on this wiring layer 36 by a spin code method, and after preheating at 85° C., via holes are formed, and a wiring layer 40 is formed. On top of this, a polyimide precursor with low viscosity is applied by a spin code method, and the via hole 42 is filled with the polyimide precursor (Fig. 1).
A normal viscosity polyimide precursor is then spin-coated to form an insulating layer 44 having a thickness of approximately 25-50 μm (FIG. 2). After further heating this at about 350℃,
A pattern for mounting rare chips etc. is formed on the surface,
Form a multilayer substrate.
上述した本実施例の説明においては、ポリイミド前駆体
の塗布を、最上層のもののみ２回に分けて行うようにし
であるが、配線層の形状等に応じて、中間層のポリイミ
ド前駆体塗布においても、ボイド（気泡）等発生防止の
ため、２回に分けて塗布するようにする。In the above description of this embodiment, the polyimide precursor is applied in two steps only for the top layer, but depending on the shape of the wiring layer, etc., the polyimide precursor may be applied in the middle layer. Also, in order to prevent the occurrence of voids (bubbles) etc., apply the product in two parts.
本実施例によれば、ビアホール形成後、ポリイミド前駆
体の塗布を２回に分けて行い、１回目は粘度の低いポリ
イミド前駆体をスピンコー子イングして、ビアホール内
にポリイミド前駆体を十分に充填せしめ、２回目は通常
粘度のポリイミド前駆体をスピンコーティングして、所
定層厚の絶縁層を形成するようにしであるから、ポリイ
ミド前駆体がビアホール内に十分流れ込まないことによ
り、絶縁層内に気泡を生じたり、最上層の絶縁層上にく
ぼみが生じたりすることがなく、絶縁層を均質にでき、
設計当初の基板特性を実現することができる。According to this example, after the via hole is formed, the polyimide precursor is applied in two steps, and in the first step, a low viscosity polyimide precursor is spin-coated to fully fill the via hole with the polyimide precursor. However, in the second coating, a polyimide precursor of normal viscosity is spin-coated to form an insulating layer with a predetermined thickness, so the polyimide precursor does not flow sufficiently into the via hole, causing air bubbles in the insulating layer. The insulating layer can be made homogeneous without causing any dents or depressions on the top insulating layer.
It is possible to realize the board characteristics originally designed.
また、この多層基板の表面は平坦なので、部品を実装す
るパターンの形成に制限がない。Furthermore, since the surface of this multilayer board is flat, there are no restrictions on the formation of patterns for mounting components.
尚、ポリイミド前駆体の塗布は、スピンコード法でなく
、スクリーン印刷等により行ってもよい。Note that the polyimide precursor may be applied by screen printing or the like instead of the spin code method.
発明の効果
本発明方法を適用して多層基板を形成すれば、絶縁層に
くぼみやボイドがなく、均質な絶縁層を形成でき、これ
により、基板のインピーダンス特性が劣化することがな
く、部品の実装にも制限の少ない多層基板を提供するこ
とができるという効果を奏する。Effects of the Invention By applying the method of the present invention to form a multilayer board, it is possible to form a homogeneous insulating layer with no depressions or voids in the insulating layer, thereby preventing deterioration of the impedance characteristics of the board and improving the quality of components. This has the effect of being able to provide a multilayer board with fewer restrictions on mounting.
第１図及び第２図は本発明を適用した方法による多層基
板の製造プロセスを説明するための図、第３図乃至第５
図は従来の方法による多層基板の製造プロセスを説明す
るための図、
第６図は従来技術の問題点を説明するための図である。
３０・・・絶縁基板、
３２．３６．４０−・・配線層（Ｃｕパターン）、３４
．３８．４４・・・絶縁層（ポリイミド層）、４２・・
・ビアホール。1 and 2 are diagrams for explaining the manufacturing process of a multilayer board by the method to which the present invention is applied, and FIGS. 3 to 5
The figure is a diagram for explaining the manufacturing process of a multilayer board by a conventional method, and FIG. 6 is a diagram for explaining the problems of the conventional technique. 30... Insulating substrate, 32.36.40-... Wiring layer (Cu pattern), 34
．． 38.44... Insulating layer (polyimide layer), 42...
・Beer hall.
Claims (1)
、該導体パターンの形成された絶縁基板上に液体の熱可
塑性樹脂前駆体を塗布し、フォトリソグラフィーにより
該塗布された熱可塑性樹脂前駆体の所定箇所にビアホー
ル（４２）を形成した後に、加熱して前記熱可塑性樹脂
を転移させ、該転移させた熱可塑性樹脂（３４）上に導
体パターン（３６）を形成し、さらに、熱可塑性樹脂前
駆体の塗布、ビアホールの形成、加熱、及び導体パター
ンの形成を複数回繰り返し、最上層に熱可塑性樹脂前駆
体を塗布した後に、加熱してなる多層基板の製造方法に
おいて、 前記熱可塑性樹脂前駆体の塗布をそれぞれ２回に分けて
行い、１回目の塗布でビアホール（４２）内に熱可塑性
樹脂前駆体を充填せしめ、２回目の塗布で所定の層厚に
形成せしめることにより、熱可塑性樹脂層が平坦且つ均
質になるようにしたことを特徴とする多層基板の製造方
法。[Claims] A conductive pattern (32) is formed on an insulating substrate (30), a liquid thermoplastic resin precursor is applied onto the insulating substrate on which the conductive pattern is formed, and the applied liquid is formed by photolithography. After forming via holes (42) at predetermined locations in the thermoplastic resin precursor, the thermoplastic resin is transferred by heating, and a conductive pattern (36) is formed on the transferred thermoplastic resin (34). Further, in a method for manufacturing a multilayer board, the steps of applying a thermoplastic resin precursor, forming via holes, heating, and forming a conductor pattern are repeated multiple times, and after applying the thermoplastic resin precursor on the top layer, heating is performed. , The thermoplastic resin precursor is applied twice, and the via hole (42) is filled with the thermoplastic resin precursor in the first application, and the thermoplastic resin precursor is formed to a predetermined layer thickness in the second application. A method for manufacturing a multilayer substrate, characterized in that the thermoplastic resin layer is made flat and homogeneous.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18553488A JPH0236591A (en) | 1988-07-27 | 1988-07-27 | Manufacture of multilayer substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18553488A JPH0236591A (en) | 1988-07-27 | 1988-07-27 | Manufacture of multilayer substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0236591A true JPH0236591A (en) | 1990-02-06 |
Family
ID=16172486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18553488A Pending JPH0236591A (en) | 1988-07-27 | 1988-07-27 | Manufacture of multilayer substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0236591A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999034655A1 (en) * | 1997-12-29 | 1999-07-08 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| JP2017168737A (en) * | 2016-03-17 | 2017-09-21 | 富士通株式会社 | Multilayer wiring board and manufacturing method of multilayer wiring board |
-
1988
- 1988-07-27 JP JP18553488A patent/JPH0236591A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999034655A1 (en) * | 1997-12-29 | 1999-07-08 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| US6365843B1 (en) | 1997-12-29 | 2002-04-02 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| JP2017168737A (en) * | 2016-03-17 | 2017-09-21 | 富士通株式会社 | Multilayer wiring board and manufacturing method of multilayer wiring board |
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