JP2017168737A - Multilayer wiring board and manufacturing method of multilayer wiring board - Google Patents

Multilayer wiring board and manufacturing method of multilayer wiring board Download PDF

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JP2017168737A
JP2017168737A JP2016054242A JP2016054242A JP2017168737A JP 2017168737 A JP2017168737 A JP 2017168737A JP 2016054242 A JP2016054242 A JP 2016054242A JP 2016054242 A JP2016054242 A JP 2016054242A JP 2017168737 A JP2017168737 A JP 2017168737A
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wiring
wiring layer
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JP6623870B2 (en
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正則 秋江
Masanori Akie
正則 秋江
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Fujitsu Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board in which adhesion of a wiring layer of a via part is high.SOLUTION: A multilayer wiring board 1 is a multilayer wiring board in which a plurality of wiring layers 12, 22, and 32 and insulation layers 11, 21, and 31 are alternately laminated. The multilayer wiring board includes: at least one of via parts 3 connecting two or more wiring layers of a plurality of wiring layers, and a projection part 14 that is provided to at least one via part, and is made of an insulation material projected toward the wiring layer of the other end side of two or more wiring layers from the wiring layer 12 of one end side of two ore more wiring layers to be connected. A tip part of the projection part reaches to the wiring layer of the other end side of two or more wiring layers to be connected. In a conductive metal film 15 covering an external surface of the projection part, two or more wiring layers to be connected are conducted.SELECTED DRAWING: Figure 2

Description

本出願は多層配線基板及び多層配線基板の製造方法に関する。   The present application relates to a multilayer wiring board and a method for manufacturing the multilayer wiring board.

従来の多層配線基板では、二つ以上の配線層を接続する際、配線層の間にある絶縁層に、二つ以上の配線層のうちの一端側に位置する配線層(例えば下方の配線層)から他端側に位置する配線層(例えば上方の配線層)に向けて広がる穴を形成し、その穴に金属を入れることでビア部を形成して配線層を接続している。   In a conventional multilayer wiring board, when two or more wiring layers are connected, a wiring layer located on one end side of the two or more wiring layers (for example, a lower wiring layer) is connected to an insulating layer between the wiring layers. ) To the wiring layer (for example, the upper wiring layer) located on the other end side, and a via portion is formed by inserting a metal into the hole to connect the wiring layers.

図11に、従来の方法により製造された、複数の配線層(112、122、132)と絶縁層(111、121、131)とからなる多層配線基板101の断面図を示す。従来の多層配線基板101では、同じ位置に連続して複数の配線層を接続する際、ビア部103(スタックビア)の穴116が形成される。穴116は、図11に示すように、一端側の配線層112から、他端側の配線層132に向けて広がるよう形成される。すなわち、穴116は、他端側の配線層132から一端側の配線層112に向かう方向(図11の矢印A方向)に従って狭くなっている。そして、この穴116に金属115を入れることで各配線層は導通される。しかしながら、配線層112とビア部103との接合部分117の面積が狭くなっているため、例えば接合部分117に応力が集中すると、ビア部103が配線層112から剥離する可能性があった。   FIG. 11 shows a cross-sectional view of a multilayer wiring board 101 made of a plurality of wiring layers (112, 122, 132) and insulating layers (111, 121, 131) manufactured by a conventional method. In the conventional multilayer wiring board 101, when a plurality of wiring layers are continuously connected to the same position, a hole 116 of a via portion 103 (stack via) is formed. As shown in FIG. 11, the hole 116 is formed so as to expand from the wiring layer 112 on one end side toward the wiring layer 132 on the other end side. That is, the hole 116 is narrowed according to the direction (direction of arrow A in FIG. 11) from the wiring layer 132 on the other end side to the wiring layer 112 on the one end side. Then, by inserting the metal 115 into the hole 116, each wiring layer is conducted. However, since the area of the joint portion 117 between the wiring layer 112 and the via portion 103 is narrow, for example, when stress is concentrated on the joint portion 117, the via portion 103 may be separated from the wiring layer 112.

特開平2−288395号公報JP-A-2-288395 特開2001−345556号公報JP 2001-345556 A 特開2002−26522号公報JP 2002-26522 A

上述の問題に鑑み、配線層とビア部との密着性が高い多層配線基板を提供することを目的とする。   In view of the above problems, an object of the present invention is to provide a multilayer wiring board having high adhesion between a wiring layer and a via portion.

1つの形態によれば、複数の配線層及び絶縁層が交互に積層される多層配線基板であって、複数の配線層のうち、二つ以上の配線層を接続する少なくとも一つのビア部と、少なくとも一つのビア部に設けられ、接続される二つ以上の配線層のうちの一端側の配線層から、二つ以上の配線層のうちの他端側の配線層に向けて突設された絶縁材料からなる突起部と、を有し、突起部の頂部は、接続される二つ以上の配線層のうちの他端側の配線層まで達すると共に、突起部の外表面に被覆された導電性金属膜で、接続される二つ以上の配線層のそれぞれが導通する、多層配線基板が提供される。   According to one embodiment, a multilayer wiring board in which a plurality of wiring layers and insulating layers are alternately stacked, and among the plurality of wiring layers, at least one via portion that connects two or more wiring layers; Provided in at least one via portion and projecting from the wiring layer on one end of the two or more wiring layers connected to the wiring layer on the other end of the two or more wiring layers A protrusion made of an insulating material, and the top of the protrusion reaches the wiring layer on the other end of the two or more connected wiring layers, and the conductive surface coated on the outer surface of the protrusion. Provided is a multilayer wiring board in which each of two or more wiring layers to be connected is conductive with a conductive metal film.

他の形態によれば、ビア部を備える多層配線基板の製造方法であって、第一の絶縁層上に、第一の配線層を形成し、ビア部と接続する第一の配線層のランド部に、絶縁材料からなり、ランド部より狭い底面を有する突起部を突設し、突起部の外表面とランド部とに、導電性金属膜を形成し第一の配線層に導通し、第一の配線層上に絶縁層及び配線層の組を少なくとも一組を形成し、導通させる配線層ごとに導電性金属膜の表面にさらに導電性金属膜を形成して各配線層との導通を図る、多層配線基板の製造方法が提供される。   According to another aspect, there is provided a method for manufacturing a multilayer wiring board including a via portion, wherein the first wiring layer is formed on the first insulating layer and connected to the via portion. Protruding parts made of an insulating material and having a bottom surface narrower than the land part are formed on the part, and a conductive metal film is formed on the outer surface of the projecting part and the land part to conduct to the first wiring layer. Form at least one set of an insulating layer and a wiring layer on one wiring layer, and further form a conductive metal film on the surface of the conductive metal film for each wiring layer to be electrically connected to each other. A method for manufacturing a multilayer wiring board is provided.

開示の多層配線基板は、接続される二つ以上の配線層の他端側の配線層まで達する頂部を有する突起部を備え、突起部に、接続される配線層のそれぞれの導電性金属膜が重なる。そのため、例えば配線層の導電性金属膜とビア部との接合面積が確保され、配線層とビア部との密着性が増大し、ビア部の剥離を防止するという効果がある。   The disclosed multilayer wiring board includes a protrusion having a top reaching the wiring layer on the other end side of two or more connected wiring layers, and each conductive metal film of the connected wiring layer is provided on the protrusion. Overlap. For this reason, for example, a bonding area between the conductive metal film of the wiring layer and the via portion is secured, the adhesion between the wiring layer and the via portion is increased, and there is an effect that peeling of the via portion is prevented.

開示の多層配線基板を示す平面図である。It is a top view which shows the multilayer wiring board of an indication. (a)は多層配線基板のビア部を示す斜視図、(b)は(a)のII−II線に沿った断面図である。(A) is a perspective view which shows the via part of a multilayer wiring board, (b) is sectional drawing along the II-II line of (a). 多層配線基板を製造する方法を示すフローチャートである。It is a flowchart which shows the method of manufacturing a multilayer wiring board. (a)は、図3に示す工程S1における、開示する多層配線基板の一部を示す斜視図、(b)は(a)のIV−IV線に沿った断面図である。(A) is a perspective view which shows a part of multilayer multilayer board | substrate to disclose in process S1 shown in FIG. 3, (b) is sectional drawing along the IV-IV line of (a). (a)は、図3に示す工程S2における、開示する多層配線基板の一部を示す斜視図、(b)は(a)のV−V線に沿った断面図である。(A) is a perspective view which shows a part of multilayer multilayer board | substrate to disclose in process S2 shown in FIG. 3, (b) is sectional drawing along the VV line of (a). (a)は、図3に示す工程S3における、開示する多層配線基板の一部を示す斜視図、(b)は(a)のVI−VI線に沿った断面図である。(A) is a perspective view which shows a part of disclosed multilayer wiring board in process S3 shown in FIG. 3, (b) is sectional drawing along the VI-VI line of (a). (a)は、図3に示す工程S4における、開示する多層配線基板の一部を示す斜視図、(b)は(a)のVII−VII線に沿った断面図である。(A) is a perspective view which shows a part of multilayer multilayer board | substrate to disclose in process S4 shown in FIG. 3, (b) is sectional drawing along the VII-VII line of (a). (a)は、図3に示す工程S5における、開示する多層配線基板の一部を示す斜視図、(b)は(a)のVIII−VIII線に沿った断面図である。(A) is a perspective view which shows a part of multilayer multilayer board | substrate to disclose in process S5 shown in FIG. 3, (b) is sectional drawing along the VIII-VIII line of (a). (a)は、図3に示す工程S6における、開示する多層配線基板の一部を示す斜視図、(b)は(a)のIX−IX線に沿った断面図である。(A) is a perspective view which shows a part of multilayer multilayer board | substrate to disclose in process S6 shown in FIG. 3, (b) is sectional drawing along the IX-IX line of (a). 4層の配線層及び絶縁層を有する多層配線基板の断面図である。It is sectional drawing of the multilayer wiring board which has a four-layer wiring layer and an insulating layer. 従来の多層配線基板を示す断面図である。It is sectional drawing which shows the conventional multilayer wiring board.

以下、添付図面を用いて本出願の実施の形態を、具体的な実施例に基づいて詳細に説明する。以下の実施の形態において同一又は類似の要素には共通の参照符号を付けて示し、理解を容易にするために、これらの図面は縮尺を適宜変更している。   Hereinafter, embodiments of the present application will be described in detail based on specific examples with reference to the accompanying drawings. In the following embodiments, the same or similar elements are denoted by common reference numerals, and these drawings are appropriately changed in scale for easy understanding.

図1は、3層の配線層及び3層の絶縁層を有する多層配線基板1を示す平面図であり、多層配線基板1の3層の配線層のうち、第三の配線層32に複数のパッド2a〜2lが配置されている。多層配線基板1では、パッド2d〜2fは、それぞれ、第三の配線層32(他端側の配線層)に設けられた配線32bにより直接、パッド2j〜2lに接続している。一方、パッド2a〜2cは、ビア部3a〜3fを介して一旦、多層配線基板1の第三の配線層32の反対側に位置する第一の配線層12(一端側の配線層の一例)又は、第一の配線層12と第三の配線層32との間に位置する第二の配線層22と接続し、パッド2g〜2iに接続する。例えば、パッド2aは、ビア部3a及び3dが中間層の第二の配線層22の配線22b(1点鎖線で示す)と、第一の配線層12の配線12b(点線で示す)とに接続することによりパッド2g及び2iに接続している。このように、ビア部3a〜3iを利用することで、パッド2a〜2lのそれぞれは交差することなく接続できる。   FIG. 1 is a plan view showing a multilayer wiring board 1 having three wiring layers and three insulating layers. Among the three wiring layers of the multilayer wiring board 1, a plurality of wiring layers 32 are arranged on a third wiring layer 32. Pads 2a to 2l are arranged. In the multilayer wiring board 1, the pads 2 d to 2 f are directly connected to the pads 2 j to 2 l by wirings 32 b provided on the third wiring layer 32 (wiring layer on the other end side), respectively. On the other hand, the pads 2a to 2c are temporarily connected to the first wiring layer 12 on the opposite side of the third wiring layer 32 of the multilayer wiring board 1 through the via portions 3a to 3f (an example of the wiring layer on one end side). Or it connects with the 2nd wiring layer 22 located between the 1st wiring layer 12 and the 3rd wiring layer 32, and connects with the pads 2g-2i. For example, the pad 2a is connected to the wiring 22b (shown by a one-dot chain line) of the second wiring layer 22 of which the via portions 3a and 3d are intermediate layers and the wiring 12b (shown by a dotted line) of the first wiring layer 12. By doing so, it is connected to the pads 2g and 2i. Thus, by using the via portions 3a to 3i, the pads 2a to 2l can be connected without crossing each other.

図2は、本実施形態の多層配線基板1に設けられたビア部3a(以下、単にビア部3と称する)の部分だけを拡大して示す図であり、(a)は多層配線基板1を拡大して示す斜視図、(b)は(a)のII−II線に沿った断面図である。   FIG. 2 is an enlarged view showing only a portion of a via portion 3a (hereinafter simply referred to as a via portion 3) provided in the multilayer wiring board 1 of the present embodiment. The perspective view which expands and shows, (b) is sectional drawing along the II-II line of (a).

図2(a)及び(b)に示すように、多層配線基板1は、3つの配線層(第一の配線層12、第二の配線層22、第三の配線層32)と3つの絶縁層(第一の絶縁層11、第二の絶縁層21、第三の絶縁層31)が交互に積層された多層配線基板である。そして、図示しないが、図2(a)及び(b)に示す第三の配線層32はパッド2aに接続し、第二の配線層22はパッド2gに、第一の配線層12はパッド2iに接続する。   As shown in FIGS. 2A and 2B, the multilayer wiring board 1 includes three wiring layers (a first wiring layer 12, a second wiring layer 22, and a third wiring layer 32) and three insulating layers. This is a multilayer wiring board in which layers (first insulating layer 11, second insulating layer 21, and third insulating layer 31) are alternately stacked. Although not shown, the third wiring layer 32 shown in FIGS. 2A and 2B is connected to the pad 2a, the second wiring layer 22 is connected to the pad 2g, and the first wiring layer 12 is the pad 2i. Connect to.

図2(b)に示すように、多層配線基板1の第一の配線層12、第二の配線層22、第三の配線層32は、ビア部3により接続されている。ビア部3は、多層配線基板1の第一の配線層12に、第一の配線層側から第三の配線層側に向けて(図2(b)の矢印B方向)突設された突起部14を有する。突起部14は絶縁材料から形成されており、突起部14の頂部14aは、接続される配線層のうち第三の配線層32まで達するよう形成される。突起部14の外表面は導電性金属膜15で覆われており、導電性金属膜15は第一の配線層のランド部12aと接続する。そして、導電性金属膜15には第二の配線層22の導電性金属膜22aが重なっている。さらに突起部14の頂部14aにおいてが、第三の配線層32の導電性金属膜32aが重なっている。ビア部3の導電性金属膜15が、ビア部3の底面側で第一の配線層12のランド部12aと接続し、ランド部12aが第一の配線層12の配線12bと接続する。第二の配線層22の導電性金属膜22aは配線22bに接続し、第三の配線層32の導電性金属膜32aは配線32bに接続する。これにより、第一の配線層12、第二の配線層22及び第三の配線層32が導通する。また、突起部14を設けることにより、突起部14とランド部12aとの接合部分14bの面積が確保される。さらに、導電性金属膜15がランド部12aに重なるため、ビア部3とランド部12aの接合面積が確保され、第一の配線層12とビア部3との密着性が向上する。また、第二の配線層22の導電性金属膜22aが、第一の配線層12の導電性金属膜15の一部を覆うことで、第二の配線層22とビア部3との接合面積が確保される。さらに、第三の配線層32の導電性金属膜32aが第二の配線層22の導電性金属膜22aの一部を覆うことで、第三の配線層32とビア部3との接合面積が確保される。そのため、配線層とビア部3との密着性が向上する。   As shown in FIG. 2B, the first wiring layer 12, the second wiring layer 22, and the third wiring layer 32 of the multilayer wiring board 1 are connected by the via portion 3. The via portion 3 is a protrusion that is provided on the first wiring layer 12 of the multilayer wiring board 1 so as to project from the first wiring layer side to the third wiring layer side (in the direction of arrow B in FIG. 2B). Part 14. The protrusion 14 is made of an insulating material, and the top 14a of the protrusion 14 is formed so as to reach the third wiring layer 32 of the connected wiring layers. The outer surface of the protrusion 14 is covered with a conductive metal film 15, and the conductive metal film 15 is connected to the land portion 12a of the first wiring layer. The conductive metal film 15 is overlaid with the conductive metal film 22 a of the second wiring layer 22. Further, the conductive metal film 32 a of the third wiring layer 32 overlaps with the top portion 14 a of the protrusion 14. The conductive metal film 15 of the via part 3 is connected to the land part 12 a of the first wiring layer 12 on the bottom side of the via part 3, and the land part 12 a is connected to the wiring 12 b of the first wiring layer 12. The conductive metal film 22a of the second wiring layer 22 is connected to the wiring 22b, and the conductive metal film 32a of the third wiring layer 32 is connected to the wiring 32b. Thereby, the 1st wiring layer 12, the 2nd wiring layer 22, and the 3rd wiring layer 32 conduct. In addition, by providing the protruding portion 14, the area of the joint portion 14b between the protruding portion 14 and the land portion 12a is secured. Furthermore, since the conductive metal film 15 overlaps the land portion 12a, a bonding area between the via portion 3 and the land portion 12a is ensured, and adhesion between the first wiring layer 12 and the via portion 3 is improved. Further, the conductive metal film 22 a of the second wiring layer 22 covers a part of the conductive metal film 15 of the first wiring layer 12, so that the junction area between the second wiring layer 22 and the via part 3 is covered. Is secured. Furthermore, since the conductive metal film 32a of the third wiring layer 32 covers a part of the conductive metal film 22a of the second wiring layer 22, the bonding area between the third wiring layer 32 and the via portion 3 is increased. Secured. Therefore, the adhesion between the wiring layer and the via part 3 is improved.

さらに、各配線層のそれぞれの導電性金属膜15、22a、32aが、突起部14の頂部14aを含むよう重なることから、導電性金属膜15、22a、32aにより突起部14が第一の配線層12側に押圧される。それにより第一の配線層12とビア部3との密着性が向上する。   Furthermore, since the respective conductive metal films 15, 22a, 32a of each wiring layer overlap so as to include the top part 14a of the protrusion 14, the conductive metal films 15, 22a, 32a cause the protrusion 14 to be the first wiring. It is pressed to the layer 12 side. Thereby, the adhesion between the first wiring layer 12 and the via part 3 is improved.

突起部14は、図2(b)に示すように、第一の配線層12から第三の配線層32(図2(b)の矢印B方向に)向かうに従い突起部14の横断面の面積が小さくなるように、先細に形成される。本実施形態では、導電性金属膜15は、銀、銅等が含まれる金属インクを塗布し焼成することで形成される。突起部14を先細に形成することで突起部14の側部が傾斜し、導電性金属膜15を形成する際に吹き付ける金属インクが、突起部14の外表面に付着しやすくなる。金属インクは、導通可能な金属であれば銀・銅以外の金属を使用してもよい。   As shown in FIG. 2B, the projecting portion 14 has an area of a cross section of the projecting portion 14 from the first wiring layer 12 toward the third wiring layer 32 (in the direction of arrow B in FIG. 2B). Is formed so as to be small. In the present embodiment, the conductive metal film 15 is formed by applying and baking a metal ink containing silver, copper, or the like. By forming the protrusions 14 in a tapered manner, the side portions of the protrusions 14 are inclined, and the metal ink sprayed when forming the conductive metal film 15 is likely to adhere to the outer surface of the protrusions 14. The metal ink may be a metal other than silver / copper as long as it is a conductive metal.

また、突起部14は、図2(b)に示すように、第一の配線層12から第三の配線層32(図2(b)の矢印B方向に)向かうに従い突起部14の横断面積が小さくなる段差形状を有する。これにより、突起部14の外表面に、導電性金属膜15を形成する際の金属インクが付着しやすくなる。本実施形態では、層ごとに一段の段差が形成されているが、この段差は層ごとに複数の段差が形成されてもよい。   Further, as shown in FIG. 2B, the projecting portion 14 has a cross-sectional area of the projecting portion 14 from the first wiring layer 12 toward the third wiring layer 32 (in the direction of arrow B in FIG. 2B). Has a stepped shape. Thereby, the metal ink at the time of forming the conductive metal film 15 is likely to adhere to the outer surface of the protrusion 14. In the present embodiment, one step is formed for each layer, but a plurality of steps may be formed for each layer.

突起部14は、突起部14が突設された第一の配線層12のランド部12aより狭い底面を有する。また、ランド部12aの周囲には、導電性金属膜15を形成する際、ランド部12aを超えてインク状の導電性金属膜15(金属インク)が広がらないよう、予め定められた厚さT1を有する塞き止め部13が設けられている。塞き止め部13の厚さT1は第一の配線層12の厚さT2よりも大きい。   The protruding portion 14 has a bottom surface that is narrower than the land portion 12a of the first wiring layer 12 on which the protruding portion 14 protrudes. Further, when the conductive metal film 15 is formed around the land portion 12a, a predetermined thickness T1 is set so that the ink-like conductive metal film 15 (metal ink) does not spread beyond the land portion 12a. A blocking portion 13 having the following is provided. The thickness T1 of the blocking portion 13 is larger than the thickness T2 of the first wiring layer 12.

本実施形態の多層配線基板1の第一の絶縁層11は、他の絶縁層21、31より厚く形成されており、多層配線基板1の基板となっている。   The first insulating layer 11 of the multilayer wiring board 1 of the present embodiment is formed to be thicker than the other insulating layers 21 and 31, and serves as a substrate for the multilayer wiring board 1.

次に、図3〜図9を用いて、本実施形態の多層配線基板1の製造方法を説明する。図3は多層配線基板1の製造方法の手順を示すフローチャートである。図4〜図9は、図3に示す各工程おける多層配線基板1の一部を示す斜視図及びその断面図である。   Next, the manufacturing method of the multilayer wiring board 1 of this embodiment is demonstrated using FIGS. FIG. 3 is a flowchart showing the procedure of the method for manufacturing the multilayer wiring board 1. 4 to 9 are a perspective view and a sectional view showing a part of the multilayer wiring board 1 in each step shown in FIG.

本実施形態において、多層配線基板1はインクジェット印刷法により製造される。まず工程S1では、図4に示すように、基板である第一の絶縁層11の上の第一の配線層12に配線パターンを形成する。配線パターンとして、第一の配線層12には、ビア部3が設けられる位置に予め定められた面積を有するランド部12aと、ランド部12aに接続する配線12bとが形成される。   In this embodiment, the multilayer wiring board 1 is manufactured by an ink jet printing method. First, in step S1, as shown in FIG. 4, a wiring pattern is formed on the first wiring layer 12 on the first insulating layer 11 which is a substrate. As the wiring pattern, the first wiring layer 12 is formed with a land portion 12a having a predetermined area at a position where the via portion 3 is provided and a wiring 12b connected to the land portion 12a.

工程S2では、図5に示すよう、第一の配線層12のランド部12aの外周部に、塞き止め部13を形成する。塞き止め部13は、インクジェット印刷法により、第一の配線層12の厚さT2より大きい厚さT1で形成される。塞き止め部13を設けることで、突起部14の外表面に導電性金属膜15となる金属インクを塗布する際、ランド部12aから金属インクが流出することを防止することができる。塞き止め部13は、絶縁材料からなり、例えば即時硬化型の樹脂材料を用いて形成される。即時硬化型の樹脂材料として、例えばUV照射にて硬化する樹脂を用いた場合、塗布した樹脂に高圧水銀ランプにて1000mJ/cm2の照射を行い硬化させる。 In step S2, a blocking portion 13 is formed on the outer peripheral portion of the land portion 12a of the first wiring layer 12, as shown in FIG. The blocking portion 13 is formed with a thickness T1 larger than the thickness T2 of the first wiring layer 12 by an ink jet printing method. By providing the blocking portion 13, it is possible to prevent the metal ink from flowing out from the land portion 12 a when the metal ink that becomes the conductive metal film 15 is applied to the outer surface of the protruding portion 14. The blocking portion 13 is made of an insulating material, and is formed using, for example, an immediately curable resin material. For example, when a resin that is cured by UV irradiation is used as the immediate curing resin material, the applied resin is irradiated with 1000 mJ / cm 2 with a high-pressure mercury lamp and cured.

工程S3では、図6に示すよう、ランド部12aのほぼ中央付近に突起部14を形成する。突起部14は絶縁材料からなり、例えばインクジェット印刷法により、即時硬化型の樹脂材料を塗布して形成する。突起部14の形成は、突起部14の頂部14aが、上層である第三の配線層32に達するよう、言い換えれば突起部14の頂部14aのランド部12aからの高さH1(図2参照)が第三の配線層32の上面より以上の高さとなるように、必要に応じてインクジェット印刷及び硬化を繰り返しておこなう。突起部14は、図6に示すように、その横断面の面積が、第一の配線層12から第三の配線層32に向かうに従い縮小するように、すなわち突起部14が先細になるよう形成する。また、図6に示すように、突起部14を形成する際、突起部14の外面には層ごとに横断面の面積が縮小するように段差形状が形成されてもよい。   In step S3, as shown in FIG. 6, the protrusion 14 is formed near the center of the land 12a. The protrusion 14 is made of an insulating material, and is formed by applying an immediately curable resin material by, for example, an ink jet printing method. The protrusion 14 is formed so that the top 14a of the protrusion 14 reaches the upper third wiring layer 32, in other words, the height H1 of the top 14a of the protrusion 14 from the land 12a (see FIG. 2). Ink jet printing and curing are repeated as necessary so that the height is higher than the upper surface of the third wiring layer 32. As shown in FIG. 6, the protrusion 14 is formed such that the area of the cross section decreases as it goes from the first wiring layer 12 to the third wiring layer 32, that is, the protrusion 14 is tapered. To do. Further, as shown in FIG. 6, when forming the protrusion 14, a step shape may be formed on the outer surface of the protrusion 14 so that the area of the cross section is reduced for each layer.

この突起部14の横断面の面積については所望する配線密度より決定される。例として従来のビア部であって、最下層の配線層(一端側の配線層)との接合部分(図11の接合部分117)がφ200μm、突起部の側部のテーパー角度が70°、各層間の絶縁膜厚さが20μm、他端側の配線層の接合部分が印刷ずれを起こすことを考慮し穴径+200μm(半径+100μm)にて作製された3層構造のビア部を置き換える場合を想定する。従来の多層配線基板では他端側の配線層では約φ630μmのビア部が形成されることになる。これを、本実施形態の突起部である突起形状に置き換えると、同じ印刷ずれ量を考慮した場合でも、多層配線基板の一端側の配線層112では約φ430μmで突起部14を形成することが可能となる。したがって、一端側の配線層における接合面積を従来と比較すると約4.6倍に拡大させることができ、これにより良好な密着性を確保することが可能となる。   The area of the cross section of the protrusion 14 is determined by the desired wiring density. As an example, it is a conventional via portion, where the joint portion (joint portion 117 in FIG. 11) with the lowermost wiring layer (wiring layer on one end side) is φ200 μm, the taper angle of the side portion of the protrusion is 70 °, In consideration of the fact that the insulating film thickness between layers is 20 μm and the joint portion of the wiring layer on the other end side causes printing misalignment, it is assumed that a via portion having a three-layer structure with a hole diameter +200 μm (radius +100 μm) is replaced. To do. In the conventional multilayer wiring board, a via portion of about φ630 μm is formed in the wiring layer on the other end side. If this is replaced with the projection shape which is the projection portion of the present embodiment, the projection portion 14 can be formed with about φ430 μm in the wiring layer 112 on one end side of the multilayer wiring board even when the same printing deviation amount is taken into consideration. It becomes. Therefore, the bonding area in the wiring layer on the one end side can be increased by about 4.6 times compared with the conventional one, thereby ensuring good adhesion.

工程S4では、図7に示すようにインクジェット印刷法により、突起部14の外表面に金属インクの塗布及び焼成を行い、ビア部3の導電性金属膜15を形成する。金属インクを噴射すると、金属インクは突起部14の外表面に付着するとともに、突起部14の底部付近からランド部12a上に流れる。これにより、第一の配線層12と、他の第二の配線層22、第三の配線層32とを接続する導電性金属膜15が一体的に形成される。金属インクは、工程S2で形成した塞き止め部13により塞き止められ、それにより所望しない部分、すなわちランド部12aの外側に漏れ広がることを防止することができる。   In step S4, as shown in FIG. 7, a metal ink is applied and baked on the outer surface of the protrusion 14 by an ink jet printing method to form the conductive metal film 15 of the via 3. When the metal ink is ejected, the metal ink adheres to the outer surface of the protrusion 14 and flows from the vicinity of the bottom of the protrusion 14 onto the land portion 12a. Thereby, the conductive metal film 15 that connects the first wiring layer 12 to the other second wiring layer 22 and the third wiring layer 32 is integrally formed. The metal ink is blocked by the blocking portion 13 formed in the step S2, thereby preventing leakage from spreading to an undesired portion, that is, the outside of the land portion 12a.

金属インクを金属化する焼成については、金属インクの金属化条件に合わせて行う。例えば約150℃にて約1時間の焼成を行う。   The firing for metallizing the metal ink is performed in accordance with the metallization conditions of the metal ink. For example, baking is performed at about 150 ° C. for about 1 hour.

工程S5では、図8に示すようにインクジェット印刷法により、第一の配線層12上に第二の絶縁層21の形成を行う。第二の絶縁層21の形成は、ビア部3を除いて行い、第二の配線層22の導電性金属膜22aとビア部3の導電性金属膜15とが導通できるようにする。   In step S5, as shown in FIG. 8, the second insulating layer 21 is formed on the first wiring layer 12 by an ink jet printing method. The formation of the second insulating layer 21 is performed except for the via portion 3 so that the conductive metal film 22a of the second wiring layer 22 and the conductive metal film 15 of the via portion 3 can conduct.

工程S6では、図9に示すようにインクジェット印刷法により、第二の配線層22の導電性金属膜22aとそれに接続する配線22bとを形成する。   In step S6, as shown in FIG. 9, the conductive metal film 22a of the second wiring layer 22 and the wiring 22b connected thereto are formed by the ink jet printing method.

工程S7では、形成した配線層の数が所望する配線層の数に達していない場合、すなわち工程S6で形成した配線層が最後の配線層でない場合(工程S7の「いいえ」)は、絶縁層の形成(工程S5)及び配線層の形成(工程S6)を繰り返し行う。所望する配線層の数に達している、すなわち形成した配線層が最後の配線層である場合(工程7の「はい」)は、接続する配線層及び絶縁層の製造が終了する。本実施形態では、さらに、第三の絶縁層31及び第三の配線層32を形成し、図2に示す多層配線基板1を完成させる。   In step S7, if the number of formed wiring layers does not reach the desired number of wiring layers, that is, if the wiring layer formed in step S6 is not the last wiring layer (“No” in step S7), the insulating layer (Step S5) and wiring layer formation (step S6) are repeated. When the desired number of wiring layers is reached, that is, when the formed wiring layer is the last wiring layer (“Yes” in step 7), the manufacturing of the wiring layer and the insulating layer to be connected is completed. In the present embodiment, a third insulating layer 31 and a third wiring layer 32 are further formed to complete the multilayer wiring board 1 shown in FIG.

本実施形態では3層の配線層及び3層の絶縁層を有する多層配線基板1を説明したが、ビア部4を図10に示すように4層の配線層(第一の配線層12、第二の配線層22、第三の配線層32、第四の配線層42)と4層の絶縁層(第一の絶縁層11、第二の絶縁層21、第三の絶縁層31、第四の絶縁層41)が交互に配置された多層配線基板2に適用してもよい。   In the present embodiment, the multilayer wiring board 1 having three wiring layers and three insulating layers has been described. However, the via portion 4 includes four wiring layers (first wiring layer 12, first wiring layer) as shown in FIG. Second wiring layer 22, third wiring layer 32, fourth wiring layer 42) and four insulating layers (first insulating layer 11, second insulating layer 21, third insulating layer 31, fourth wiring layer 42) The insulating layer 41) may be applied to the multilayer wiring board 2 arranged alternately.

以上、本出願を特にその好ましい実施の形態を参照して詳細に説明した。本出願の容易な理解のために、本出願の具体的な形態を以下に付記する。   The present application has been described in detail with particular reference to preferred embodiments thereof. For easy understanding of the present application, specific forms of the present application are appended below.

(付記1)複数の配線層及び絶縁層が交互に積層される多層配線基板であって、
前記複数の配線層のうち、二つ以上の配線層を接続する少なくとも一つのビア部と、
前記少なくとも一つのビア部に設けられ、接続される前記二つ以上の配線層のうちの一端側の配線層から、前記二つ以上の配線層のうちの他端側の配線層に向けて突設された絶縁材料からなる突起部と、を有し、
前記突起部の頂部は、接続される前記二つ以上の配線層のうちの他端側の配線層まで達すると共に、前記突起部の外表面に被覆された導電性金属膜で、接続される前記二つ以上の配線層のそれぞれが導通する、多層配線基板。
(付記2)前記突起部は、前記一端側の配線層から、前記他端側の配線層に向かうに従い前記突起部の横断面の面積が小さくなるよう形成される、付記1に記載の多層配線板。
(付記3)前記突起部は、前記一端側の配線層から、前記他端側の配線層に向かうに従い前記突起部の横断面の面積が小さくなる段差形状を有する、付記1又は2に記載の多層配線板。
(付記4)接続される前記二つ以上の配線層のうち一端側の配線層以外の配線層の導電性金属膜は、前記突起部の頂部を覆うように形成される、付記1から3のいずれかに記載の多層配線板。
(Appendix 1) A multilayer wiring board in which a plurality of wiring layers and insulating layers are alternately laminated,
Among the plurality of wiring layers, at least one via portion connecting two or more wiring layers;
The one or more wiring layers provided in the at least one via portion and connected to one end of the wiring layer project from the wiring layer on the other end side of the two or more wiring layers. A projection made of an insulating material provided,
The top of the protrusion reaches the wiring layer on the other end side of the two or more wiring layers to be connected and is connected with the conductive metal film coated on the outer surface of the protrusion. A multilayer wiring board in which each of two or more wiring layers conducts.
(Supplementary note 2) The multilayer wiring according to supplementary note 1, wherein the protrusion is formed so that a cross-sectional area of the protrusion decreases from the wiring layer on the one end side toward the wiring layer on the other end side. Board.
(Supplementary note 3) The supplementary note 1 or 2, wherein the protruding portion has a step shape in which an area of a cross section of the protruding portion decreases from the wiring layer on the one end side toward the wiring layer on the other end side. Multilayer wiring board.
(Appendix 4) The conductive metal film of the interconnect layer other than the interconnect layer on one end side of the two or more interconnect layers to be connected is formed so as to cover the top of the protrusion, The multilayer wiring board in any one.

(付記5)ビア部を備える多層配線基板の製造方法であって、第一の絶縁層に、第一の配線層を形成し、前記ビア部と接続する前記第一の配線層のランド部に、絶縁材料からなり、前記ランド部より狭い底面を有する突起部を突設し、前記突起部の外表面と前記ランド部とに導電性金属膜を形成し前記第一の配線層に導通し、前記第一の配線層上に絶縁層及び配線層の組を少なくとも一組を形成し、導通させる配線層ごとに前記導電性金属膜の表面にさらに導電性金属膜を形成して各配線層との導通を図る、多層配線基板の製造方法。
(付記6)前記突起部の外表面に導電性金属膜を塗布する前に、前記ランド部の外周に、予め定められた高さを有する塞き止め部を形成すること、を含む付記5に記載の多層配線基板の製造方法。
(Additional remark 5) It is a manufacturing method of a multilayer wiring board provided with a via part, Comprising: The 1st wiring layer is formed in the 1st insulating layer, and the land part of the 1st wiring layer connected with the via part A protrusion made of an insulating material and having a bottom surface narrower than the land, and a conductive metal film is formed on the outer surface of the protrusion and the land to conduct to the first wiring layer, At least one set of an insulating layer and a wiring layer is formed on the first wiring layer, and a conductive metal film is further formed on the surface of the conductive metal film for each wiring layer to be conducted. The manufacturing method of a multilayer wiring board which aims at electrical conduction.
(Appendix 6) In appendix 5, including forming a blocking portion having a predetermined height on the outer periphery of the land portion before applying a conductive metal film to the outer surface of the protrusion portion. The manufacturing method of the multilayer wiring board as described.

1、1a 多層配線基板
2a〜2l パッド
3、3a〜3f、4 ビア部
11 第一の絶縁層(基板)
12 第一の配線層
12a ランド部
12b、22b、32b 配線
13 塞き止め部
14 突起部
14a 頂部
14b 接合部分
15、22a、32a 導電性金属膜
21 第二の絶縁層
22 第二の配線層
31 第三の絶縁層
32 第三の配線層
41 第四の絶縁層
42 第四の配線層
DESCRIPTION OF SYMBOLS 1, 1a Multilayer wiring board 2a-2l Pad 3, 3a-3f, 4 Via part 11 1st insulating layer (board | substrate)
DESCRIPTION OF SYMBOLS 12 1st wiring layer 12a Land part 12b, 22b, 32b Wiring 13 Blocking part 14 Protrusion part 14a Top part 14b Joining part 15, 22a, 32a Conductive metal film 21 2nd insulating layer 22 2nd wiring layer 31 Third insulating layer 32 Third wiring layer 41 Fourth insulating layer 42 Fourth wiring layer

Claims (6)

複数の配線層及び絶縁層が交互に積層される多層配線基板であって、
前記複数の配線層のうち、二つ以上の配線層を接続する少なくとも一つのビア部と、
前記少なくとも一つのビア部に設けられ、接続される前記二つ以上の配線層のうちの一端側の配線層から、前記二つ以上の配線層のうちの他端側の配線層に向けて突設された絶縁材料からなる突起部と、を有し、
前記突起部の頂部は、接続される前記二つ以上の配線層のうちの他端側の配線層まで達すると共に、前記突起部の外表面に被覆された導電性金属膜で、接続される前記二つ以上の配線層のそれぞれが導通する、多層配線基板。
A multilayer wiring board in which a plurality of wiring layers and insulating layers are alternately laminated,
Among the plurality of wiring layers, at least one via portion connecting two or more wiring layers;
The one or more wiring layers provided in the at least one via portion and connected to one end of the wiring layer project from the wiring layer on the other end side of the two or more wiring layers. A projection made of an insulating material provided,
The top of the protrusion reaches the wiring layer on the other end side of the two or more wiring layers to be connected and is connected with the conductive metal film coated on the outer surface of the protrusion. A multilayer wiring board in which each of two or more wiring layers conducts.
前記突起部は、前記一端側の配線層から前記他端側の配線層に向かうに従い前記突起部の横断面の面積が小さくなるよう形成される、請求項1に記載の多層配線基板。   2. The multilayer wiring board according to claim 1, wherein the projecting portion is formed so that an area of a cross section of the projecting portion decreases from the wiring layer on the one end side toward the wiring layer on the other end side. 前記突起部は、前記一端側の配線層から前記他端側の配線層に向かうに従い前記突起部の横断面の面積が小さくなる段差形状を有する、請求項1又は2に記載の多層配線基板。   3. The multilayer wiring board according to claim 1, wherein the protruding portion has a stepped shape in which a cross-sectional area of the protruding portion decreases from the wiring layer on the one end side toward the wiring layer on the other end side. 接続される前記二つ以上の配線層のうち一端側の配線層以外の配線層の導電性金属膜は、前記突起部の頂部を覆うように形成される、請求項1から3の何れか一項に記載の多層配線基板。   4. The conductive metal film of a wiring layer other than the wiring layer on one end side of the two or more wiring layers to be connected is formed so as to cover a top portion of the protruding portion. A multilayer wiring board according to the item. ビア部を備える多層配線基板の製造方法であって、
第一の絶縁層上に、第一の配線層を形成し、
前記ビア部と接続する前記第一の配線層のランド部に、絶縁材料からなり、前記ランド部より狭い底面を有する突起部を突設し、
前記突起部の外表面と前記ランド部とに、導電性金属膜を形成し前記第一の配線層に導通し、
前記第一の配線層上に絶縁層及び配線層の組を少なくとも一組を形成し、
導通させる配線層ごとに前記導電性金属膜の表面にさらに導電性金属膜を形成して各配線層との導通を図る、多層配線基板の製造方法。
A method of manufacturing a multilayer wiring board having a via portion,
Forming a first wiring layer on the first insulating layer;
The land portion of the first wiring layer connected to the via portion is made of an insulating material and has a protruding portion having a bottom surface narrower than the land portion,
Forming a conductive metal film on the outer surface of the protrusion and the land, and conducting to the first wiring layer,
Forming at least one set of an insulating layer and a wiring layer on the first wiring layer;
A method of manufacturing a multilayer wiring board, wherein a conductive metal film is further formed on the surface of the conductive metal film for each wiring layer to be conducted to achieve conduction with each wiring layer.
前記突起部の外表面に導電性金属膜を塗布する前に、前記ランド部の外周に、予め定められた高さを有する塞き止め部を形成すること、を含む請求項5に記載の多層配線基板の製造方法。   The multilayer according to claim 5, further comprising: forming a blocking portion having a predetermined height on the outer periphery of the land portion before applying a conductive metal film to the outer surface of the protruding portion. A method for manufacturing a wiring board.
JP2016054242A 2016-03-17 2016-03-17 Multilayer wiring board and method of manufacturing multilayer wiring board Expired - Fee Related JP6623870B2 (en)

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JPH0236591A (en) * 1988-07-27 1990-02-06 Fujitsu Ltd Manufacture of multilayer substrate
JPH09232760A (en) * 1996-02-26 1997-09-05 Nippon Avionics Co Ltd Multilayered printed-wiring board and manufacture thereof
JP2000332421A (en) * 1999-05-18 2000-11-30 Samsung Electro Mech Co Ltd Printed circuit substrate and manufacture thereof
JP2001144442A (en) * 1999-11-16 2001-05-25 Ibiden Co Ltd Multilayer wiring board
JP2005116560A (en) * 2003-10-02 2005-04-28 Seiko Epson Corp Semiconductor device, circuit board, and electro-optical device
JP2013048185A (en) * 2011-08-29 2013-03-07 Denso Corp Multilayer substrate, and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0236591A (en) * 1988-07-27 1990-02-06 Fujitsu Ltd Manufacture of multilayer substrate
JPH09232760A (en) * 1996-02-26 1997-09-05 Nippon Avionics Co Ltd Multilayered printed-wiring board and manufacture thereof
JP2000332421A (en) * 1999-05-18 2000-11-30 Samsung Electro Mech Co Ltd Printed circuit substrate and manufacture thereof
JP2001144442A (en) * 1999-11-16 2001-05-25 Ibiden Co Ltd Multilayer wiring board
JP2005116560A (en) * 2003-10-02 2005-04-28 Seiko Epson Corp Semiconductor device, circuit board, and electro-optical device
JP2013048185A (en) * 2011-08-29 2013-03-07 Denso Corp Multilayer substrate, and manufacturing method thereof

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