JP2007142017A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
JP2007142017A
JP2007142017A JP2005331407A JP2005331407A JP2007142017A JP 2007142017 A JP2007142017 A JP 2007142017A JP 2005331407 A JP2005331407 A JP 2005331407A JP 2005331407 A JP2005331407 A JP 2005331407A JP 2007142017 A JP2007142017 A JP 2007142017A
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chip
bumps
bump
semiconductor device
wiring board
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Inventor
Maiko Hishioka
麻衣子 菱岡
Isamu Aokura
勇 青倉
Takatoshi Osumi
貴寿 大隅
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005331407A priority Critical patent/JP2007142017A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent faulty connections among chips and a wiring substrate due to the concentration of stress, by enlarging the sectional areas of bumps, going from the center toward the outer periphery of a region with a plurality of bumps arranged thereon. <P>SOLUTION: The bumps between the chip 2 and the wiring substrate are arranged annularly to disperse the stress generated in the outer periphery of the chip 2, and the bumps having different diameters are arranged from the center toward the outer periphery of the chip. The diameter of the bumps 3c, at positions having maximal distance from the center of the chip 2, is larger than that of the bumps 3a, at positions having minimal distance from the center of the chip; while the diameter of the bumps 3b at intermediate positions is larger than that of the bumps 3a and smaller than that of the bumps 3c. According to this constitution, improvement in reliability can be realized regarding the jointing of the semiconductor device. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置において、半導体素子であるチップに設けた、チップと配線基板とのジョイント部分であるバンプの配置構造に係り、特に、半導体装置の各部材の熱膨張係数の差により発生する半導体素子であるチップ外周部での応力集中を防ぐ半導体装置およびその製造方法に関するものである。   The present invention relates to an arrangement structure of bumps, which are joint portions between a chip and a wiring board, provided on a chip which is a semiconductor element in a semiconductor device, and particularly occurs due to a difference in thermal expansion coefficient of each member of the semiconductor device. The present invention relates to a semiconductor device for preventing stress concentration at a chip outer periphery which is a semiconductor element, and a manufacturing method thereof.

半導体素子であるチップを配線基板に実装する際、チップと配線基板とのジョイント部分であるバンプをチップに形成し、バンプと配線基板を接合することにより実装している。   When a chip, which is a semiconductor element, is mounted on a wiring board, bumps, which are joint portions between the chip and the wiring board, are formed on the chip, and the bumps are mounted by bonding the wiring board.

以下、図面を用いて従来例を説明する。図６（ａ）は、チップを配線基板上に実装してなる半導体装置の斜視図、図６（ｂ）は、図６（ａ）の破線Ｅ−Ｅ’に沿って切断した断面図、図６（ｃ）は、バンプが形成されたチップの平面図である。   Hereinafter, a conventional example will be described with reference to the drawings. 6A is a perspective view of a semiconductor device in which a chip is mounted on a wiring board. FIG. 6B is a cross-sectional view taken along a broken line EE ′ in FIG. 6 (c) is a plan view of a chip on which bumps are formed.

従来の半導体装置１６は、チップ１０と配線基板１１を備えており、複数のバンプ１３が複数の同心円状の円周上に配置されている。配線基板表面の電極１５に対応したバンプ１３をチップ１０に形成し、チップ１０と配線基板１１とを接合する。また、チップ１０と配線基板１１間は封止樹脂１４で埋め補強する。   A conventional semiconductor device 16 includes a chip 10 and a wiring board 11, and a plurality of bumps 13 are arranged on a plurality of concentric circles. Bumps 13 corresponding to the electrodes 15 on the surface of the wiring board are formed on the chip 10, and the chip 10 and the wiring board 11 are joined. The space between the chip 10 and the wiring board 11 is filled with a sealing resin 14 and reinforced.

チップ１０と配線基板１１，バンプ１３，封止樹脂１４はそれぞれ異なる熱膨張係数をもつため、バンプ１３を配置する領域の外周部では中心部と比較してより大きな応力が加わっている。また、チップ１０の外周部では応力集中が発生する。電気的接続の信頼性を向上させるために、径の異なる複数の同心円状の円周上にバンプ１３を配置し、さらにチップ１０の四隅に補強バンプ１２を設けている。   Since the chip 10, the wiring substrate 11, the bump 13, and the sealing resin 14 have different thermal expansion coefficients, a larger stress is applied to the outer peripheral portion of the region where the bump 13 is disposed than the central portion. Further, stress concentration occurs in the outer peripheral portion of the chip 10. In order to improve the reliability of electrical connection, bumps 13 are arranged on a plurality of concentric circles having different diameters, and reinforcing bumps 12 are provided at the four corners of the chip 10.

従来例では、バンプ１３を同心円状に配置することにより、チップ１０のコーナー部へバンプを配置する場合に比べ、バンプへの応力集中は緩和されている。
特開２０００−１２４２５９号公報 In the conventional example, by arranging the bumps 13 concentrically, the stress concentration on the bumps is alleviated compared to the case where the bumps are arranged at the corners of the chip 10.
JP 2000-124259 A

しかしながら、応力は距離に大略比例して大きくなるため、同心円状に配置されたバンプ配置では、同心円の径の大きい円周上に配置されたバンプに係る応力は、同心円の径の小さい円周上に配置されたバンプに係る応力より大きくなるので、外周部のバンプへの応力緩和は十分でないという問題があった。   However, since the stress increases substantially in proportion to the distance, in the bump arrangement arranged concentrically, the stress related to the bump arranged on the circumference having a large diameter of the concentric circle is on the circumference having a small diameter of the concentric circle. Therefore, there is a problem that stress relaxation to the bumps on the outer peripheral portion is not sufficient.

本発明は、前記従来技術の問題を解決することに指向するものであり、半導体装置の半導体素子であるチップ、配線基板、チップと配線基板とのジョイント部分であるバンプ、封止樹脂など、各部材のそれぞれの熱膨張係数の差により生じる応力を緩和できるバンプの配置構造として、複数のバンプを円形に配置し、バンプの配置される領域の中心部から外周部にかけてバンプの配置密度を高くして、応力集中によるチップ配線基板間の接合不良を防止する半導体装置およびその製造方法を提供することを目的とする。   The present invention is directed to solving the problems of the prior art, and includes a chip that is a semiconductor element of a semiconductor device, a wiring board, a bump that is a joint portion between the chip and the wiring board, a sealing resin, and the like. As a bump arrangement structure that can relieve stress caused by the difference in thermal expansion coefficient of each member, multiple bumps are arranged in a circle, and the bump arrangement density is increased from the center to the outer periphery of the area where the bumps are arranged. Thus, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that prevent a bonding failure between chip wiring boards due to stress concentration.

前記の目的を達成するために、本発明に係る請求項１に記載した半導体装置は、半導体素子であるチップと、チップを搭載する配線基板と、チップと配線基板のジョイント部分としてチップに配置し接合したバンプとを有し、バンプを配置した領域において、チップの中心からの距離の大きい位置に配置したバンプが、チップの中心からの距離の小さい位置に配置したバンプよりもバンプの断面積が大きいことを特徴とする。   In order to achieve the above object, a semiconductor device according to claim 1 of the present invention is arranged on a chip as a semiconductor element chip, a wiring board on which the chip is mounted, and a joint part between the chip and the wiring board. In the area where the bumps are arranged, the bumps arranged at a position where the distance from the center of the chip is larger than the bumps arranged at a position where the distance from the center of the chip is small. It is large.

また、請求項２，３に記載した半導体装置は、請求項１の半導体装置のバンプを配置した領域において、バンプを径の異なる同心円の円周上に配置して、同心円の大きな径の円周上に配置したバンプが、同心円の小さな径の円周上に配置したバンプよりもバンプの断面積が大きいこと、さらに、バンプの最も大きな断面積が、バンプの最も小さな断面積の６倍以下であることを特徴とする。   According to a second and third aspect of the present invention, in the semiconductor device according to the first aspect, in the region where the bumps are arranged, the bumps are arranged on the circumferences of concentric circles having different diameters. The bump placed above has a larger cross-sectional area than the bump placed on the circumference of a concentric circle with a small diameter, and the largest cross-sectional area of the bump is less than 6 times the smallest cross-sectional area of the bump. It is characterized by being.

この構成により、半導体装置を構成する各部材の各々異なった熱膨張係数により生じる応力を緩和でき、接合の信頼性を向上すること、さらに、応力集中が起こる可能性をより低くできる。   With this configuration, it is possible to relieve the stress caused by the different thermal expansion coefficients of the respective members constituting the semiconductor device, improve the reliability of bonding, and further reduce the possibility of stress concentration.

また、請求項４に記載した半導体装置は、半導体素子であるチップと、チップを搭載する配線基板と、チップと配線基板のジョイント部分としてチップに配置し接合したバンプとを有し、バンプを配置した領域において、バンプを径の異なる同心円の円周上に配置して、同心円の小さな径の円周上に配置したバンプより、同心円の大きな径の円周上に配置したバンプの数を多くしてバンプの配置密度を高くしたことを特徴とする。   According to a fourth aspect of the present invention, there is provided a semiconductor device including a chip which is a semiconductor element, a wiring board on which the chip is mounted, and a bump which is arranged and bonded to the chip as a joint portion of the chip and the wiring board. In this area, bumps are arranged on the circumference of concentric circles with different diameters, and the number of bumps arranged on the circumference of a large diameter of concentric circles is larger than the bumps arranged on the circumference of small diameters of concentric circles. The feature is that the bump arrangement density is increased.

また、請求項５に記載さいた半導体装置は、請求項４の半導体装置の円周上に配置したバンプの最も多い数が、バンプの最も少ない数の５５倍以下であることを特徴とする。   The semiconductor device described in claim 5 is characterized in that the largest number of bumps arranged on the circumference of the semiconductor device of claim 4 is 55 times or less the smallest number of bumps.

この構成により、半導体装置を構成する各部材の各々異なった熱膨張係数により生じる応力を緩和でき、接合の信頼性を向上すること、さらに、応力集中が起こる可能性をより低くできる。   With this configuration, it is possible to relieve the stress caused by the different thermal expansion coefficients of the respective members constituting the semiconductor device, improve the reliability of bonding, and further reduce the possibility of stress concentration.

また、請求項６に記載した半導体装置は、半導体素子であるチップと、チップを搭載する配線基板と、チップと配線基板のジョイント部分としてチップに配置し接合したバンプとを有し、バンプを配置した領域において、バンプをチップの中心から放射状に配置して、チップの中心から外周に向かうにつれて、配置するバンプの間隔を狭くしてバンプの配置密度を高くしたことを特徴とする。   According to a sixth aspect of the present invention, there is provided a semiconductor device including a chip which is a semiconductor element, a wiring board on which the chip is mounted, and a bump which is arranged and bonded to the chip as a joint portion between the chip and the wiring board. In this area, bumps are arranged radially from the center of the chip, and as the distance from the center of the chip toward the outer periphery, the interval between the arranged bumps is narrowed to increase the arrangement density of the bumps.

この構成により、半導体装置を構成する各部材の各々異なった熱膨張係数により生じる応力を緩和でき、接合の信頼性を向上すること、さらに、バンプを一直線上に配置して容易に形成することができる。   With this configuration, it is possible to relieve stress caused by different thermal expansion coefficients of the respective members constituting the semiconductor device, to improve the reliability of bonding, and to easily form bumps on a straight line. it can.

また、請求項７に記載した半導体装置は、請求項１〜６の半導体装置に配線基板とチップの間に充填する封止樹脂を有し、封止樹脂を、配線基板表面の電極と接合するバンプを配置した領域にのみ塗布することを特徴とする。   According to a seventh aspect of the present invention, there is provided a semiconductor device according to any one of the first to sixth aspects, wherein the semiconductor device according to any one of the first to sixth aspects has a sealing resin filled between the wiring board and the chip, and the sealing resin is bonded to the electrode on the surface of the wiring board. It is characterized in that it is applied only to the area where the bumps are arranged.

また、請求項８に記載した半導体装置は、半導体素子であるチップと、チップを搭載する配線基板と、チップと配線基板のジョイント部分としてチップの円形の領域に配置し接合したバンプと、配線基板とチップの間に充填する封止樹脂とを有し、封止樹脂を、配線基板表面の電極と接合するバンプを配置した領域にのみ塗布することを特徴とする。   According to another aspect of the present invention, there is provided a semiconductor device including a chip that is a semiconductor element, a wiring board on which the chip is mounted, a bump that is disposed and bonded to a circular area of the chip as a joint portion between the chip and the wiring board, and a wiring board. And a sealing resin filled between the chips, and the sealing resin is applied only to a region where bumps to be bonded to the electrodes on the surface of the wiring substrate are disposed.

これにより、封止樹脂により生じる応力も緩和でき接合の信頼性を向上することができる。   Thereby, the stress caused by the sealing resin can be relaxed and the reliability of the bonding can be improved.

また、請求項９に記載した半導体装置の製造方法は、半導体素子であるチップ上にチップと配線基板のジョイント部分としてバンプを円形の領域に配置して接合する工程と、配線基板に封止樹脂を塗布する工程と、封止樹脂が塗布された配線基板上にバンプを配置したチップを搭載する工程と、チップと配線基板間に充填した封止樹脂を硬化させる工程とからなる半導体装置の製造方法であって、封止樹脂の充填部分は、バンプを配置した領域であり、封止樹脂の充填部分の高さを、配線基板とチップ間の距離として、バンプを配置した領域に充填部分の高さを掛けて求めた封止樹脂の充填部分の体積から、バンプの総体積を引いて封止樹脂の塗布量を決定することを特徴とする。   According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step of placing a bump in a circular region as a joint portion between a chip and a wiring board on a chip that is a semiconductor element; A semiconductor device comprising: a step of applying a chip, a step of mounting a chip having bumps disposed on a wiring substrate coated with a sealing resin, and a step of curing the sealing resin filled between the chip and the wiring substrate The filling portion of the sealing resin is a region where the bump is arranged, and the height of the filling portion of the sealing resin is the distance between the wiring board and the chip, and the filling portion is filled in the region where the bump is arranged. The coating amount of the sealing resin is determined by subtracting the total volume of the bumps from the volume of the filling portion of the sealing resin obtained by multiplying the height.

本発明によれば、応力に大略比例したバンプの配置密度を有し、これにより、熱膨張係数の差による応力集中を緩和して、接合不良の発生を防ぐことができるという効果を奏する。   According to the present invention, the bump arrangement density is approximately proportional to the stress, thereby reducing the stress concentration due to the difference in thermal expansion coefficient and preventing the occurrence of bonding failure.

以下、図面を参照して本発明における実施の形態を詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図１（ａ）は本発明の実施の形態１におけるバンプの配置を有する半導体装置の正面図、図１（ｂ）は図１（ａ）の破線Ａ−Ａ’に沿って切断した断面図を示す図である。   1A is a front view of a semiconductor device having a bump arrangement according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along a broken line AA ′ in FIG. FIG.

本実施の形態１について図１（ａ），（ｂ）を参照しながら説明する。図１（ａ），（ｂ）に示すように、半導体素子であるチップ２のパターン形成面上で３つの同心円の円周上に配置されたバンプ３ａ，３ｂ，３ｃを有する半導体装置１ａである。本実施の形態１におけるバンプは配線基板表面の電極に対応していることとする。   The first embodiment will be described with reference to FIGS. 1 (a) and 1 (b). As shown in FIGS. 1A and 1B, a semiconductor device 1a having bumps 3a, 3b, and 3c arranged on the circumference of three concentric circles on the pattern forming surface of a chip 2 that is a semiconductor element. . The bumps in the first embodiment correspond to the electrodes on the wiring board surface.

また、３つの同心円の円周上にバンプ径の異なるバンプを配置する。最も小さい円周上に配置されたバンプ３ａ、中間の円周上に配置されたバンプ３ｂ、最も大きい円周上に配置されたバンプ３ｃとし、チップの中心から最も小さい円周上に配置されたバンプ３ａまでの距離を「１」、中間の円周上に配置されたバンプ３ｂまでの距離を「３」、最も大きい円周上に配置されたバンプ３ｃまでの距離を「５」とすると、バンプ３ｂの径はバンプ３ａの径の３倍、バンプ３ｃの径はバンプ３ａの径の５倍である。   Also, bumps having different bump diameters are arranged on the circumference of three concentric circles. The bumps 3a arranged on the smallest circumference, the bumps 3b arranged on the middle circumference, and the bumps 3c arranged on the largest circumference were arranged on the smallest circumference from the center of the chip. When the distance to the bump 3a is "1", the distance to the bump 3b arranged on the middle circumference is "3", and the distance to the bump 3c arranged on the largest circumference is "5", The diameter of the bump 3b is three times the diameter of the bump 3a, and the diameter of the bump 3c is five times the diameter of the bump 3a.

以上のように構成された半導体装置１ａについて、その原理を説明する。半導体装置１ａを構成する各部材は、各々異なった熱膨張係数をもっているため、昇温時に熱膨張係数の差による力で応力が発生し、その応力はチップ２の中心部からの距離に大略比例して大きくなる。そこで、本実施の形態１は、バンプの径を応力に合わせ変化させることで、バンプとチップ２や、バンプと配線基板表面の電極の接合面積に係る応力を均一にすることができる。   The principle of the semiconductor device 1a configured as described above will be described. Since each member constituting the semiconductor device 1a has a different thermal expansion coefficient, a stress is generated by a force due to the difference in the thermal expansion coefficient when the temperature is raised, and the stress is approximately proportional to the distance from the center portion of the chip 2. And get bigger. Therefore, in the first embodiment, by changing the bump diameter according to the stress, the stress related to the bonding area between the bump and the chip 2 or between the bump and the electrode on the wiring board surface can be made uniform.

以上の原理により、接合部に発生する応力集中を防止することができる。また、本実施の形態１は、外周部のバンプの断面積が、中心部のバンプの断面積よりも大きいことにより、外部から加わる応力に対してより大きい効果を得ることができる。   Based on the above principle, stress concentration occurring in the joint can be prevented. Further, in the first embodiment, since the cross-sectional area of the outer peripheral bump is larger than the cross-sectional area of the central bump, it is possible to obtain a greater effect on the externally applied stress.

なお、本実施の形態１では同心円の円周上に配置するバンプとしたが、同心円でなくても構わない。また、３つの円周を用いて説明をしたが、複数存在すればよい。さらに、チップ２の中心からの距離に比例させてバンプの径を大きくしたが、必ずしも比例させてバンプの径を大きくしなくても構わない。ただし、一般的に使用されるはんだバンプの場合、バンプの断面積を大きくするとほぼ比例的にバンプの高さも大きくなるため、チップ２の面内でのバンプの高さの差への許容量は１００μｍ以下である。したがって、バンプの最小断面の径を２０μｍとするとバンプの断面の面積比は６倍以下であることが望ましい。   In the first embodiment, the bumps are arranged on the circumference of a concentric circle. However, the bumps need not be concentric. Moreover, although it demonstrated using three circumferences, multiple should just exist. Further, although the bump diameter is increased in proportion to the distance from the center of the chip 2, the bump diameter need not necessarily be increased in proportion. However, in the case of generally used solder bumps, the bump height increases approximately proportionally when the bump cross-sectional area is increased, so the allowable amount for the difference in bump height in the plane of the chip 2 is 100 μm or less. Accordingly, when the diameter of the minimum cross section of the bump is 20 μm, the area ratio of the cross section of the bump is desirably 6 times or less.

また、バンプの断面の面積比を６倍より大きくすると、チップを配線基板に搭載する時、チップ２と配線基板とのジョイント部分であるバンプの形状は変形し、バンプ断面がバンプの隣接する方向に大きくなるため、隣接するバンプと接触し、ショートしてしまう問題があるので、好適には６倍以下とするのが好ましい。   If the area ratio of the bump cross section is larger than 6 times, when the chip is mounted on the wiring board, the shape of the bump, which is a joint part between the chip 2 and the wiring board, is deformed, and the bump cross section is adjacent to the bump. Therefore, there is a problem that it contacts with an adjacent bump and short-circuits.

次に、図２（ａ）は本発明の実施の形態２におけるバンプの配置を有する半導体装置の正面図、図２（ｂ）は図２（ａ）の破線Ｂ−Ｂ’に沿って切断した断面図を示す図である。   Next, FIG. 2A is a front view of the semiconductor device having the bump arrangement in the second embodiment of the present invention, and FIG. 2B is cut along the broken line BB ′ in FIG. It is a figure which shows sectional drawing.

本実施の形態２について、図２（ａ），（ｂ）を参照しながら説明する。図２（ａ），（ｂ）に示すように、半導体素子であるチップ２のパターン形成面上で３つの同心円の円周上に配置されたバンプ４ａ，４ｂ，４ｃを有する半導体装置１ｂである。本実施の形態２におけるバンプは配線基板表面の電極に対応していることとする。   The second embodiment will be described with reference to FIGS. 2 (a) and 2 (b). As shown in FIGS. 2A and 2B, the semiconductor device 1b has bumps 4a, 4b, and 4c arranged on the circumference of three concentric circles on the pattern formation surface of the chip 2 that is a semiconductor element. . The bumps in the second embodiment correspond to the electrodes on the wiring board surface.

また、３つの同心円について、最も径の小さい円周上に配置されたバンプ４ａ、中間の円周上に配置されたバンプ４ｂ、最も大きい円周上に配置されたバンプ４ｃとして、チップ２の中心からバンプ４ａまでの距離を「１」、バンプ４ｂまでの距離を「３」、バンプ４ｃまでの距離を「５」とすると、中間の円周上に配置されるバンプ４ｂの数は、最も小さい円周上に配置するバンプ４ａの数の３倍存在し、また最も大きい円周上に配置されたバンプ４ｃの数は、最も小さい円周上に配置されたバンプ４ａの数の５倍存在する。   Further, with respect to the three concentric circles, the center of the chip 2 is formed as a bump 4a arranged on the circumference having the smallest diameter, a bump 4b arranged on the middle circumference, and a bump 4c arranged on the largest circumference. When the distance from the bump 4a to the bump 4a is "1", the distance to the bump 4b is "3", and the distance to the bump 4c is "5", the number of bumps 4b arranged on the middle circumference is the smallest There are three times the number of bumps 4a arranged on the circumference, and the number of bumps 4c arranged on the largest circumference is five times the number of bumps 4a arranged on the smallest circumference. .

以上のように構成された半導体装置１ｂについて、その原理を説明する。半導体装置１ｂを構成する各部材は、各々異なった熱膨張係数をもっているため、昇温時に熱膨張係数の差による力で応力が発生し、その応力はチップ２の中心部からの距離に大略比例して大きくなる。そこで、本実施の形態２は、バンプの配置密度を応力に合わせ変化させることで、バンプとチップ２や、バンプと配線基板表面の電極の接合面積に係る応力を均一にすることができる。   The principle of the semiconductor device 1b configured as described above will be described. Since each member constituting the semiconductor device 1b has a different thermal expansion coefficient, a stress is generated by a force due to the difference in the thermal expansion coefficient when the temperature is raised, and the stress is approximately proportional to the distance from the center portion of the chip 2. And get bigger. Therefore, in the second embodiment, the stress related to the bonding area between the bump and the chip 2 or the electrode on the surface of the wiring board can be made uniform by changing the arrangement density of the bump in accordance with the stress.

以上の原理により、接合部に発生する応力集中を防止することができる。また、本実施の形態２は、バンプの配置密度を変化させ、バンプの断面積を均一にすることにより、バンプ高さのばらつきを抑えることができ、接合の信頼性向上を得ることができる。   Based on the above principle, stress concentration occurring in the joint can be prevented. Further, in the second embodiment, by changing the bump arrangement density and making the bump cross-sectional area uniform, it is possible to suppress variations in bump height and to improve the bonding reliability.

なお、本実施の形態２では同心円の円周上に配置するバンプとしたが、同心円でなくても構わない。また、３つの円周を用いて説明をしたが、複数存在すればよい。さらに、チップ２の中心からの距離に比例させてバンプの配置数を変化させたが、必ずしも比例させてバンプの数を増加させなくても構わない。ただし、チップ２を配線基板に搭載する実装時にバンプは変形して、バンプ断面はバンプの隣接する方向に大きくなり、隣接するバンプと接触してショートを起こす可能性があるので、バンプとバンプの間の距離、つまりバンプ間ピッチは、一定の間隔が必要である。いま、バンプの断面の径を２０μｍとすると、チップ２の面内でのバンプ間ピッチは４０μｍ以上とし、最も大きい円周径を９９００μｍ、最も小さい円周径を１８０μｍとした場合で計算すると、バンプの最小断面の径が２０μｍで最も多いバンプの配置数は最も少ないバンプの配置数の５５倍以下であることが望ましい。   In the second embodiment, the bumps are arranged on the circumference of a concentric circle. However, the bumps may not be a concentric circle. Moreover, although it demonstrated using three circumferences, multiple should just exist. Further, although the number of bumps arranged is changed in proportion to the distance from the center of the chip 2, it is not always necessary to increase the number of bumps in proportion. However, when mounting the chip 2 on the wiring board, the bump is deformed, and the bump cross section becomes larger in the adjacent direction of the bump, which may cause a short circuit by contacting with the adjacent bump. The distance between them, that is, the pitch between the bumps, needs to be constant. Now, assuming that the cross-sectional diameter of the bump is 20 μm, the pitch between the bumps in the surface of the chip 2 is 40 μm or more, the largest circumferential diameter is 9900 μm, and the smallest circumferential diameter is 180 μm. It is desirable that the smallest bump diameter is 20 μm and the largest number of bumps is 55 times or less than the smallest number of bumps.

次に、図３（ａ）は本発明の実施の形態３におけるバンプの配置を有する半導体装置の正面図、図３（ｂ）は図３（ａ）の破線Ｃ−Ｃ’に沿って切断した断面図を示す図である。   Next, FIG. 3A is a front view of the semiconductor device having the bump arrangement in the third embodiment of the present invention, and FIG. 3B is cut along the broken line CC ′ in FIG. It is a figure which shows sectional drawing.

本実施の形態３について、図３（ａ），（ｂ）を参照しながら説明する。図３（ａ），（ｂ）に示すように、半導体素子であるチップ２のパターン形成面上で放射状に配置されたバンプ５ａ，５ｂを有する半導体装置１ｃである。本実施の形態３におけるバンプは配線基板表面の電極に対応していることとする。   The third embodiment will be described with reference to FIGS. 3 (a) and 3 (b). As shown in FIGS. 3A and 3B, the semiconductor device 1c has bumps 5a and 5b arranged radially on the pattern forming surface of the chip 2 which is a semiconductor element. The bumps in the third embodiment correspond to the electrodes on the wiring board surface.

バンプを、バンプの配置される領域に放射状に配置し、その放射線上に配置されたバンプの配置密度は、チップ２中心部の領域に配置されたバンプ５ａより外周部に近づく領域に配置されたバンプ５ｂの方が高くなるように配置する。ただし放射状に配置されたバンプの各直線について、各々の直線でのバンプの数は等しくなくても構わない。   The bumps are arranged radially in the area where the bumps are arranged, and the arrangement density of the bumps arranged on the radiation is arranged in an area closer to the outer periphery than the bumps 5a arranged in the central area of the chip 2. It arrange | positions so that the bump 5b may become higher. However, the number of bumps in each straight line may not be equal for each straight line of bumps arranged radially.

以上のように構成された半導体装置１ｃについて、その原理を説明する。半導体装置１ｃを構成する各部材は、各々異なった熱膨張係数をもっているため、昇温時に熱膨張係数の差による力で応力が発生し、その応力はチップ２の中心部からの距離に大略比例して大きくなる。そこで、本実施の形態３は、バンプの配置密度を応力の変化に応じて変化させることで応力を分散させることができ、接合性の向上を図ることができる。また、本実施の形態３は、バンプを一直線上に配置させるため、バンプが容易に形成できる。   The principle of the semiconductor device 1c configured as described above will be described. Since each member constituting the semiconductor device 1c has a different thermal expansion coefficient, a stress is generated by a force due to the difference in the thermal expansion coefficient when the temperature is raised, and the stress is approximately proportional to the distance from the center portion of the chip 2. And get bigger. Therefore, in the third embodiment, the stress can be dispersed by changing the arrangement density of the bumps according to the change of the stress, and the bondability can be improved. In the third embodiment, since the bumps are arranged on a straight line, the bumps can be easily formed.

次に、図４は本発明の実施の形態４における半導体装置の断面図である。本実施の形態４について、図４を参照しながら説明する。また、図４に示すように、半導体素子１ｄにおけるバンプ８は配線基板７表面の電極６に対応していることとする。   Next, FIG. 4 is a sectional view of the semiconductor device according to the fourth embodiment of the present invention. The fourth embodiment will be described with reference to FIG. Further, as shown in FIG. 4, the bump 8 in the semiconductor element 1 d corresponds to the electrode 6 on the surface of the wiring substrate 7.

半導体素子であるチップ２には、チップ２と配線基板７とのジョイント部分であるバンプ８が円形に配置されて形成されており、配線基板表面の電極６にバンプ８を介してチップ２を接合している。また、配線基板７とチップ２の間には、封止樹脂９が充填されている。この充填される封止樹脂９の領域は、円形に配置されたバンプ８が存在する部分のみに存在している。   On the chip 2 which is a semiconductor element, bumps 8 which are joint portions of the chip 2 and the wiring board 7 are formed in a circular shape, and the chip 2 is bonded to the electrodes 6 on the surface of the wiring board via the bumps 8. is doing. A sealing resin 9 is filled between the wiring substrate 7 and the chip 2. The area | region of this sealing resin 9 with which it fills exists only in the part in which the bump 8 arrange | positioned circularly exists.

以上のように構成された半導体装置１ｄについて、その原理を説明する。半導体装置１ｄを構成する各部材、つまりチップ２，配線基板７，封止樹脂９は、各々異なった熱膨張係数をもっているため、昇温時に熱膨張係数の差による力で応力が発生し、その応力はチップ２の中心部からの距離に大略比例して大きくなる。よって封止樹脂９も応力発生に係わることから、封止樹脂９の充填領域部を円形にすることで、封止樹脂９の応力緩和を得ることができる。なお、封止樹脂９を充填する部分は、バンプ８を配置する領域よりも大きい範囲でも構わない。   The principle of the semiconductor device 1d configured as described above will be described. Since each member constituting the semiconductor device 1d, that is, the chip 2, the wiring board 7, and the sealing resin 9 has different thermal expansion coefficients, stress is generated by the force due to the difference in thermal expansion coefficient when the temperature is raised. The stress increases in proportion to the distance from the center of the chip 2. Therefore, since the sealing resin 9 also relates to the generation of stress, the stress relaxation of the sealing resin 9 can be obtained by making the filling region portion of the sealing resin 9 circular. The portion filled with the sealing resin 9 may be larger than the region where the bumps 8 are arranged.

また、前述の実施の形態１〜３のように、チップ２のバンプを配置した領域に、本実施の形態４の封止樹脂９を充填することで、より接合の信頼性を向上することができる。   In addition, as in the first to third embodiments described above, the bonding reliability can be further improved by filling the region where the bumps of the chip 2 are arranged with the sealing resin 9 of the fourth embodiment. it can.

次に、図５（ａ）は本発明の実施の形態５におけるバンプの配置を有する半導体装置の平面図、図５（ｂ）は図５（ａ）の破線Ａ−Ａ’の断面図、図５（ｃ）は半導体素子であるチップを配線基板に接合する工程を示す断面図、図５（ｄ）は半導体装置の断面図、図５（ｅ）は半導体装置の斜視図である。   Next, FIG. 5A is a plan view of the semiconductor device having the bump arrangement according to the fifth embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the broken line AA ′ in FIG. 5C is a cross-sectional view showing a process of bonding a chip, which is a semiconductor element, to a wiring board, FIG. 5D is a cross-sectional view of the semiconductor device, and FIG. 5E is a perspective view of the semiconductor device.

本実施の形態５における半導体装置の製造方法について、図５（ａ）〜（ｅ）を参照しながら説明する。   A method for manufacturing a semiconductor device according to the fifth embodiment will be described with reference to FIGS.

本実施の形態５における製造方法は、まず、半導体素子であるチップ２のパターン形成面上でバンプ８を円形に形成する（図５（ａ），（ｂ）参照）。一般にバンプ８は金や半田などからできている。しかし、他の金属でも構わない。   In the manufacturing method according to the fifth embodiment, first, bumps 8 are formed in a circle on the pattern formation surface of chip 2 which is a semiconductor element (see FIGS. 5A and 5B). In general, the bumps 8 are made of gold or solder. However, other metals may be used.

次に、図５（ｃ）に示す、バンプ８の付いたチップ２と配線基板７を接合させる工程において、封止樹脂９を用いて、バンプ８の配置された領域のみを接合する。一般に封止樹脂９はエポキシ系のものを用いることが多いが、エポキシ系以外のものでも構わない。また本実施の形態５のバンプ８は配線基板表面の電極６に対応していることとする。   Next, in the step of bonding the chip 2 with the bumps 8 and the wiring board 7 shown in FIG. 5C, only the region where the bumps 8 are arranged is bonded using the sealing resin 9. In general, the sealing resin 9 is often an epoxy resin, but it may be other than the epoxy resin. The bumps 8 of the fifth embodiment correspond to the electrodes 6 on the wiring board surface.

この接合させる工程において、まず、配線基板７上に封止樹脂９を滴下し、上部よりバンプ８の付いたチップ２を降下し、バンプ８と電極６を当接するように配線基板７上に搭載することにより、滴下した封止樹脂９が伸び、円形にバンプ８が配置されている部分に封止樹脂９が広がり、この封止樹脂９を硬化させ接合させる製造方法である。   In this bonding step, first, the sealing resin 9 is dropped on the wiring board 7, the chip 2 with the bumps 8 is lowered from above, and the bumps 8 and the electrodes 6 are mounted on the wiring board 7 so as to contact each other. In this manufacturing method, the dropped sealing resin 9 extends, and the sealing resin 9 spreads to a portion where the bumps 8 are arranged in a circle. The sealing resin 9 is cured and bonded.

ただし、封止樹脂９を硬化させるためには、一般に１５０℃程度で約２時間硬化炉中に置かなければならない。封止樹脂充填部分の高さは、配線基板と半導体素子であるチップ２間の距離とし、封止樹脂９を塗布する体積はバンプ８を配置する領域に対応する配線基板７の円形部分に樹脂充填部の高さを掛けて、その体積から複数のバンプ８の総体積を引いて封止樹脂９の量を決定する。   However, in order to cure the sealing resin 9, it must generally be placed in a curing furnace at about 150 ° C. for about 2 hours. The height of the sealing resin filling portion is the distance between the wiring substrate and the chip 2 which is a semiconductor element, and the volume for applying the sealing resin 9 is resin on the circular portion of the wiring substrate 7 corresponding to the region where the bumps 8 are arranged. The amount of the sealing resin 9 is determined by multiplying the height of the filling portion and subtracting the total volume of the plurality of bumps 8 from the volume.

以上のような製造方法について、その原理を説明する。半導体装置１ｄを構成する各部材、つまりチップ２，配線基板７，封止樹脂９は、各々異なった熱膨張係数をもっているため、昇温時に熱膨張係数の差による力で応力が発生し、その応力はチップ２の中心部からの距離に大略比例して大きくなる。よって封止樹脂９も応力発生に係わることから、封止樹脂９を塗布する領域を円形にすることで、封止樹脂９の応力緩和を得ることができる。   The principle of the manufacturing method as described above will be described. Since each member constituting the semiconductor device 1d, that is, the chip 2, the wiring board 7, and the sealing resin 9 has different thermal expansion coefficients, stress is generated by the force due to the difference in thermal expansion coefficient when the temperature is raised. The stress increases in proportion to the distance from the center of the chip 2. Therefore, since the sealing resin 9 is also involved in the generation of stress, the stress relaxation of the sealing resin 9 can be obtained by making the region to which the sealing resin 9 is applied circular.

なお、封止樹脂９を塗布する部分は、バンプ８を配置する領域よりも大きい範囲でも構わない。また、本実施の形態５の製造方法は、チップ２と配線基板７との接合および封止樹脂の注入を同時に行うことができるので、製造時間の短縮に有効である。   The portion where the sealing resin 9 is applied may be larger than the region where the bumps 8 are arranged. In addition, the manufacturing method of the fifth embodiment is effective in shortening the manufacturing time because the chip 2 and the wiring substrate 7 can be joined and the sealing resin can be injected simultaneously.

本発明に係る半導体装置およびその製造方法は、応力に大略比例したバンプの配置密度を有して、熱膨張係数の差による応力集中を緩和し、接合不良の発生を防ぐことができ、半導体装置において、半導体素子であるチップに設けた、チップと配線基板とのジョイント部分であるバンプの配置構造に係り、半導体装置の各部材の熱膨張係数の差により発生するチップ外周部での応力集中の防止に有用である。   The semiconductor device and the manufacturing method thereof according to the present invention have a bump arrangement density substantially proportional to stress, can relieve stress concentration due to a difference in thermal expansion coefficient, and can prevent occurrence of bonding failure. In this case, the stress concentration at the outer periphery of the chip is caused by the difference in the thermal expansion coefficient of each member of the semiconductor device in relation to the arrangement structure of the bump which is the joint portion between the chip and the wiring board provided on the chip as the semiconductor element. Useful for prevention.

（ａ）は本発明の実施の形態１におけるバンプの配置を有する半導体装置の正面図、（ｂ）は（ａ）の破線Ａ−Ａ’に沿って切断した断面図を示す図(A) is a front view of the semiconductor device having the bump arrangement according to the first embodiment of the present invention, and (b) is a cross-sectional view taken along the broken line A-A ′ of (a). （ａ）は本発明の実施の形態２におけるバンプの配置を有する半導体装置の正面図、（ｂ）は（ａ）の破線Ｂ−Ｂ’に沿って切断した断面図を示す図(A) is a front view of the semiconductor device which has arrangement | positioning of the bump in Embodiment 2 of this invention, (b) is a figure which shows sectional drawing cut | disconnected along the broken line B-B 'of (a) （ａ）は本発明の実施の形態３におけるバンプの配置を有する半導体装置の正面図、（ｂ）は（ａ）の破線Ｃ−Ｃ’に沿って切断した断面図を示す図(A) is a front view of a semiconductor device having a bump arrangement in the third embodiment of the present invention, and (b) is a cross-sectional view taken along a broken line C-C 'in (a). 本発明の実施の形態４における半導体装置の断面図Sectional drawing of the semiconductor device in Embodiment 4 of this invention （ａ）は本発明の実施の形態５におけるバンプの配置を有する半導体装置の平面図、（ｂ）は（ａ）の破線Ａ−Ａ’の断面図、（ｃ）は半導体素子であるチップを配線基板に接合する工程を示す断面図、（ｄ）は半導体装置の断面図、（ｅ）は半導体装置の斜視図(A) is a top view of the semiconductor device which has arrangement | positioning of the bump in Embodiment 5 of this invention, (b) is sectional drawing of broken line AA 'of (a), (c) is a chip | tip which is a semiconductor element. Sectional drawing which shows the process joined to a wiring board, (d) is sectional drawing of a semiconductor device, (e) is a perspective view of a semiconductor device （ａ）は、従来のチップを配線基板上に実装してなる半導体装置の斜視図、（ｂ）は、（ａ）の破線Ｅ−Ｅ’に沿って切断した断面図、（ｃ）は、バンプが形成されたチップの平面図(A) is a perspective view of a semiconductor device in which a conventional chip is mounted on a wiring board, (b) is a cross-sectional view taken along the broken line EE ′ of (a), and (c) is Plan view of chip with bumps formed

符号の説明Explanation of symbols

１ａ，１ｂ，１ｃ，１ｄ，１６ 半導体装置
２，１０ チップ
３ａ，３ｂ，３ｃ，４ａ，４ｂ，４ｃ，５ａ，５ｂ，８，１３ バンプ
６，１５ 電極
７，１１ 配線基板
９，１４ 封止樹脂
１２ 補給バンプ 1a, 1b, 1c, 1d, 16 Semiconductor device 2, 10 Chip 3a, 3b, 3c, 4a, 4b, 4c, 5a, 5b, 8, 13 Bump 6, 15 Electrode 7, 11 Wiring substrate 9, 14 Sealing resin 12 Supply bump

Claims (9)

半導体素子であるチップと、前記チップを搭載する配線基板と、前記チップと前記配線基板のジョイント部分として前記チップに配置し接合したバンプとを有し、
前記バンプを配置した領域において、前記チップの中心からの距離の大きい位置に配置した前記バンプが、前記チップの中心からの距離の小さい位置に配置した前記バンプよりも前記バンプの断面積が大きいことを特徴とする半導体装置。 A chip that is a semiconductor element, a wiring board on which the chip is mounted, and a bump that is arranged and bonded to the chip as a joint part of the chip and the wiring board,
In the region where the bumps are arranged, the bump arranged at a position with a large distance from the center of the chip has a larger sectional area of the bump than the bump arranged at a position with a small distance from the center of the chip. A semiconductor device characterized by the above. 前記バンプを配置した領域において、前記バンプを径の異なる同心円の円周上に配置して、前記同心円の大きな径の円周上に配置した前記バンプが、前記同心円の小さな径の円周上に配置した前記バンプよりも前記バンプの断面積が大きいことを特徴とする請求項１記載の半導体装置。   In the region where the bumps are arranged, the bumps are arranged on the circumference of a concentric circle having a different diameter, and the bumps arranged on the circumference of the concentric circle having a large diameter are arranged on the circumference of the concentric circle having a small diameter. The semiconductor device according to claim 1, wherein a cross-sectional area of the bump is larger than the arranged bump. 前記バンプの最も大きな断面積が、前記バンプの最も小さな断面積の６倍以下であることを特徴とする請求項１または２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the largest cross-sectional area of the bump is not more than six times the smallest cross-sectional area of the bump. 半導体素子であるチップと、前記チップを搭載する配線基板と、前記チップと前記配線基板のジョイント部分として前記チップに配置し接合したバンプとを有し、
前記バンプを配置した領域において、前記バンプを径の異なる同心円の円周上に配置して、前記同心円の小さな径の円周上に配置した前記バンプより、前記同心円の大きな径の円周上に配置した前記バンプの数を多くして前記バンプの配置密度を高くしたことを特徴とする半導体装置。 A chip that is a semiconductor element, a wiring board on which the chip is mounted, and a bump that is arranged and bonded to the chip as a joint part of the chip and the wiring board,
In the region where the bumps are arranged, the bumps are arranged on the circumference of a concentric circle having a different diameter, and the bumps arranged on the circumference of the concentric circle having a small diameter are arranged on the circumference of the concentric circle having a large diameter. A semiconductor device characterized in that the number of the arranged bumps is increased to increase the arrangement density of the bumps. 円周上に配置した前記バンプの最も多い数が、前記バンプの最も少ない数の５５倍以下であることを特徴とする請求項４記載の半導体装置。   5. The semiconductor device according to claim 4, wherein the largest number of the bumps arranged on the circumference is 55 times or less the smallest number of the bumps. 半導体素子であるチップと、前記チップを搭載する配線基板と、前記チップと前記配線基板のジョイント部分として前記チップに配置し接合したバンプとを有し、
前記バンプを配置した領域において、前記バンプを前記チップの中心から放射状に配置して、前記チップの中心から外周に向かうにつれて、配置する前記バンプの間隔を狭くして前記バンプの配置密度を高くしたことを特徴とする半導体装置。 A chip which is a semiconductor element; a wiring board on which the chip is mounted; and a bump which is arranged and bonded to the chip as a joint part of the chip and the wiring board,
In the area where the bumps are arranged, the bumps are arranged radially from the center of the chip, and as the distance from the center of the chip toward the outer periphery, the interval between the arranged bumps is reduced to increase the arrangement density of the bumps. A semiconductor device. 前記配線基板と前記チップの間に充填する封止樹脂を有し、前記封止樹脂を、前記配線基板表面の電極と接合する前記バンプを配置した領域にのみ塗布することを特徴とする請求項１〜６のいずれか１項に記載の半導体装置。   The sealing resin filling between the wiring substrate and the chip, and the sealing resin is applied only to a region where the bumps to be bonded to the electrodes on the surface of the wiring substrate are disposed. The semiconductor device according to any one of 1 to 6. 半導体素子であるチップと、前記チップを搭載する配線基板と、前記チップと前記配線基板のジョイント部分として前記チップの円形の領域に配置し接合したバンプと、前記配線基板と前記チップの間に充填する封止樹脂とを有し、
前記封止樹脂を、前記配線基板表面の電極と接合する前記バンプを配置した領域にのみ塗布することを特徴とする半導体装置。 A chip which is a semiconductor element; a wiring board on which the chip is mounted; a bump which is arranged and joined in a circular area of the chip as a joint portion between the chip and the wiring board; and a space between the wiring board and the chip Sealing resin to be
The semiconductor device, wherein the sealing resin is applied only to a region where the bumps to be bonded to the electrodes on the surface of the wiring board are disposed. 半導体素子であるチップ上に前記チップと配線基板のジョイント部分としてバンプを円形の領域に配置して接合する工程と、前記配線基板に封止樹脂を塗布する工程と、前記封止樹脂が塗布された前記配線基板上に前記バンプを配置した前記チップを搭載する工程と、前記チップと前記配線基板間に充填した前記封止樹脂を硬化させる工程とからなる半導体装置の製造方法であって、
前記封止樹脂の充填部分は、前記バンプを配置した領域であり、前記封止樹脂の充填部分の高さを、前記配線基板と前記チップ間の距離として、前記バンプを配置した領域に前記充填部分の高さを掛けて求めた前記封止樹脂の充填部分の体積から、前記バンプの総体積を引いて前記封止樹脂の塗布量を決定することを特徴とする半導体装置の製造方法。 A step of placing bumps in a circular area as a joint portion between the chip and the wiring substrate on a chip that is a semiconductor element and bonding, a step of applying a sealing resin to the wiring substrate, and the sealing resin being applied A method of manufacturing a semiconductor device comprising a step of mounting the chip on which the bumps are arranged on the wiring substrate, and a step of curing the sealing resin filled between the chip and the wiring substrate,
The filling portion of the sealing resin is a region where the bumps are arranged, and the filling region is filled with the height of the filling portion of the sealing resin as a distance between the wiring board and the chip. A method for manufacturing a semiconductor device, comprising: subtracting the total volume of the bumps from the volume of the filled portion of the sealing resin obtained by multiplying the height of the portion to determine the coating amount of the sealing resin.
JP2005331407A 2005-11-16 2005-11-16 Semiconductor device and manufacturing method therefor Pending JP2007142017A (en)

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