JP2007173724A - Circuit module - Google Patents

Circuit module Download PDF

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Publication number
JP2007173724A
JP2007173724A JP2005372600A JP2005372600A JP2007173724A JP 2007173724 A JP2007173724 A JP 2007173724A JP 2005372600 A JP2005372600 A JP 2005372600A JP 2005372600 A JP2005372600 A JP 2005372600A JP 2007173724 A JP2007173724 A JP 2007173724A
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JP
Japan
Prior art keywords
circuit module
circuit board
underfill
main body
land
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Withdrawn
Application number
JP2005372600A
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Japanese (ja)
Inventor
Tomoyuki Honma
友幸 本間
Kazuo Chihiro
和夫 千尋
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Publication date
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Priority to JP2005372600A priority Critical patent/JP2007173724A/en
Priority to TW095146285A priority patent/TW200733321A/en
Priority to CN 200610165987 priority patent/CN100521170C/en
Publication of JP2007173724A publication Critical patent/JP2007173724A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit module without any voids (bubbles) in underfill. <P>SOLUTION: In the circuit module, the underfill 11 rapidly flows into an area between a lower surface center and a circuit board 1 due to the presence of a projection T for reducing a gap provided between the lower surface center of a body 8 in which no bumps 10 are formed, and the circuit board 1 opposing the lower surface center section, thus eliminating voids (bubbles) and preventing the underfill 11 from being peeled. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、種々の電子回路ユニット等に使用して好適な回路モジュールに関するものである。   The present invention relates to a circuit module suitable for use in various electronic circuit units and the like.

従来の回路モジュールに係る図面を説明すると、図８は従来の回路モジュールに係る要部断面図、図９は従来の回路モジュールに係る回路基板の平面図、図１０は従来の回路モジュールに係る半導体部品の下面図、図１１は従来の回路モジュールに係り、アンダーフィルの注入過程を示す説明図、図１２は従来の回路モジュールに係り、アンダーフィルの注入後の状態を示す説明図である。   FIG. 8 is a cross-sectional view of a main part of a conventional circuit module, FIG. 9 is a plan view of a circuit board of the conventional circuit module, and FIG. 10 is a semiconductor of the conventional circuit module. FIG. 11 is an explanatory view showing an underfill injection process related to the conventional circuit module, and FIG. 12 is an explanatory view showing a state after the underfill injection related to the conventional circuit module.

次に、従来の回路モジュールに係る構成を図８〜図１０に基づいて説明すると、回路基板５１には、特に図９に示すように、３列状態で環状に高密度に配置された複数のランド部５２を有し、このランド部５２の中央部に位置する回路基板５１には、余白部５１ａが設けられている。   Next, the configuration of the conventional circuit module will be described with reference to FIGS. 8 to 10. In particular, the circuit board 51 includes a plurality of circularly arranged high density elements in three rows as shown in FIG. 9. A circuit board 51 having a land portion 52 and located at the center of the land portion 52 is provided with a blank portion 51a.

半導体部品５３は、特に図１０に示すように、本体部５４と、ランド部５２に対応して本体部５４の下面に設けられた複数の電極５５と、この電極５５に設けられたバンプ５６を有し、この電極５５の中央部に位置する本体部５４には、余白部５４ａが設けられている。   As shown in FIG. 10 in particular, the semiconductor component 53 includes a main body portion 54, a plurality of electrodes 55 provided on the lower surface of the main body portion 54 corresponding to the land portions 52, and bumps 56 provided on the electrodes 55. The main body 54 located at the center of the electrode 55 is provided with a blank portion 54a.

そして、この半導体部品５３は、回路基板５１上に配置され、電極５５がバンプ５６によってランド部５２に接続、取付が行われると共に、半導体部品５３の本体部５４と回路基板５１との間には、樹脂からなるアンダーフィル５７がディスペンサ５８によって設けられた構成となっている（例えば、特許文献１参照）。   The semiconductor component 53 is disposed on the circuit board 51, and the electrodes 55 are connected to and attached to the land portions 52 by the bumps 56, and between the main body portion 54 of the semiconductor component 53 and the circuit board 51. The underfill 57 made of resin is provided by a dispenser 58 (see, for example, Patent Document 1).

また、従来の回路モジュールに係るアンダーフィル５７の形成方法を図１１，図１２に基づいて説明すると、先ず、回路基板５１には、バンプ５６によって半導体部品５３を取付、しかる後、図１１に示すように、半導体部品５３の近傍にディスペンサ５８を配置して、ディスペンサ５８によって、液状のアンダーフィル５７を回路基板５１と本体部５４との間の隙間に注入する。   Further, a method of forming the underfill 57 according to the conventional circuit module will be described with reference to FIGS. 11 and 12. First, the semiconductor component 53 is attached to the circuit board 51 by the bumps 56, and then, as shown in FIG. As described above, the dispenser 58 is disposed in the vicinity of the semiconductor component 53, and the liquid underfill 57 is injected into the gap between the circuit board 51 and the main body 54 by the dispenser 58.

すると、図１１に示すように、液状のアンダーフィル５７は、先ず、ディスペンサ５８に近い位置から順次、高密度に配置されたバンプ５６間に毛細管現象によって流れ込み、そして、図１２に示すように、バンプ５６の全体がアンダーフィル５７によって覆われた状態となる。   Then, as shown in FIG. 11, the liquid underfill 57 first flows into the bumps 56 arranged at high density sequentially from the position close to the dispenser 58 by capillary action, and as shown in FIG. The entire bump 56 is covered with the underfill 57.

この時、液状のアンダーフィル５７は、高密度に配置されたバンプ５６間に早く流れるため、半導体部品５３の本体部５４の中央部に位置する余白部５４ａと、この余白部５４ａに対向する回路基板５１の余白部５１ａとの間には、ボイド（気泡）５９が発生した状態になると共に、このアンダーフィル５７を硬化すると、アンダーフィル５７の形成が完了する。
特開２００２−２７１０１４号公報 At this time, since the liquid underfill 57 flows quickly between the bumps 56 arranged at a high density, a blank portion 54a located at the center of the main body portion 54 of the semiconductor component 53 and a circuit facing the blank portion 54a. A void (bubble) 59 is generated between the blank portion 51a of the substrate 51, and when the underfill 57 is cured, the formation of the underfill 57 is completed.
JP 2002-271014 A

しかし、従来の回路モジュールにあっては、半導体部品５３の本体部５４の中央部に位置する余白部５４ａと、この余白部５４ａに対向する回路基板５１の余白部５１ａとの間にボイド（気泡）５９が発生し、外気温が高くなると、ボイド（気泡）５９が膨張して、アンダーフィル５７が剥がれるという問題がある。   However, in the conventional circuit module, there is a void (bubble) between the blank portion 54a located at the center of the main body portion 54 of the semiconductor component 53 and the blank portion 51a of the circuit board 51 facing the blank portion 54a. ) 59 occurs and the outside air temperature becomes high, the void (bubble) 59 expands and the underfill 57 is peeled off.

本発明は、このような従来技術の実情に鑑みてなされたもので、その目的は、アンダーフィルにボイド（気泡）の無い回路モジュールを提供することにある。   The present invention has been made in view of such a state of the prior art, and an object thereof is to provide a circuit module having no void (bubble) in the underfill.

上記の目的を達成するために、本発明は、本体部の下面周辺に複数の電極が形成された半導体部品と、電極に対応する複数のランド部が設けられた回路基板と、電極とランド部とを接続するバンプと、このバンプを覆った状態で、回路基板と本体部の間に設けられた樹脂からなるアンダーフィルとを備え、バンプが形成されていない本体部の下面中央部と、この下面中央部と対向する回路基板との間には、下面中央部と回路基板との間の隙間を小さくするための凸部が設けられたことを特徴としている。   In order to achieve the above object, the present invention provides a semiconductor component having a plurality of electrodes formed around the lower surface of a main body, a circuit board having a plurality of lands corresponding to the electrodes, and an electrode and a land. And an underfill made of resin provided between the circuit board and the main body in a state of covering the bump, and a central portion of the lower surface of the main body where no bump is formed, A convex portion for reducing a gap between the lower surface center portion and the circuit board is provided between the lower surface center portion and the circuit substrate facing the lower surface center portion.

このように構成した本発明は、バンプが形成されていない本体部の下面中央部と、この下面中央部と対向する回路基板との間に設けられた隙間を小さくするための凸部の存在によって、アンダーフィルが下面中央部と回路基板との間に早く流入して、ボイド（気泡）を無くすることができ、アンダーフィルの剥がれの無いものが得られる。   The present invention configured as described above is based on the presence of the convex portion for reducing the gap provided between the lower surface center portion of the main body portion where the bumps are not formed and the circuit substrate facing the lower surface center portion. The underfill flows quickly between the center portion of the lower surface and the circuit board, and voids (bubbles) can be eliminated, so that the underfill does not peel off.

また、本発明は、上記発明において、凸部は、回路基板と本体部の何れか一方、或いは双方に設けられたことを特徴としている。このように構成した本発明は、凸部の形成が回路基板と本体部とに適宜に選択できて、凸部の形成が好適である。   Further, the present invention is characterized in that, in the above-mentioned invention, the convex portion is provided on one or both of the circuit board and the main body portion. In the present invention configured as described above, the formation of the convex portion can be appropriately selected for the circuit board and the main body portion, and the convex portion is preferably formed.

また、本発明は、上記発明において、回路基板には、ランド部を露出した状態で形成されたレジスト膜と、下面中央部に対向する位置に設けられた層状部を有し、凸部がレジスト膜と層状部との重ね合わせによって形成されたことを特徴としている。   Further, according to the present invention, in the above invention, the circuit board has a resist film formed with the land portion exposed, and a layered portion provided at a position facing the center portion of the lower surface, and the convex portion is a resist. It is characterized by being formed by superimposing a film and a layered portion.

このように構成した本発明は、レジスト膜と層状部が回路基板に設けられているため、回路基板の製造時に凸部が同時に形成できて、生産性の良好なものが得られる。   In the present invention configured as described above, since the resist film and the layered portion are provided on the circuit board, the convex portions can be formed at the same time when the circuit board is manufactured, and a product with good productivity can be obtained.

また、本発明は、上記発明において、層状部が導電材からなるダミーランド部、或いは絶縁材からなる絶縁層によって形成されたことを特徴としている。このように構成した本発明は、ダミーランド部がランド部の形成時に、また、絶縁層がレジスト膜と同材料で形成できて、生産性が良く、安価なものが得られる。   The present invention is characterized in that, in the above invention, the layered portion is formed by a dummy land portion made of a conductive material or an insulating layer made of an insulating material. In the present invention configured as described above, the dummy land portion can be formed when the land portion is formed, and the insulating layer can be formed of the same material as that of the resist film.

また、本発明は、上記発明において、層状部は、複数の島状部によって形成されたことを特徴としている。このように構成した本発明は、島状部が中央部の空き状態によって任意の形状を選定できて、自由度のあるものが得られる。   Moreover, the present invention is characterized in that, in the above invention, the layered portion is formed by a plurality of island-shaped portions. In the present invention configured as described above, an arbitrary shape can be selected depending on the free state of the central portion of the island-shaped portion, and a flexible one can be obtained.

また、本発明は、上記発明において、ランド部には、下面中央部側に延びるパターンを有し、このパターン上には、レジスト膜が設けられ、パターンとレジスト膜とからなる厚みが凸部の厚みと同等に形成されたことを特徴としている。   Further, according to the present invention, in the above invention, the land portion has a pattern extending toward the lower surface central portion side, a resist film is provided on the pattern, and the thickness of the pattern and the resist film is a convex portion. It is characterized by being formed with the same thickness.

このように構成した本発明は、パターンが下面中央部側に延設されることによって、小型化ができると共に、ランド部近傍がパターンによってアンダーフィルによる固着を確実にできる。   In the present invention configured as described above, the pattern can be reduced in size by extending toward the center portion of the lower surface, and the vicinity of the land portion can be reliably fixed by the underfill by the pattern.

本発明は、本体部の下面中央部と回路基板との間に設けられた隙間を小さくするための凸部の存在によって、アンダーフィルが下面中央部と回路基板との間に早く流入して、ボイド（気泡）を無くすることができ、アンダーフィルの剥がれの無いものが得られる。   In the present invention, due to the presence of the convex portion for reducing the gap provided between the lower surface central portion of the main body portion and the circuit board, the underfill quickly flows between the lower surface central portion and the circuit board, Voids (bubbles) can be eliminated, and a product without underfill peeling can be obtained.

発明の実施の形態について図面を参照して説明すると、図１は本発明の回路モジュールの第１実施例に係る要部断面図、図２は本発明の回路モジュールの第１実施例に係る回路基板の平面図、図３は本発明の回路モジュールの第１実施例に係り、アンダーフィルの注入過程を示す説明図、図４は本発明の回路モジュールの第１実施例に係り、アンダーフィルの注入後の状態を示す説明図である。   BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of an essential part of a circuit module according to a first embodiment of the present invention, and FIG. 2 is a circuit according to the first embodiment of the circuit module of the present invention; FIG. 3 is a plan view of a substrate, FIG. 3 relates to a first embodiment of the circuit module of the present invention, and is an explanatory view showing an underfill injection process, and FIG. 4 relates to the first embodiment of the circuit module of the present invention. It is explanatory drawing which shows the state after injection | pouring.

また、図５は本発明の回路モジュールの第２実施例に係る要部断面図、図６は本発明の回路モジュールの第２実施例に係る回路基板の平面図、図７は本発明の回路モジュールの第３実施例に係る回路基板の平面図である。   5 is a cross-sectional view of the main part of a circuit module according to a second embodiment of the present invention, FIG. 6 is a plan view of a circuit board according to the second embodiment of the circuit module of the present invention, and FIG. 7 is a circuit of the present invention. It is a top view of the circuit board concerning the 3rd example of a module.

次に、本発明の回路モジュールの第１実施例に係る構成を図１，図２に基づいて説明すると、回路基板１は、低温焼成セラミック（ＬＴＣＣ）等の多層基板からなり、表面に、一列状態で環状に配置された複数のランド部２と、積層内に設けられた配線パターン３と、ランド部２と配線パターン３間を接続するビア導体４を有する。   Next, the configuration according to the first embodiment of the circuit module of the present invention will be described with reference to FIG. 1 and FIG. 2. A plurality of land portions 2 arranged in a ring shape in a state, a wiring pattern 3 provided in the stack, and a via conductor 4 connecting between the land portion 2 and the wiring pattern 3 are provided.

この回路基板１は、ランド部２の中央部に余白部１ａが設けられ、この余白部１ａには、複数の島状部からなる層状部５が設けられている。この層状部５は、この実施例では電気的に接続されていない導電材からなるダミーランド部で形成されている。   The circuit board 1 is provided with a blank portion 1a at the center portion of the land portion 2, and the blank portion 1a is provided with a layered portion 5 including a plurality of island-shaped portions. The layered portion 5 is formed of a dummy land portion made of a conductive material that is not electrically connected in this embodiment.

また、回路基板１の表面には、ランド部２を露出した状態でレジスト膜６が設けられ、このレジスト膜６は、層状部５上を含む回路基板１の表面に設けられて、余白部１ａには、互いに重ね合わされた層状部５とレジスト膜６とによって凸部Ｔが形成されている。   Further, a resist film 6 is provided on the surface of the circuit board 1 with the land portion 2 exposed, and the resist film 6 is provided on the surface of the circuit board 1 including on the layered portion 5 to form a blank portion 1a. A convex portion T is formed by the layered portion 5 and the resist film 6 that are superposed on each other.

なお、この凸部Ｔは、層状部５のダミーランド部に代えて、レジスト等の絶縁材からなる絶縁層を使用しても良く、また、凸部Ｔは、種々の形態が適用できること勿論である。   In addition, this convex part T may replace with the dummy land part of the layered part 5, and may use the insulating layer which consists of insulating materials, such as a resist, Of course, various forms can apply the convex part T. is there.

半導体部品７は、ベアチップ等からなり、本体部８と、ランド部２に対応して本体部８の下面に設けられた複数の電極９と、この電極９に設けられたバンプ１０を有し、この電極９の中央部に位置する本体部８の下面中央部には、余白部８ａが設けられている。   The semiconductor component 7 is made of a bare chip or the like, and includes a main body 8, a plurality of electrodes 9 provided on the lower surface of the main body 8 corresponding to the land 2, and bumps 10 provided on the electrodes 9. A blank portion 8 a is provided at the center of the lower surface of the main body 8 located at the center of the electrode 9.

この半導体部品７は、回路基板１上に配置され、電極９がバンプ１０によってランド部２に接続、取付が行われると共に、半導体部品７の本体部８と回路基板１との間には、樹脂からなるアンダーフィル１１が設けられ、このアンダーフィル１１によって、バンプ１０を覆った状態で、本体部８と回路基板１が固着されている。   The semiconductor component 7 is disposed on the circuit board 1, the electrodes 9 are connected to and attached to the land portion 2 by the bumps 10, and a resin is interposed between the main body portion 8 of the semiconductor component 7 and the circuit board 1. The underfill 11 is provided, and the main body 8 and the circuit board 1 are fixed to each other with the bump 10 covered by the underfill 11.

なお、ここでは図示しないが、回路基板１上には、種々の電子部品が搭載されて、所望の電気回路が形成された状態となっている。   Although not shown here, various electronic components are mounted on the circuit board 1 to form a desired electric circuit.

また、半導体部品７が回路基板１に取り付けられた際、本体部８の余白部８ａと回路基板１の余白部１ａが互いに対向した状態になると共に、この余白部１ａ、８ａ間の隙間は、凸部Ｔによって小さくなっており、これによって、アンダーフィル１１が毛細管現象によって早く流入するようになっている。   Further, when the semiconductor component 7 is attached to the circuit board 1, the blank part 8a of the main body 8 and the blank part 1a of the circuit board 1 are in a state of facing each other, and the gap between the blank parts 1a and 8a is It becomes small by the convex part T, and, thereby, the underfill 11 flows in early by capillary action.

次に、本発明の回路モジュールに係るアンダーフィル１１の形成方法を図３，図４に基づいて説明すると、先ず、回路基板１には、バンプ１０によって半導体部品７を取付、しかる後、図３に示すように、半導体部品７の近傍にディスペンサ１２を配置して、ディスペンサ１２によって、液状のアンダーフィル１１を回路基板１と本体部８との間の隙間に注入する。   Next, a method of forming the underfill 11 according to the circuit module of the present invention will be described with reference to FIGS. 3 and 4. First, the semiconductor component 7 is attached to the circuit board 1 by the bumps 10, and then FIG. 2, a dispenser 12 is arranged in the vicinity of the semiconductor component 7, and the liquid underfill 11 is injected into the gap between the circuit board 1 and the main body 8 by the dispenser 12.

すると、液状のアンダーフィル１１は、先ず、ディスペンサ１２に近い位置から順次、バンプ１０間、及び凸部Ｔと本体部８との間に毛細管現象によって流れ込み、図３に示すように、アンダーフィル１１は、バンプ１０間と凸部Ｔの箇所でほぼ均等に流入するようになる。   Then, the liquid underfill 11 first flows in order from the position close to the dispenser 12 between the bumps 10 and between the convex portion T and the main body portion 8 by capillary action, and as shown in FIG. Flows almost evenly between the bumps 10 and at the locations of the convex portions T.

そして、アンダーフィル１１の注入を続けると、図４に示すように、本体部８と回路基板１との間の隙間全体にアンダーフィル１１が流入して、バンプ１０が覆われると共に、ボイド（気泡）の無いアンダーフィル１１の形成ができ、また、アンダーフィル１１の流入後、液状のアンダーフィル１１を加熱等によって硬化すると、アンダーフィル１１の形成が完了する。   Then, when the underfill 11 is continuously injected, as shown in FIG. 4, the underfill 11 flows into the entire gap between the main body 8 and the circuit board 1 to cover the bumps 10, and voids (bubbles) The underfill 11 can be formed, and after the underfill 11 flows, the underfill 11 is completed when the liquid underfill 11 is cured by heating or the like.

また、図５，図６は本発明の回路モジュールの第２実施例を示し、この第２実施例について説明すると、ランド部２には、回路基板１の余白部１ａ側（本体部８の下面中央部）に延びるパターン２ａを有し、このパターン２ａの端部の位置で、ランド部２がビア導体４によって配線パターン３に接続されている。   5 and 6 show a second embodiment of the circuit module according to the present invention. The second embodiment will be described. The land portion 2 has a blank portion 1a side of the circuit board 1 (the lower surface of the main body portion 8). It has a pattern 2 a extending in the center), and the land portion 2 is connected to the wiring pattern 3 by a via conductor 4 at the position of the end of the pattern 2 a.

そして、このパターン２ａ上には、レジスト膜６が設けられ、このレジスト膜６とパターン２ａとからなる厚みが凸部Ｔの厚みと同等に形成されており、その他の構成は、上記第１実施例と同様の構成を有し、同一部品に同一番号を付し、ここではその説明を省略する。   A resist film 6 is provided on the pattern 2a, and the thickness of the resist film 6 and the pattern 2a is formed to be equal to the thickness of the convex portion T. Other configurations are the same as those in the first embodiment. It has the same configuration as the example, the same parts are assigned the same numbers, and the description thereof is omitted here.

また、図７は本発明の回路モジュールの第３実施例を示し、この第３実施例について説明すると、ランド部２は、２列状態で環状に配置され、内側に位置するランド部２には、回路基板１の余白部１ａ側（本体部８の下面中央部）にパターン２ａを有し、この内側のパターン２ａの端部の位置で、ランド部２がビア導体４によって配線パターン３に接続されている。   FIG. 7 shows a third embodiment of the circuit module according to the present invention. The third embodiment will be described. The land portions 2 are arranged in an annular shape in two rows, The circuit board 1 has a pattern 2a on the blank portion 1a side (lower surface center portion of the main body portion 8), and the land portion 2 is connected to the wiring pattern 3 by the via conductor 4 at the position of the end portion of the inner pattern 2a. Has been.

外側に位置するランド部２には、半導体部品７よりも外側に延びるパターン２ｂを有し、この外側のパターン２ｂの端部の位置で、ランド部２がビア導体４によって配線パターン３に接続されている。   The land portion 2 located outside has a pattern 2 b extending outward from the semiconductor component 7, and the land portion 2 is connected to the wiring pattern 3 by the via conductor 4 at the position of the end portion of the outside pattern 2 b. ing.

そして、内側と外側のランド部２には、半導体部品７がバンプ１０によって接続されており、その他の構成は、上記第２実施例と同様の構成を有し、同一部品に同一番号を付し、ここではその説明を省略する。   The semiconductor parts 7 are connected to the inner and outer lands 2 by bumps 10, and the other parts are the same as those in the second embodiment, and the same parts are given the same numbers. The description is omitted here.

なお、上記実施例の凸部Ｔは、回路基板１側に設けたもので説明したが、半導体部品７の本体部８に設けても良く、また、凸部Ｔは、回路基板１と半導体部品７の双方に設けても良い。   The convex portion T in the above embodiment has been described as being provided on the circuit board 1 side. However, the convex portion T may be provided on the main body portion 8 of the semiconductor component 7, and the convex portion T may be provided on the circuit board 1 and the semiconductor component. 7 may be provided on both sides.

本発明の回路モジュールの第１実施例に係る要部断面図である。It is principal part sectional drawing which concerns on 1st Example of the circuit module of this invention. 本発明の回路モジュールの第１実施例に係る回路基板の平面図である。It is a top view of the circuit board which concerns on 1st Example of the circuit module of this invention. 本発明の回路モジュールの第１実施例に係り、アンダーフィルの注入過程を示す説明図である。It is explanatory drawing which concerns on 1st Example of the circuit module of this invention and shows the injection | pouring process of an underfill. 本発明の回路モジュールの第１実施例に係り、アンダーフィルの注入後の状態を示す説明図である。It is explanatory drawing which concerns on 1st Example of the circuit module of this invention and shows the state after injection | pouring of an underfill. 本発明の回路モジュールの第２実施例に係る要部断面図である。It is principal part sectional drawing which concerns on 2nd Example of the circuit module of this invention. 本発明の回路モジュールの第２実施例に係る回路基板の平面図である。It is a top view of the circuit board which concerns on 2nd Example of the circuit module of this invention. 本発明の回路モジュールの第３実施例に係る回路基板の平面図である。It is a top view of the circuit board which concerns on 3rd Example of the circuit module of this invention. 従来の回路モジュールに係る要部断面図である。It is principal part sectional drawing concerning the conventional circuit module. 従来の回路モジュールに係る回路基板の平面図である。It is a top view of the circuit board concerning the conventional circuit module. 従来の回路モジュールに係る半導体部品の下面図である。It is a bottom view of the semiconductor component which concerns on the conventional circuit module. 従来の回路モジュールに係り、アンダーフィルの注入過程を示す説明図である。It is explanatory drawing which shows the injection process of an underfill in connection with the conventional circuit module. 従来の回路モジュールに係り、アンダーフィルの注入後の状態を示す説明図である。It is explanatory drawing which shows the state after injection | pouring of an underfill in connection with the conventional circuit module.

符号の説明Explanation of symbols

１ 回路基板
１ａ 余白部
２ ランド部
２ａ、２ｂ パターン
３ 配線パターン
４ ビア導体
５ 層状部
６ レジスト膜
Ｔ 凸部
７ 半導体部品
８ 本体部
８ａ 余白部
９ 電極
１０ バンプ
１１ アンダーフィル
１２ ディスペンサ DESCRIPTION OF SYMBOLS 1 Circuit board 1a Blank part 2 Land part 2a, 2b Pattern 3 Wiring pattern 4 Via conductor 5 Layered part 6 Resist film T Convex part 7 Semiconductor component 8 Main body part 8a Blank part 9 Electrode 10 Bump 11 Underfill 12 Dispenser

Claims (6)

本体部の下面周辺に複数の電極が形成された半導体部品と、前記電極に対応する複数のランド部が設けられた回路基板と、前記電極と前記ランド部とを接続するバンプと、このバンプを覆った状態で、前記回路基板と前記本体部の間に設けられた樹脂からなるアンダーフィルとを備え、前記バンプが形成されていない前記本体部の下面中央部と、この下面中央部と対向する前記回路基板との間には、前記下面中央部と前記回路基板との間の隙間を小さくするための凸部が設けられたことを特徴とする回路モジュール。 A semiconductor component having a plurality of electrodes formed around the lower surface of the main body, a circuit board having a plurality of lands corresponding to the electrodes, a bump connecting the electrodes and the land, and the bump In a covered state, the resin includes an underfill made of resin provided between the circuit board and the main body, and is opposed to the lower surface central portion of the main body portion where the bumps are not formed and the lower surface central portion. A circuit module, characterized in that a convex portion is provided between the circuit board and a gap between the center portion of the lower surface and the circuit board. 前記凸部は、前記回路基板と前記本体部の何れか一方、或いは双方に設けられたことを特徴とする請求項１記載の回路モジュール。 The circuit module according to claim 1, wherein the convex portion is provided on one or both of the circuit board and the main body. 前記回路基板には、前記ランド部を露出した状態で形成されたレジスト膜と、前記下面中央部に対向する位置に設けられた層状部を有し、前記凸部が前記レジスト膜と前記層状部との重ね合わせによって形成されたことを特徴とする請求項１、又は２記載の回路モジュール。 The circuit board includes a resist film formed in a state where the land portion is exposed, and a layered portion provided at a position facing the lower surface center portion, and the convex portion is the resist film and the layered portion. The circuit module according to claim 1, wherein the circuit module is formed by superimposing with the circuit module. 前記層状部が導電材からなるダミーランド部、或いは絶縁材からなる絶縁層によって形成されたことを特徴とする請求項３記載の回路モジュール。 4. The circuit module according to claim 3, wherein the layered portion is formed by a dummy land portion made of a conductive material or an insulating layer made of an insulating material. 前記層状部は、複数の島状部によって形成されたことを特徴とする請求項４記載の回路モジュール。 The circuit module according to claim 4, wherein the layered portion is formed by a plurality of island-shaped portions. 前記ランド部には、前記下面中央部側に延びるパターンを有し、このパターン上には、前記レジスト膜が設けられ、前記パターンと前記レジスト膜とからなる厚みが前記凸部の厚みと同等に形成されたことを特徴とする請求項３から５の何れか１項に記載の回路モジュール。 The land portion has a pattern extending toward the lower surface central portion, and the resist film is provided on the pattern, and the thickness of the pattern and the resist film is equal to the thickness of the convex portion. The circuit module according to claim 3, wherein the circuit module is formed.
JP2005372600A 2005-12-26 2005-12-26 Circuit module Withdrawn JP2007173724A (en)

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CN 200610165987 CN100521170C (en) 2005-12-26 2006-12-12 Circuit component

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Cited By (2)

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WO2017010228A1 (en) * 2015-07-13 2017-01-19 株式会社村田製作所 Resin substrate, component-mounted resin substrate and manufacturing method therefor
JP2018019032A (en) * 2016-07-29 2018-02-01 豊田合成株式会社 Method for manufacturing light-emitting device

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CN101431030B (en) * 2007-11-07 2010-08-11 联测科技股份有限公司 Method for producing semiconductor device
CN115000036A (en) * 2021-12-08 2022-09-02 荣耀终端有限公司 Chip structure, manufacturing method of chip structure and electronic equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017010228A1 (en) * 2015-07-13 2017-01-19 株式会社村田製作所 Resin substrate, component-mounted resin substrate and manufacturing method therefor
US10568209B2 (en) 2015-07-13 2020-02-18 Murata Manufacturing Co., Ltd. Resin substrate, component-mounted resin substrate, and method of manufacturing component-mounted resin substrate
JP2018019032A (en) * 2016-07-29 2018-02-01 豊田合成株式会社 Method for manufacturing light-emitting device

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