JP2005340864A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which distortion or crack of a package does not occur even if thermal hysteresis is applied by packaging, and of which packaging density during packaging is improved more than that of a conventional structure, and its manufacturing method. <P>SOLUTION: In a semiconductor device 50, a step due to a land 17 provided on the lower surface of a base material 12, is removed by forming a solder resist 22 between the base material 12 and a sheet-like elastomer 26. The semiconductor device is also configured such that the package and the land 17 are shared by arranging a semiconductor element 28 and a semiconductor element 54 in a stack inside the same package, and by electrically connecting to the land 17 through inner leads 18, 58, and 60. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a surface-mount type semiconductor device.

  An example of a conventional semiconductor device having a ball grid array (Ball Grid Array is hereinafter abbreviated as “BGA”) structure using a tape carrier is shown in FIG.

  As shown in FIG. 10A, the semiconductor device 100 includes a plurality of lands 17 (electrodes) that are provided in an array along the four sides on the substrate surface side and on which the solder balls 20 (external connection terminals) are mounted, and The adhesive strength of the patterned copper foil 16 adhered to the base substrate 12 (polyimide film) adhered to the lower surface by the insulating adhesive 14 and the exposed lower surface portion of the insulating adhesive 14 and the land 17. And a semiconductor element 28 bonded to a plurality of electrode pads 30 which are substantially fixed to the lower surface of the elastomer 26 and have inner leads 18 extending from the lands 17 at the periphery of the upper surface. And an insulating resin 32 for protecting the inner lead 18 and the bonding portion.

  Here, the base substrate 12, the insulating adhesive 14, the copper foil 16, the land 17, and the inner lead 18 are collectively referred to as a tape carrier 25.

  However, in the above-described semiconductor device having the BGA structure, when the assembly conditions are poor or the elastomer material is not suitable, the elastomer 26 adhered to the lower surface side of the base substrate 12 is partially around the land 17. As a result, the space 102 surrounded by the lower surface of the insulating adhesive 14, the side surface of the land 17, and the elastomer 26 as shown in FIG. For this reason, there is a problem that moisture or air accumulated in the space 102 expands due to a thermal history or the like when the semiconductor device is mounted on the motherboard, and the package is deformed or cracked.

  Further, in recent years when electronic devices are becoming smaller, there is a demand for further downsizing of semiconductor devices. However, the semiconductor device described above has a configuration in which one semiconductor element is arranged in one package. In other words, in a device using this semiconductor device, for example, when a semiconductor element having a different function is required or a plurality of semiconductor elements are required even if the same type of semiconductor element is used, it is a matter of course. Therefore, it is necessary to secure the space occupied by the packages and connection terminal portions of each semiconductor device. Therefore, it has been desired to improve the mounting density of the semiconductor device by reducing such a space.

  In view of the above facts, the present invention provides a method for manufacturing a semiconductor device that is free from deformation and cracking of a package even when a thermal history is applied by mounting, and further has improved mounting density at the time of mounting compared to the conventional structure. Is an issue.

  The method of manufacturing a semiconductor device according to claim 1 includes a step of forming an electrode portion for providing an external connection terminal exposed from the hole to the surface side on the back surface of the base substrate in which the hole is formed; A step of providing an insulating layer that eliminates the step between the base substrate and the electrode portion on the back surface of the material, and a sheet-like elastic body interposed between the base substrate provided with the insulating layer and the surface of the semiconductor element And disposing the base substrate so as to face the surface of the semiconductor element, and electrically connecting the electrode portion and the electrode pad provided on the surface of the semiconductor element.

  In other words, in the method for manufacturing a semiconductor device according to the first aspect, after the electrode portion is formed on the back surface of the base substrate, the insulating layer that is formed by the electrode portion and eliminates the step between the electrode portion and the back surface of the base substrate is formed. A sheet-like elastic body is interposed between the back surface side of the base substrate smoothed by the insulating layer, that is, between the insulating layer and the semiconductor element.

  For this reason, a gap or the like does not occur in the contact portion of the sheet-like elastic body that is in surface contact with the smoothed insulating layer. Further, even when this elastic body is sticky, a partial peeling force does not occur on the adhesive surface with the insulating layer. As a result, no gap or space due to partial peeling occurs on the contact surface or adhesive surface between the insulating layer and the elastic body. Therefore, even if a thermal history is applied to the semiconductor device manufactured in this way by mounting, the package is not deformed or cracked.

  The method for manufacturing a semiconductor device according to claim 2, wherein in the step of electrically connecting the electrode portion and the electrode pad of the semiconductor element, the insulating layer faces the base substrate on which the electrode portion and the insulating layer are provided. Thus, after the sheet-like elastic body is provided, a base substrate on which the electrode portion, the insulating layer, and the elastic body are provided is arranged with respect to the semiconductor element.

  The semiconductor device manufacturing method according to claim 3 is made of the same material as the base substrate for the insulating layer, and the semiconductor device manufacturing method according to claim 4 uses polyimide as the material. It is.

  According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing method in which an insulating layer is applied by screen printing.

  By such various features, for example, the insulating layer is reliably filled in the gaps on the back surface of the base substrate by being applied. Therefore, no gap remains on the back surface of the base substrate, the gap is reliably filled and the step on the back surface of the base substrate is removed, and a short circuit at the electrode portion through which current flows can be avoided.

  Since the semiconductor device manufacturing method of the present invention has the above-described configuration, there is no deformation or cracking of the package even when a thermal history is applied by mounting, and the mounting density at the time of mounting can be improved from the conventional structure.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a semiconductor device 10 having a BGA structure using a tape carrier according to a first embodiment of the present invention.

  The semiconductor device 10 includes a base substrate 12 (polyimide film) having a plurality of ball mounting holes 12a, and an insulating adhesive 14 is formed on the lower surface of the base substrate 12 in layers. With this insulating adhesive 14, the patterned copper foil 16 and lands 17 (electrode portions) arranged so as to close the lower openings of the ball mounting holes 12 a are attached to the lower surface of the base substrate 12. Has been.

  Further, from each land 17, inner leads 18 whose surfaces are plated with gold extend obliquely downward in a predetermined direction (left and right in the figure, front side and depth direction). Solder balls 20 projecting toward the upper surface side of the base substrate 12 are mounted on the upper surfaces of the lands 17. The solder balls 20 are welded to electrode lands formed on a substrate when the semiconductor device 10 is surface-mounted on a circuit board, a mother board or the like by reflow or the like, thereby mechanically connecting the semiconductor device 10 and the substrate. It serves as a junction and an electrical connection.

  Further, on the lower surface side of the base substrate 12, solder resists 22 (step removal members) are formed on the side surfaces and the lower surfaces of the lands 17 and the lower surface exposed portions of the insulating adhesive 14. The solder resist 22 is obtained by, for example, applying a polyimide resin having insulating properties and heat resistance in a liquid state and applying heat treatment or the like to solidify. Therefore, the side surface and the lower surface of the land 17 and the exposed lower surface portion of the insulating adhesive 14 are covered with the solder resist 22 formed in a substantially film shape, and at the same time, the land 17 is protected.

  As a result, the solder resist 22 enters and adheres to the stepped portion or uneven portion formed by the land 17 without any gap, and the shape thereof is maintained. Here, the base substrate 12, the adhesive layer 14, the copper foil 16, the land 17, the inner lead 18, and the solder resist 22 are collectively referred to as a tape carrier 24.

  Further, the lower surface of the solder resist 22 is a smooth surface, and the semiconductor element 28 is substantially fixed to the lower surface of the tape carrier 24 by an elastic elastomer 26 having an adhesive force attached to the lower surface, so that the lower side of the semiconductor device 10 is located below. Placed on the side.

  A plurality of electrode pads 30 are provided on the peripheral portion on the upper surface side of the semiconductor element 28, and predetermined inner leads 18 corresponding to the electrode pads 30 are bonded to the electrode pads 30. Thereby, the semiconductor element 28 is electrically connected to the substrate through the solder balls 20 as external connection terminals at the time of mounting. A predetermined peripheral portion of the tape carrier 24 is sealed with an insulating resin 32 that protects the inner lead 18 and the bonding portion.

  Thus, in the semiconductor device 10 of this embodiment, the solder resist 22 that eliminates the step between the base substrate 12 and the land 17 is provided between the base substrate 12 and the sheet-like elastomer 26. The step due to the land 17 provided on the lower surface of the base substrate 12 is removed. Further, since the solder resist 22 is a coating agent, the solder resist 22 is surely filled in the gap on the lower surface portion of the base substrate 12, and no gap remains.

  Therefore, a partial peeling force does not occur on the smoothed lower surface portion of the base substrate 12, that is, the adhesive surface of the elastomer 26 bonded to the lower surface of the solder resist 22. Therefore, a space due to partial peeling does not occur on the bonding surface, and the package is not deformed or cracked even if a thermal history is applied by mounting.

  Needless to say, since the solder resist 22 has an insulating property, there is no short circuit in the land 17 through which a current flows.

  Furthermore, in this embodiment, the solder resist 22 is a polyimide resin, and is the same material as the base substrate 12 that is a polyimide film. Therefore, since the coefficients of thermal expansion are approximately equal, they are not easily affected by thermal stress or the like, and the solder resist 22 is not peeled off from the base substrate 12 or a gap is not generated even when a thermal history is applied.

  In addition, various materials can be applied to the solder resist 22 in addition to the polyimide resin. For example, when an epoxy resin is used, it is less expensive than a polyimide resin, and thus there is an advantage that manufacturing costs can be reduced.

  Next, a method for manufacturing the semiconductor device having the above-described configuration will be described with reference to FIGS.

  First, as shown in FIGS. 2 (A) and 2 (B), holes necessary for the mold or etching are opened in the base substrate 12 having the cover tape 34 attached to the lower surface of the insulating adhesive 14. The holes include a ball mounting hole 12a for mounting the solder ball 20, a bonding hole 12b for connecting the inner lead 18 and the electrode pad 30, and a perforation hole 12c used for positioning and transporting the base substrate 12. It is.

  Next, as shown in FIG. 2C, the cover tape 34 is peeled off, and the copper foil 16 is attached to the insulating adhesive 14. Subsequently, a photosensitive resist 36 is applied to the lower surface of the copper foil 16, and a back coat material 38 is applied to the upper surface of the copper foil 16.

  Here, when the photosensitive resist 36 is exposed and developed through a mask on which a circuit pattern is baked, a predetermined portion of the photosensitive resist 36 is dissolved by a developing solution to form a pattern (concave portion) as shown in FIG. Is done. Further, the exposed portion of the copper foil 16 is processed by etching, and when the photosensitive resist 36 and the backcoat material 38 are peeled off, the land 17 and the inner lead 18 are formed as shown in FIG.

  Further, as shown in FIG. 3F, a solder resist 22 (insulating layer) is applied to a part of the land 17 and the inner lead 18. As a method for applying the solder resist 22, for example, screen printing can be used. Thus, the tape carrier 24 is completed.

  A manufacturing process of a BGA structure semiconductor device using the tape carrier 24 and the semiconductor element 28 is shown in FIGS.

  First, as shown in FIG. 4G, a sheet-like elastomer 26 processed into a predetermined shape is attached to the solder resist 22 with heat and load, and then, as shown in FIG. 28 is aligned and joined to the elastomer 26 by heat and load.

  Next, heat, load, and ultrasonic waves are applied to the tool 40 shown in FIG. 4I, and inner bonding is performed at the bonding hole 12b (arrow T direction), and the inner lead 18 is bonded to the electrode pad 30. Further, as shown in FIG. 5 (J), the inner bonding portion is sealed with a resin 32, and as shown in FIG. Are joined. Finally, as shown in FIG. 5L, the product portion is punched from the tape carrier, and the semiconductor device 10 having the BGA structure is completed.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, after the land 17 is formed on the base substrate 12, the solder resist that eliminates the step between the land 17 and the lower surface of the base substrate 12 formed by the land 17. 22 is formed. A sheet-like elastomer 26 is bonded to the lower surface side of the base substrate 12 smoothed by the solder resist 22, that is, to the solder resist 22.

  For this reason, no gap or the like occurs on the adhesive surface of the elastomer 26 that comes into surface contact with the smooth solder resist 22, and no partial peeling force occurs. Therefore, no space is generated due to partial peeling on the bonding surface, and the package is not deformed or cracked even if a thermal history due to mounting is applied to the semiconductor device 10 manufactured in this way.

  Next, a second embodiment of the present invention will be described. In the second embodiment, since the configuration is almost the same as that described in the first embodiment, the same components are denoted by the same reference numerals, and the description of the configuration is omitted. The feature of the second embodiment relates to the arrangement structure of the semiconductor elements.

  FIG. 6 shows a semiconductor device 50 according to the second embodiment of the present invention. In the semiconductor device 50, a semiconductor element 54 whose outer dimension is slightly larger than that of the semiconductor element 28 is fixed to the lower surface of the semiconductor element 28 with an adhesive 52. Similarly to the semiconductor element 28, an electrode pad 56 is provided on the peripheral edge of the upper surface of the semiconductor element 54.

  For the connection between the electrode pad 56 of the semiconductor element 54 and the land 17, the inner lead 58 (one bend in the height direction) directly connecting the land 17 and the electrode pad 56 and the electrode pad 30 from the land 17 are connected. An inner lead 60 (a plurality of bends in the height direction) connected to the electrode pad 56 via the via is used.

  The joining method of these inner leads and the electrode pads 56 is the same as that of the inner leads 18 of the semiconductor element 28 (first embodiment), and is connected by the “single point bonding method using both ultrasonic wave, heat and load”. However, in the case of the inner lead 60 that is bonded at two locations, the upper electrode pad 30 is bonded after the lower electrode pad 56 is bonded first. Therefore, the semiconductor element 28 and the semiconductor element 54 are electrically connected within the semiconductor device 50 by the inner lead 60.

  Here, the semiconductor elements can be combined with semiconductor elements having different functions. That is, the upper semiconductor element 28 can be a logic semiconductor element and the lower semiconductor element 54 can be a memory semiconductor element. Of course, the combination is not limited to this, and the functions of the semiconductor device can be increased by various combinations such as logic or memory semiconductor elements.

  Thus, in the semiconductor device 50 of the present embodiment, a plurality of semiconductor elements are provided in the semiconductor device, and each semiconductor element is electrically connected. That is, the semiconductor element 28 and the semiconductor element 54 are arranged in the same package and share the package and the land 17. Further, since the semiconductor element 28 and the semiconductor element 54 are arranged in a stacked manner, that is, both the semiconductor elements are overlapped in the thickness direction, the semiconductor device 50 is compared with the case where the semiconductor elements are arranged in a plane. The external dimensions in the mounting surface direction are reduced.

  As a result, the mounting space is reduced and the mounting density is improved as compared with the case where a plurality of semiconductor devices having a conventional structure in which one semiconductor element is housed in one package are mounted in a predetermined range.

  Also, compared to the conventional case where each semiconductor device is electrically connected through an external path such as a substrate pattern, the connection path between the semiconductor elements is shortened, which is advantageous for delay in signal transmission time. is there.

  Next, a third embodiment of the present invention will be described. In the third embodiment, since the configuration is substantially the same as that described in the first and second embodiments, the same components are denoted by the same reference numerals, and the description of the configuration is omitted. The feature of the third embodiment relates to the connection structure of the semiconductor element in the second embodiment.

  FIG. 7 shows a semiconductor device 70 according to the third embodiment of the present invention. The semiconductor device 70 has a structure in which a semiconductor element 28 and a semiconductor element 54 are connected by an inner lead 18 and an inner lead 58 provided on the same land 17. That is, each semiconductor element is electrically connected directly to the land 17 without using the inner lead 60 joined at two places as in the second embodiment.

  This eliminates the need for a complicated connection structure and method that spans between the semiconductor element 28 and the semiconductor element 54, and simplifies the bonding method.

  Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, since the configuration is substantially the same as that described in the first embodiment, the same components are denoted by the same reference numerals, and the description of the configuration is omitted. The feature of the fourth embodiment relates to an arrangement structure of semiconductor elements different from those of the second and third embodiments.

  8 and 9 show a semiconductor device 80 according to the fourth embodiment of the present invention. In the semiconductor device 80, two tape carriers are arranged side by side on the same plane, and each tape carrier is provided with a semiconductor element having substantially the same external dimensions and thickness. Here, the semiconductor element 28L is substantially fixed to the left tape carrier 24L, and the semiconductor element 28R is substantially fixed to the right tape carrier 24R by an elastomer 26, respectively. Further, the semiconductor elements 28L and 28R are joined to the lands 17 provided on the tape carriers 24L and 28R by the electrode pads 30 by the inner leads 18.

  Further, a part of the land 17 located adjacent to the tape carriers 24L and 28R is divided into an inner lead 82 joined to the adjacent semiconductor element and a fork in the middle, and each tip is connected to the semiconductor elements 28L and 28R. An inner lead 84 is provided. Therefore, the semiconductor elements 28L and 28R are electrically connected by the inner lead 84.

  As described above, in the semiconductor device 80, since the semiconductor elements are arranged side by side in the same plane, the semiconductor device can be made thinner than the case where the semiconductor elements are arranged in a stack, and each semiconductor device is mounted side by side on a plane such as a substrate. The mounting area is also reduced compared to the arrangement of. Therefore, for example, when applied to a thin device or the like, the mounting density is improved as compared with a semiconductor device having a conventional structure.

  Further, when arranged in parallel as described above, they can be accommodated in one package regardless of the size of each semiconductor element.

  In the second, third, and fourth embodiments, the number of semiconductor elements in the semiconductor device is two. However, the number of arrangements is not limited to this, and the number of semiconductor elements is also applicable to three or more. Is possible.

  In all the embodiments, the present invention can also be applied to a BGA structure semiconductor device in which the inner lead used for wiring between the land and the electrode pad of the semiconductor element is a gold wire (wire) or the like.

It is a 1st Embodiment of this invention and is a schematic sectional drawing which shows the state by which the soldering resist was provided in the lower surface of the base base material. It is a figure explaining the manufacturing method of the tape carrier part which concerns on the 1st Embodiment of this invention, (A) is the state in which the elongate base base material used as the raw material of a tape carrier was set, (B) is a base A state in which hole processing is performed on the base material, (C) shows a state in which a photosensitive resist and a back coat material are applied to the base base material. It is a figure explaining the manufacturing method of the tape carrier part which concerns on the 1st Embodiment of this invention, (D) is the state in which the circuit pattern was formed in the photosensitive resist by exposure and image development, (E) is a base base material A state in which the copper foil is etched to form lands and inner leads, and (F) shows a state in which a solder resist is applied to a part of the lands and inner leads to complete a tape carrier. It is a figure explaining the manufacturing method of the semiconductor device of the BGA structure which concerns on the 1st Embodiment of this invention, (G) is the state in which the elastomer was affixed on the soldering resist of a tape carrier, (H) is a semiconductor in an elastomer. A state in which the element is substantially fixed, (I) shows a state in which the inner lead is bonded to the electrode pad of the semiconductor element. It is a figure explaining the manufacturing method of the semiconductor device of the BGA structure which concerns on the 1st Embodiment of this invention, (J) is the state in which the inner lead and the inner bonding part were sealed with resin, (K) is land A state in which solder balls are mounted, (L) shows a state in which a product portion is punched from the tape carrier and a semiconductor device having a BGA structure is completed. FIG. 6A is a top view of a semiconductor device having a BGA structure according to a second embodiment of the present invention, and FIG. 6B is a schematic cross-sectional view taken along line 6-6 of FIG. FIG. 8A is a top view of a semiconductor device having a BGA structure according to a third embodiment of the present invention, and FIG. 7B is a schematic cross-sectional view taken along line 7-7 of FIG. It is a top view which shows the semiconductor device of the BGA structure which concerns on 4th Embodiment of this invention. FIG. 9A is a schematic cross-sectional view taken along line 9a-9a in FIG. 8 and FIG. 8B is a cross-sectional view taken along line 9b-9b in FIG. 8, showing a semiconductor device having a BGA structure according to a fourth embodiment of the present invention. It is a schematic sectional drawing. It is a schematic sectional drawing which shows the semiconductor device of the conventional BGA structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 12 ... Base base material 12a ... Ball mounting hole (hole)
20 ... Solder ball (external connection terminal)
22 ... Solder resist (step removal member / insulating layer)
26 ... Elastomer (elastic body)
28 ... Semiconductor element 28L ... Semiconductor element 28R ... Semiconductor element 30 ... Electrode pad (electrode part)
50 ... Semiconductor device 54 ... Semiconductor element 56 ... Electrode pad (electrode part)
70 ... Semiconductor device 80 ... Semiconductor device

Claims (5)

Forming an electrode portion for providing an external connection terminal exposed on the front surface side from the hole on the back surface of the base substrate in which the hole is formed;
Providing an insulating layer on the back surface of the base substrate to eliminate a step between the base substrate and the electrode part;
The base substrate is disposed so as to face the surface of the semiconductor element with a sheet-like elastic body interposed between the base substrate provided with the insulating layer and the surface of the semiconductor element, and the electrode Electrically connecting a portion and an electrode pad provided on the surface of the semiconductor element;
A method for manufacturing a semiconductor device, comprising: In the step of electrically connecting the electrode part and the electrode pad of the semiconductor element,
After the sheet-like elastic body is provided so as to face the insulating layer with respect to the base substrate on which the electrode part and the insulating layer are provided, the electrode part, the insulating layer, and the elastic body are The method for manufacturing a semiconductor device according to claim 1, wherein the provided base material is disposed with respect to the semiconductor element.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer is made of the same material as the base substrate.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the material is polyimide.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer is applied by screen printing.

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