JPH0786737A - Manufacture of thin film multilayer circuit board - Google Patents
Manufacture of thin film multilayer circuit boardInfo
- Publication number
- JPH0786737A JPH0786737A JP23271493A JP23271493A JPH0786737A JP H0786737 A JPH0786737 A JP H0786737A JP 23271493 A JP23271493 A JP 23271493A JP 23271493 A JP23271493 A JP 23271493A JP H0786737 A JPH0786737 A JP H0786737A
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- Prior art keywords
- metal
- layer
- conductive layer
- film
- insulating layer
- Prior art date
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はビアの断線を無くした薄
膜多層回路基板の製造方法に関する。薄膜多層回路基板
はセラミックスやメタルコアよりなる耐熱性基板上に薄
膜形成技術と写真蝕刻技術（フォトリソグラフィ）を用
いて導体金属よりなる配線パターンを形成した後、この
上にポリイミドのような有機材料を用いて絶縁層を形成
し、この上に配線パターンを形成する方法を繰り返すこ
とにより多層化して形成されている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film multilayer circuit board which eliminates the disconnection of vias. A thin film multilayer circuit board is formed by forming a wiring pattern made of a conductive metal on a heat resistant substrate made of ceramics or a metal core by using a thin film forming technique and a photolithography technique (photolithography), and then forming an organic material such as polyimide on it. An insulating layer is formed by using the insulating layer, and a method of forming a wiring pattern on the insulating layer is repeated to form a multilayer structure.
【０００２】すなわち、基板上に搭載するＬＳＩやＶＬ
ＳＩなどの半導体集積回路は少なくとも信号配線，電源
配線，グランド配線が必要であり、これらを錯綜してパ
ターン形成する必要があり、また、情報処理装置におい
ては、更に多数の集積回路を配列することから、回路基
板は必然的に多層化構造が採られており、それぞれの配
線層はビア（Via)により回路接続が行なわれている。That is, an LSI or a VL mounted on a substrate
A semiconductor integrated circuit such as SI requires at least signal wiring, power wiring, and ground wiring, and it is necessary to form a pattern by combining these wirings. Further, in an information processing device, a larger number of integrated circuits should be arranged. Therefore, the circuit board inevitably has a multi-layered structure, and the respective wiring layers are circuit-connected by vias.
【０００３】[0003]
【従来の技術】表面実装部品を高密度に搭載したマルチ
・チップ・モジュール（略称ＭＣＭ）のように高密度実
装が行なわれている回路基板にパターン形成されている
配線の最小線幅は10数μm と狭く、上下の配線はビアに
より回路接続が行なわれているが、配線幅の狭小化によ
りビア径は30μm 程度と微細化している。2. Description of the Related Art The minimum line width of a wiring pattern formed on a circuit board on which high density mounting is performed, such as a multi-chip module (abbreviated as MCM) in which surface mounting components are mounted at high density, is ten or more. The wiring is as narrow as μm, and the upper and lower wirings are connected by vias, but the via diameter has been reduced to 30μm due to the narrowed wiring width.
【０００４】こゝで、ビア形成法としては層間絶縁層の
必要とする位置に写真蝕刻技術を用いてビア穴を開けた
後、層間絶縁層の上にスパッタ法や真空蒸着法を用いて
配線パターン形成用の金属薄膜を形成する際に、ビア穴
の中までも金属薄膜が形成できるのを利用してビアの形
成が行なわれていた。As a method of forming a via, a via hole is formed at a position where an interlayer insulating layer is required by using a photo-etching technique, and then a wiring is formed on the interlayer insulating layer by a sputtering method or a vacuum deposition method. When the metal thin film for pattern formation is formed, the via is formed by utilizing the fact that the metal thin film can be formed even in the via hole.
【０００５】すなわち、層間絶縁層の上に密着性強化と
導電層形成金属のマイグレーションを防ぐための金属膜
としてクローム(Cr)やチタン(Ti)などの金属をスパッタ
法などを用いて数100 Åの厚さに膜形成し、更に、この
上に導電層形成金属膜として銅(Cu)など電導度の優れた
金属をスパッタ法などで数100 Åの厚さに膜形成し、更
に、メッキ処理を行なって所定の厚さの導電層を形成し
ているが、このスパッタ法などで数100 Åの薄膜を形成
する段階でビア穴の底までも膜形成できることを利用し
ていた。That is, metal such as chrome (Cr) or titanium (Ti) is used as a metal film for enhancing adhesion and preventing migration of the metal for forming the conductive layer on the interlayer insulating layer by using the sputtering method for several hundred Å. To a thickness of several hundred Å by a metal such as copper (Cu) having a high electrical conductivity as a conductive layer forming metal film by a sputtering method. Although a conductive layer having a predetermined thickness is formed by performing the above, the fact that a film can be formed even on the bottom of the via hole at the stage of forming a thin film of several 100 Å by this sputtering method or the like was used.
【０００６】然し、ビア径は30μm 程度まで縮小化し、
また、層間絶縁層として厚さが50μm 程度のものを使用
して、アスペクト比が１以上となるような条件では、ビ
ア穴の内部まで膜形成することは困難であり、そのた
め、断線が生じ易かった。However, the via diameter is reduced to about 30 μm,
In addition, it is difficult to form a film inside the via hole under the condition that the aspect ratio is 1 or more by using the interlayer insulating layer having a thickness of about 50 μm, and therefore the disconnection is apt to occur. It was
【０００７】[0007]
【発明が解決しようとする課題】高密度実装を行なう薄
膜多層回路基板においては配線のパターン幅は微少化し
ており、そのため、ビア径は30μm 程度まで微細化し、
アスペクト比は１を越えるようになっているが、かゝる
薄膜多層回路においては上下の配線層を回路接続するビ
アのエッジ部で断線が生じ易く、製造歩留りを低下させ
ている。そこで、この解決が課題である。In a thin film multilayer circuit board for high-density mounting, the pattern width of the wiring has been reduced, and therefore the via diameter has been reduced to about 30 μm.
The aspect ratio exceeds 1, but in such a thin film multilayer circuit, disconnection is likely to occur at the edge portion of the via that connects the upper and lower wiring layers to each other, which lowers the manufacturing yield. Therefore, this solution is an issue.
【０００８】[0008]
【課題を解決するための手段】上記の課題は第１の導電
層を備えた絶縁基板上にビア穴を含む第１の絶縁層を形
成し、次に、このビア穴に金属粒を充填し、次に、超微
粒子金属ペーストを第１の絶縁層上にスピンコートした
後、加熱してビア穴の金属粒を第１の導電層に密着させ
ると共に第１の絶縁層上に金属膜を形成し、次に、金属
膜を形成した第１の絶縁層上に密着性強化金属膜と導電
層形成金属膜との積層膜を形成し、次に、積層膜の上に
レジストを被覆した後、配線パターン形成位置を窓開け
し、窓開け位置に所定の厚さに導電層形成金属をメッキ
して配線を形成し、次に、レジストを除去した後、配線
形成位置を除いて第１の絶縁層上に存在する金属膜をエ
ッチングして除去して第２の導電層を形成する工程とを
少なくとも含むことを特徴として薄膜多層回路基板を製
造することにより解決することができる。[Means for Solving the Problems] The above object is to form a first insulating layer including a via hole on an insulating substrate having a first conductive layer, and then fill the via hole with metal particles. Then, after spin-coating the ultrafine metal paste on the first insulating layer, it is heated to bring the metal particles of the via hole into close contact with the first conductive layer and form a metal film on the first insulating layer. Then, a laminated film of the adhesion-strengthening metal film and the conductive layer-forming metal film is formed on the first insulating layer having the metal film formed thereon, and then the resist is coated on the laminated film, A window is opened at the wiring pattern forming position, a conductive layer forming metal is plated at a predetermined thickness at the window forming position to form a wiring, and then the resist is removed, and then the first insulating layer is formed except for the wiring forming position. Etching the metal film present on the layer to form a second conductive layer. It can be solved by manufacturing a thin film multi-layer circuit board as said.
【０００９】[0009]
【作用】高密度実装が行なわれている薄膜多層回路基板
のビアとしては直径30μm 程度のものが用いられてお
り、一方、層間絶縁層の薄層化には限度があるためにア
スペクト比は１を越えるに到っているが、かゝる形状の
ビア穴については従来のようなビア形成法を適用するこ
とは無理である。そこで、本発明はビア穴を底上げする
ために電導度の良い金属よりなる金属粒を挿入するもの
である。[Function] As a via of a thin film multi-layer circuit board on which high-density mounting is performed, a via having a diameter of about 30 μm is used. On the other hand, the aspect ratio is 1 because the thinning of the interlayer insulating layer is limited. However, it is impossible to apply the conventional via forming method to the via hole having such a shape. Therefore, the present invention inserts metal particles made of a metal having a high electric conductivity in order to raise the bottom of the via hole.
【００１０】こゝで、ビア穴にこれに見合った直径の金
属粒を挿入することは理想的であるが、基板上に直径が
約30μm のビア穴が不規則に膨大な数量存在する状態に
おいては不可能であり、また、挿入できたとしても層間
絶縁層の下にパターン形成してある導電層と良好な導通
を確保することは難しい。Here, it is ideal to insert metal particles of a diameter corresponding to this into the via holes, but in the state where a large number of via holes with a diameter of about 30 μm are irregularly present on the substrate. Is impossible, and even if it can be inserted, it is difficult to secure good conduction with the conductive layer patterned under the interlayer insulating layer.
【００１１】そこで、本発明は、 ビア穴に較べて遙かに小さい金属粒を揺動手段など
により挿入して底上げを行なう。 底上げしたビア穴に超微粒子金属ペーストを供給し
て金属粒と下の導電層との導通を確保する。 ものである。図２は本発明に係るビア形成の原理図であ
って、ビア穴１が穴開けしてある第１の絶縁層２の下に
は第１の導電層３が形成してあるが、このビア穴１の中
にこれに較べて粒径が遙かに小さい金属粒４を複数個挿
入する。こゝで、目的は底上げにあることから、金属粒
４は真球である必要もなく、また、必ずしもビア穴１を
埋める必要もないが、必ず複数個は挿入してある必要が
あり、そのためにはビア穴１をもつ絶縁基板を治具で固
定し、金属粒４を供給して振動を与え、金属粒４をビア
穴１に落とし込むのがよく、その後、表面に残存する余
分の金属粒４を掃きとることにより同図（Ａ）に示すよ
うに部分的に金属粒４を充填することができる。Therefore, according to the present invention, metal particles that are much smaller than the via holes are inserted by rocking means or the like to raise the bottom. The ultrafine metal paste is supplied to the raised via hole to secure the conduction between the metal grains and the conductive layer below. It is a thing. FIG. 2 is a principle diagram of via formation according to the present invention. A first conductive layer 3 is formed below a first insulating layer 2 having a via hole 1 formed therein. A plurality of metal particles 4 having a particle diameter much smaller than that of the hole 1 is inserted into the hole 1. Here, since the purpose is to raise the bottom, the metal particles 4 do not have to be true spheres, and the via hole 1 does not necessarily have to be filled, but it is necessary to insert a plurality of them. It is preferable to fix the insulating substrate having the via hole 1 with a jig and supply the metal particles 4 to give vibration to drop the metal particles 4 into the via hole 1 and then to remove the excess metal particles remaining on the surface. By sweeping away the metal particles 4, the metal particles 4 can be partially filled as shown in FIG.
【００１２】次に、第１の絶縁層２の上に粘度調節した
超微粒子金属ペーストをスピンコートすると、超微粒子
金属ペーストはビア穴１に入るだけでなく、毛細管現象
が働く結果、第１の導電層３に到るまで注入することが
でき、これを加熱することによりビア穴１を金属により
底上げすることができる。なお、第１の絶縁層２の上に
は超微粒子金属ペーストよりなる金属膜５が形成され
る。（以上同図Ｂ） 次に、導電層形成金属のマイグレーションを防ぎ、且
つ、密着性を向上するため、密着性強化金属膜６と導電
層形成金属膜７を従来と同様にスパッタ法などにより膜
形成すると、ビア穴１は底上げされているので、アスペ
クト比が１以下の場合と同様にビア穴１の中も一様に膜
形成することができる。（以上同図Ｃ） 次に、この上にレジスト９を被覆した後、配線パターン
形成位置を窓開けし、この位置に導電層形成金属をメッ
キして配線10を形成する。( 以上同図Ｄ） 以下、レジスト９を除いた後、このレジスト存在位置を
第１の絶縁層２に達するまでエッチングすることにより
断線のないビアを備えた導電層を形成することができ
る。Next, when the viscosity-adjusted ultrafine particle metal paste is spin-coated on the first insulating layer 2, not only the ultrafine particle metal paste enters the via hole 1, but also a capillary phenomenon works. It can be injected up to the conductive layer 3, and by heating this, the via hole 1 can be raised by metal. A metal film 5 made of ultrafine metal paste is formed on the first insulating layer 2. (B in the same figure) Next, in order to prevent the migration of the conductive layer forming metal and improve the adhesion, the adhesion enhancing metal film 6 and the conductive layer forming metal film 7 are formed by a sputtering method or the like as in the conventional method. Since the via hole 1 is raised when formed, a film can be uniformly formed in the via hole 1 as in the case where the aspect ratio is 1 or less. Next, after coating the resist 9 thereon, a wiring pattern forming position is opened and a conductive layer forming metal is plated at this position to form the wiring 10. (Above, the same figure D) Hereinafter, after removing the resist 9, by etching the resist existing position until reaching the first insulating layer 2, it is possible to form a conductive layer having vias without disconnection.
【００１３】[0013]
【実施例】実施例１：（図１関連） 100mm 角で厚さが２ mm の窒化アルミニウム（AlN)基板
12を用い、この上に薄膜形成技術と写真蝕刻技術を用い
てCr/Cu/Crの三層構造をとる第１の導電層３を形成し
た。すなわち、スパッタ法を用いてCrを700 Åの厚さ
に、引き続いてCuを700 Åの厚さに層形成した後、基板
上にレジストを被覆し、配線形成位置を窓開けし、この
位置にCuを５μm の厚さにメッキして配線を作り、レジ
ストを除去した後に基板上にCrを700 Åの厚さにスパッ
タし、配線を除く位置のCr/Cu/Cr層を溶解除去すること
により第１の導電層を形成した。EXAMPLES Example 1: (Related to FIG. 1) Aluminum nitride (AlN) substrate 100 mm square and 2 mm thick
12 was used to form a first conductive layer 3 having a three-layer structure of Cr / Cu / Cr by using a thin film forming technique and a photo-etching technique. That is, after forming a layer of Cr to a thickness of 700 Å and then a layer of Cu to a thickness of 700 Å using the sputtering method, cover the substrate with a resist and open a wiring formation position at this position. Cu is plated to a thickness of 5 μm to form wiring, and after removing the resist, Cr is sputtered on the substrate to a thickness of 700 Å and the Cr / Cu / Cr layer at the position excluding the wiring is dissolved and removed. A first conductive layer was formed.
【００１４】次に、この基板上に感光性ポリイミド前駆
体ワニスをスピンコートし、溶剤を乾燥させてから、マ
スクを用いて紫外線の選択露光を行なって感光させた
後、N-メチル-2- ピロリドンを用いて現像を行い、次
に、350 ℃で30分加熱してイミド化させることにより所
定の位置に径30μm のビア穴１を備えた第１の絶縁層２
を形成した。（以上図１Ａ） 次に、ビア穴１に挿入する金属粒４として平均粒径が５
μm のCu粉（三井金属製）を用い、このCu粉を満たして
ある容器中に基板12を入れ、超音波振動を加えることで
ビア穴１の中に金属粒４を挿入させた。（以上同図Ｂ） 次に、超微粒子金属ペーストとして独立分散超微粒子ペ
ースト（真空冶金，商品名）を用い、メチルエチルケト
ンを用いて粘度調節を行なった後、基板上にスピンコー
トし、溶剤を乾燥させてから、300 ℃で１時間熱処理す
ることにより厚さが２μm のAgよりなる金属膜５を形成
したが、ビア穴１は中の金属粒４の上まで密に金属膜５
が形成されていた。（以上同図Ｃ） 次に、この金属膜５の上に密着性強化金属膜６としてCr
を、また、導電層形成金属７としてCuを従来と同様にス
パッタ法によりそれぞれ700 Åの厚さに膜形成した。(
以上同図Ｄ） 次に、この基板上にレジスト９を被覆し、従来と同様に
配線形成位置を窓開けした後に、Cuの無電解メッキを行
い、厚さが５μm の配線10をパターン形成した。( 以上
同図Ｅ） 次に、レジスト９を溶解除去した後、Crをフェリシアン
化カリ[K3Fe(CN)6] のアルカリ溶液で、また、Cuを過硫
酸アンモニウム[(NH4)2S2O8]の水溶液で溶解除去した
後、アセトンで金属膜の樹脂成分を除去することで第２
の導電層14を形成した。( 以上同図Ｆ） このようなビア形成法を使用することにより、ビアのエ
ッジ部での断線がなくなり、また、ビアの抵抗値を約５
mΩと従来に較べて大幅に低下させることができた。Next, a photosensitive polyimide precursor varnish was spin-coated on this substrate, the solvent was dried, and then selective exposure of ultraviolet rays was carried out using a mask to expose it, and then N-methyl-2- Development is carried out using pyrrolidone, then heating at 350 ° C. for 30 minutes to imidize the first insulating layer 2 with a via hole 1 having a diameter of 30 μm at a predetermined position.
Was formed. (Above FIG. 1A) Next, as the metal particles 4 to be inserted into the via hole 1, the average particle diameter is 5
Using Cu powder (made by Mitsui Metal Co., Ltd.) having a diameter of μm, the substrate 12 was placed in a container filled with this Cu powder, and ultrasonic vibration was applied to insert the metal particles 4 into the via hole 1. (B in the same figure) Next, the independent dispersion ultrafine particle paste (vacuum metallurgy, trade name) is used as the ultrafine particle metal paste, the viscosity is adjusted using methyl ethyl ketone, and then spin coating is performed on the substrate and the solvent is dried. After that, a metal film 5 made of Ag having a thickness of 2 μm was formed by heat treatment at 300 ° C. for 1 hour. The via hole 1 was densely formed on the metal particles 4 inside.
Had been formed. (Above C in the same figure) Next, as the adhesion enhancing metal film 6, Cr is formed on the metal film 5.
And Cu as the conductive layer forming metal 7 were formed into a film having a thickness of 700 Å by the sputtering method as in the conventional case. (
As described above, the same FIG. D) Next, resist 9 is coated on this substrate, a wiring formation position is opened as in the conventional case, and then Cu electroless plating is performed to form a wiring 10 having a thickness of 5 μm. . Next, after removing the resist 9 by dissolution, Cr is an alkaline solution of potassium ferricyanide [K 3 Fe (CN) 6 ] and Cu is ammonium persulfate [(NH 4 ) 2 S. 2 O 8 ] is dissolved and removed in an aqueous solution, and then the resin component of the metal film is removed with acetone
The conductive layer 14 of was formed. (F in the same figure F) By using such a via forming method, there is no disconnection at the edge portion of the via, and the resistance value of the via is about 5
It was able to be drastically reduced compared to the conventional one with mΩ.
【００１５】[0015]
【発明の効果】本発明によれば、ビア穴の径が30μm 以
下と小さく、且つ、アスペクト比が１を越すような薄膜
多層回路基板をビアの断線を伴うことなく形成すること
が可能となる。According to the present invention, it is possible to form a thin film multilayer circuit board having a via hole diameter as small as 30 μm or less and an aspect ratio of more than 1 without disconnection of the via. .
【図１】 本発明の工程を示す断面図である。FIG. 1 is a cross-sectional view showing a process of the present invention.
【図２】 ビア形成の原理図である。FIG. 2 is a principle diagram of via formation.
１ ビア穴 ２ 第１の絶縁層 ３ 第１の導電層 ４ 金属粒 ５ 金属膜 ６ 密着性強化金属膜 ７ 導電層形成金属膜 ９ レジスト 10 配線 14 第２の導電層 1 Via Hole 2 First Insulating Layer 3 First Conductive Layer 4 Metal Grains 5 Metal Film 6 Adhesion Strengthening Metal Film 7 Conductive Layer Forming Metal Film 9 Resist 10 Wiring 14 Second Conductive Layer
Claims (1)
にビア穴（１）を含む第１の絶縁層（２）を形成し、 次に、該ビア穴（１）に金属粒（４）を充填し、 次に、超微粒子金属ペーストを前記第１の絶縁層（２）
の上にスピンコートした後、加熱してビア穴（１）の金
属粒（４）を第１の導電層（３）に密着させると共に第
１の絶縁層（２）の上に金属膜（５）を形成し、 次に、該金属膜（５）を形成した第１の絶縁層（２）の
上に密着性強化金属膜（６）と導電層形成金属膜（７）
との積層膜を形成し、 次に、該積層膜の上にレジスト（９）を被覆した後、配
線パターン形成位置を窓開けし、該窓開け位置に所定の
厚さに導電層形成金属をメッキして配線（10）を形成
し、 次に、レジスト（９）を除去した後、配線形成位置を除
いて第１の絶縁層（２）の上に存在する金属膜（５）を
エッチングして除去して第２の導電層（14）を形成する
工程を含むことを特徴とする薄膜多層回路基板の製造方
法。1. A first insulating layer (2) including a via hole (1) is formed on an insulating substrate provided with a first conductive layer (3), and a metal is then formed in the via hole (1). The particles (4) are filled, and then the ultrafine metal paste is added to the first insulating layer (2).
After spin-coating on it, it is heated to bring the metal particles (4) of the via hole (1) into close contact with the first conductive layer (3), and at the same time, to form a metal film (5) on the first insulating layer (2). ) Is formed, and then the adhesion enhancing metal film (6) and the conductive layer forming metal film (7) are formed on the first insulating layer (2) on which the metal film (5) is formed.
And a resist (9) is coated on the laminated film, a window is formed at a wiring pattern forming position, and a conductive layer forming metal is formed at a predetermined thickness at the window opening position. The wiring (10) is formed by plating, the resist (9) is then removed, and then the metal film (5) existing on the first insulating layer (2) is etched except the wiring formation position. And a second conductive layer (14) to form a second conductive layer (14).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23271493A JPH0786737A (en) | 1993-09-20 | 1993-09-20 | Manufacture of thin film multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23271493A JPH0786737A (en) | 1993-09-20 | 1993-09-20 | Manufacture of thin film multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0786737A true JPH0786737A (en) | 1995-03-31 |
Family
ID=16943638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23271493A Withdrawn JPH0786737A (en) | 1993-09-20 | 1993-09-20 | Manufacture of thin film multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0786737A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054652A (en) * | 1997-04-18 | 2000-04-25 | Fujitsu Limited | Thin-film multi-layer substrate and electronic device |
| JP2000123634A (en) * | 1998-08-10 | 2000-04-28 | Vacuum Metallurgical Co Ltd | Copper very fine particle independent dispersion solution |
| JP2001035255A (en) * | 1999-07-22 | 2001-02-09 | Vacuum Metallurgical Co Ltd | Silver superfine particle independently dispersed solution |
| JP2006093280A (en) * | 2004-09-22 | 2006-04-06 | Miyachi Technos Corp | Method for connecting between wiring layers of printed wiring board |
-
1993
- 1993-09-20 JP JP23271493A patent/JPH0786737A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054652A (en) * | 1997-04-18 | 2000-04-25 | Fujitsu Limited | Thin-film multi-layer substrate and electronic device |
| JP2000123634A (en) * | 1998-08-10 | 2000-04-28 | Vacuum Metallurgical Co Ltd | Copper very fine particle independent dispersion solution |
| JP2001035255A (en) * | 1999-07-22 | 2001-02-09 | Vacuum Metallurgical Co Ltd | Silver superfine particle independently dispersed solution |
| JP2006093280A (en) * | 2004-09-22 | 2006-04-06 | Miyachi Technos Corp | Method for connecting between wiring layers of printed wiring board |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20001128 |