JP2001094224A - Printed interconnection board and method of manufacturing printed interconnection board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multilayer printed interconnection board which can be manufactured with a high yield of the wiring circuit made by precise process and has the excellent bonding performance of the circuit. SOLUTION: An inner insulating layer 8 is formed on the surface of a 1st inner wiring layer including a land 7. A blind via-hole 9 is drilled in the inner insulating layer 8. A vacuum deposition copper layer 10 is formed on the surface in a vacuum. A plating resist film 11 with a wiring circuit pattern is formed on the vacuum deposition copper layer 10. A copper plating layer 12 is formed through the pattern. The resist film 11 is removed and then an inner wiring circuit pattern is formed by selective etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a printed wiring board and a method for manufacturing a printed wiring board.

[0002]

2. Description of the Related Art In response to the multi-media age, LSI
Are integrated as much as possible. Along with this, printed wiring boards are required to be reduced in size, extremely thinned, lighter, higher in density, lower in cost, and the like. As a technique for manufacturing a printed wiring board that satisfies this demand, a build-up type multilayer printed wiring board has attracted attention.

In recent years, as electronic devices such as mobile phones, Internet mobile terminals, and mobile personal computers have become lighter and thinner, there has been a demand for higher multilayer and higher density printed wiring boards.

[0004] In general, a method of manufacturing a laminated multilayer printed wiring board is as follows. That is, a copper-clad laminate (copper foil) used as an inner circuit board is provided on both sides or one side on the front and back surfaces of the insulator substrate. By selectively etching the copper-clad laminate (copper foil) using the wiring circuit pattern as a mask, an inner circuit board having an inner wiring layer formed thereon is manufactured.
A plurality of the inner layer circuit boards are manufactured. For each inner layer circuit board, the surface of the copper foil of the electric circuit pattern is surface-treated.

Further, a copper-clad laminate (copper foil) to be used as an outer circuit board is provided on both sides or one side on the front and back surfaces of the insulator substrate.

[0006] Next, a prepreg is laminated as an inner insulating layer between the inner circuit boards. Further, the outer layer circuit boards are arranged at upper and lower portions as outermost layers. In this laminated state, it is set on a press jig, and heated and pressed to form an integral unit. Thereafter, an outer wiring layer having a predetermined electric wiring circuit pattern is formed on the outermost copper foil. This outer wiring layer is subjected to a surface treatment on the surface of the copper foil.

[0007] Further, resin sheets with copper foil are arranged on the upper and lower surfaces of the laminate having the above-described configuration, and the laminate is again mounted on a press jig and heated and pressed to be integrally laminated. Thus, a multilayer printed wiring board is manufactured.

A via hole is formed in an outer wiring board of the multilayer printed wiring board. That is, the outermost copper foil at the via hole formation position is removed by selective etching. Next, a hole is formed by irradiating a laser beam to the position where the etching has been removed. By forming a metal plating layer on the inner wall surface of the hole, electrical connection between wiring layers is performed, and a multilayer printed wiring board is formed.

In the case of forming a via hole over a plurality of inner circuit boards and outer circuit boards, an ordinary laminated printed wiring board is formed as follows. That is, in a state where the resin sheet with copper foil is arranged on both the upper and lower surfaces of the multilayer printed wiring board, the resin sheet is mounted on the press jig, heated and pressed, and integrally molded, and then a step of forming a via hole is repeated to form a plurality of layers. Via holes for interlayer connection are formed.

[0010]

The use of copper foil for forming a wiring circuit on a printed wiring board has the advantage of good adhesion and good repairability. However, a wiring layer for forming an electric circuit pattern is formed by further forming a plating layer on the copper foil. Therefore, the thickness of the wiring layer becomes large, which causes a decrease in yield when forming a wiring circuit by fine processing.

In particular, in LSI, the possibility of manufacturing up to 15 Gbits of integration is increasing, and the degree of integration is improving year by year. In accordance with this degree of integration, CSP (Chip Size Pa)
The technology for mass production of packaging has been established, and mass production of some models started in 1999.

The CSP mounting means that the number of electrode pins per unit area increases as the degree of integration increases. This increase in the number of electrode pins means an increase in the number of solder bumps.
A miniaturization technique is required for forming a mounting part land pattern.

[0013] It has been desired to develop a method capable of producing a wiring circuit by fine processing with a good yield while making use of these advantages.

The present invention has been made in view of the above points,
An object of the present invention is to provide a method of manufacturing a printed wiring board and a multilayer printed wiring board which can be finely processed, have a high yield, and have good circuit adhesion.

Further, the present invention is particularly suitable when applied to a build-up type multilayer printed wiring board and a method for manufacturing the same.

[0016]

The inventors of the present invention have made intensive studies to achieve the above objects and objects, and as a result, have found that a laminated printed wiring board, a build-up multilayer printed wiring board, and a method of manufacturing the same. It has been found that the above object can be achieved by forming a wiring layer including a power supply layer by a conductor layer formed in a vacuum in place of a copper foil and using the wiring layer as an adhesion layer to an insulator substrate, The present invention has been completed.

The printed wiring board of the present invention comprises, for example, a conductor layer formed on an insulator in a vacuum, and a conductor plating layer provided on the conductor layer. The wiring layer is constituted by a laminated structure of the plating layers.

The printed wiring board of the present invention comprises, for example, an insulating substrate, a copper vapor deposition layer provided on the insulating substrate, and a wiring layer in which a copper plating layer is laminated on the copper vapor deposition layer. A first wiring, an insulating layer provided on the first wiring and the insulating substrate, and a wiring layer formed by stacking a copper vapor deposition layer and a copper plating layer provided on the insulating layer And a second wiring comprising:

The method for manufacturing a printed wiring board according to the present invention comprises:
For example, a step of forming a conductor layer in a vacuum on an insulator,
The method includes a step of forming a wiring layer in which a conductive plating layer is laminated on the conductor layer, and a step of selectively etching the wiring layer to form a wiring circuit pattern.

The method for manufacturing a printed wiring board according to the present invention comprises:
For example, a step of forming a blind via hole in an insulator, a step of forming a conductor layer in a vacuum on the insulator including the blind via hole formed in this step, and a step of forming a conductor plating layer on the conductor film The method includes a step of forming a laminated wiring layer, and a step of selectively etching the wiring layer to form a wiring circuit pattern.

The method for manufacturing a printed wiring board according to the present invention comprises:
For example, a step of forming a conductor layer in a vacuum on an insulator,
A step of forming a mask pattern of a wiring pattern on the conductor layer, a step of forming a plating layer of a conductor on the conductor layer, a step of removing the mask pattern, and a step of removing the exposed conductor layer The method comprises: In the method for manufacturing a printed wiring board according to the present invention, for example, means for forming a conductor layer in a vacuum is formed by vacuum evaporation, sputtering,
CVD and the like.

[0022]

Next, an embodiment in which the present invention is applied to a printed wiring board will be described with reference to FIG. FIG.
FIG. 7 is a cross-sectional view for describing a manufacturing step of forming an inner wiring layer on a printed wiring board in the order of steps.

Formation of First Layer of Wiring Layer A conductor layer for forming a wiring circuit is formed in vacuum on the front and back surfaces of an insulating substrate, for example, a glass epoxy resin substrate 1. This film forming means forms, for example, copper vapor deposited layers 2 and 3. The thickness of the vapor deposition layers 2 and 3 is, for example, 1 μm. These vapor deposition layers 2 and 3 are, for example, vacuum vapor deposition. The degree of vacuum at the time of vapor deposition is selected to be 5 × 10 ⁻⁵ Torr or less.
By forming a thin layer of 1.5 μm or less and 0.5 μm or more for the first conductor layer, high-definition and high-density wiring can be realized with a high yield.

Means for forming a film in a vacuum include sputtering, plasma CVD, thermal CVD and other vapor phase growth, and epitaxial growth. The copper vapor deposition layer 2 on the front and back surfaces,
One of the three is an inner wiring layer.

Formation of a Resist Film A photosensitive resist, for example, a plating resist layer 4 is applied on the copper wiring layer 2 on the inner wiring layer side. The plating resist layer 4 is exposed and developed using a predetermined inner wiring circuit pattern as a mask. By this process, the plating resist layer 4 is selectively removed. This state is shown in FIG.

Next, a conductor is formed on the plating resist layer 4 and the exposed copper deposition layer 2, for example, a copper plating layer 5 is formed as shown in FIG. . This plating means is desirably electrolytic plating. By performing the electroplating, a current mainly flows through the exposed vapor deposition layer 2, and the plating layer 5 can be formed on the vapor deposition layer 2 in a concentrated manner. The thickness of the plating layer 5 is, for example, 2 μm, which is thicker than the vapor deposition layers 2 and 3. Next, the plating resist layer 4 is removed by etching as shown in FIG.

Further, by performing soft etching, an inner layer wiring circuit pattern is formed as shown in FIG. That is, the exposed copper deposited layer 2 is removed by the soft etching process. Thus, the inner wiring layer 6 having a laminated structure in which the copper plating layer 5 is applied on the copper vapor deposition layer 2 as a base is formed. The soft etching means performs liquid phase etching using, for example, an acidic etching solution as an etching medium.

In the above embodiment, the insulating substrate 1
Other than the above, for example, paper base material-phenolic resin laminated board,
Paper substrate-epoxy resin laminated substrate, paper substrate-polyester resin laminated substrate, paper substrate-Teflon resin laminated substrate, glass substrate-epoxy resin laminated substrate, glass substrate-polyimide resin laminated substrate glass substrate-BT ( (Bisimaleimide-triazine) An insulating substrate such as a synthetic resin substrate such as a resin resin laminated substrate or a composite resin substrate, a polyimide resin, a polyester resin substrate, or a ceramic substrate.

Next, an embodiment in which a multilayer printed wiring board is formed on the inner wiring layer 6 will be described with reference to FIG. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the build-up type printed wiring board in the order of processes.

That is, an embodiment in which a build-up layer is formed on the printed wiring board of the above embodiment and an inner wiring layer is formed will be described. The same parts as those in FIG. 1 are described with the same numbers. An embodiment for interlayer connection with one land 7 in the inner wiring layer 6 will be described. Formation of Inner Insulating Layer By performing a blackening reduction treatment as a pre-process for forming an inner insulating layer (build-up layer), adhesion can be improved. After this processing, an inner insulating layer (build-up layer), for example, a photosensitive polymer epoxy resin layer 8 is formed on the inner wiring layer 6 as shown in FIG.
As shown in FIG.

As described above, one land 7 of the inner wiring layer 6 is shown in FIG. The film forming means of the epoxy resin layer 8 is formed by applying, for example, an epoxy resin liquid, heating and drying.

The coating solution is prepared, for example, by adding aminoethyl- as a silane coupling agent to a photosensitive polymer epoxy resin.
It is a build-up liquid mixed with 2 WT% of aminopropyltrimethoxysilane. The coupling agent may be a titanium-based coupling agent. Next, the curing temperature of the coating film is 140 ° C. to 160 ° C. For example, 150 ° C
For 60 minutes to dry and cure.

Formation of blind via hole (non-through hole) The blind via hole 9 having a depth of about 5
0 μm is formed. The blind via hole 9 is a hole having the land 7 as a bottom surface. This blind beer hall 9
Are, for example, a hole drilling unit by photo-etching, a hole drilling unit by a laser beam, a hole drilling unit by a drill, and the like. The above-described hole forming means by photoetching has an effect that a uniform hole can be simultaneously formed in all the blind via holes 9 in the surface of the epoxy resin layer 8.

That is, when the photo via processing method is used, the blind via hole 4
Can be formed by chemical processing by photo-etching, plasma etching or the like by simultaneously mask patterning. The exposure amount during this photo-etching is 50
~ 700 MJ / CM2 is desirable. The diameter of the blind via hole 9 thus formed is, for example, 30 μm.
It is selected in the range of ５００500 μm.

Formation of First Layer of Wiring Layer On the epoxy resin layer 8 including the blind via holes 9, a conductor layer formed in a vacuum, for example, a copper evaporation layer 10
To form This film formation state is shown in FIG. The copper vapor deposition layer 10 is formed to a thickness of, for example, 1 μm by vacuum vapor deposition.
The degree of vacuum during this vacuum deposition is selected to be 5 × 10 ⁻⁵ Torr or less.

The first layer is a conductor layer formed in a vacuum, and has high adhesion to the underlying epoxy resin layer 8. . The thickness of this conductor layer is suitably 1.5 μm to 0.5 μm in terms of processing. This thin layer enables high-definition, high-density wiring processing.

Means for forming a film in a vacuum include sputtering, plasma CVD, thermal CVD, epitaxial growth and the like, in addition to vacuum deposition.

Formation of Wiring Circuit Pattern A photosensitive resist film, for example, a plating resist film 11 is formed, for example, on the copper vapor deposition layer 10. The plating resist film 11 is exposed and developed using the inner wiring circuit pattern as a mask. As a result, the plating resist film 11 is selectively removed as shown in FIG. That is, the portion of the plating resist film 11 that becomes the wiring circuit pattern including the blind via holes 9 is removed.

Next, a second layer of a wiring layer is formed. The second layer may be a conductor layer, for example, a copper plating layer 12.
Is formed to a thickness of, for example, 2 μm. This second plating layer 1
2 is formed to be thicker than the thickness of the vapor deposition layer 10. As the thickness, a thickness corresponding to a current capacity flowing through the wiring, stress distortion, or the like is selected.

As a result, a copper plating layer 12 is formed on the copper deposition layer 10 as shown in FIG. This plating layer 1
2 is also formed on the inner wall surface of the blind via hole 9 at the same time. For example, in order to mainly form a film on the exposed copper vapor deposition layer 10 by this film forming means, it is desirable to perform electrolytic plating. This second layer forming means may be any means for forming a film thicker than the first vapor deposition layer.

Next, the plating resist film 11 is removed, for example, by liquid phase etching, so that a laminate of a copper vapor deposition layer 10 and a copper plating layer 12 remains as shown in FIG.
Next, the exposed copper deposition layer 10 is removed. This removing means is, for example, soft etching (ashing), liquid phase etching with an acidic etching solution, or the like.

As a result, an inner wiring circuit pattern 13 having a laminated structure of a copper vapor deposition layer 10 and a copper plating layer 12 is formed as shown in FIG. At the same time, an interlayer connector (power supply layer) with high connection reliability is also formed in the blind via hole 9.

Further, in the case of manufacturing a multilayer printed wiring board, the processes shown in FIGS. 2A to 2G are repeated as many times as desired to form a build-up layer, an inner wiring layer and the like. By carrying out, a multilayer printed wiring board can be obtained. In the above-described embodiment, the conductor for the wiring layer 6 and the wiring circuit pattern 13 may be, for example, gold, silver, nickel, aluminum, chromium, tin, or the like alone, or may be a composite or a laminate, in addition to the copper.

Further, any of the above-mentioned vapor deposition means for the first layer can be applied as long as it is vapor deposition in a vacuum such as lamp heating vapor deposition and electron beam heating vapor deposition. An aggregate having a particle diameter of the deposited copper film of 0.007 to 0.85 μm is desirable. The thickness of the deposited film is desirably 0.5 to 1.5 μm. Furthermore, the second copper plating films 5 and 12 are formed by electroplating with a current density of 3 A / dmm ² or more.

For example, by electroplating at a current density of 5 A / dmm ² , a copper plating layer having a thickness of, for example, 7 μm can be formed. If the current density is 8 A / dnmm ² or more, the plating film quality is poor. Conditions of the electroplating, for example, the concentration of copper sulfate _{(CuSo 4 .5H 2 O) 180~242g} /
L, sulfuric acid (H ₂ SO ₄ ) concentration 44-62 g / L, chloride ion (CL ⁻ ) 20-80 mg / L, thiourea 0.0
An electroplating process of copper can be performed with an electrolyte of 1 g / L and dextrin 0.01 g / L.

As described above, according to this embodiment, the wiring layer has a laminated structure, and the conductor layer formed in a vacuum is used as the underlayer. It becomes possible to manufacture wiring electric circuits with a high yield.

In the above embodiment, since the first conductor layer is processed and formed in a vacuum such as vapor deposition, it is possible to manufacture a build-up type multilayer printed wiring board having good circuit adhesion. Further, in the above embodiment, the wiring layer
Although the embodiment of the same conductor in which the copper plating layer is formed on the copper vapor deposition layer has been described, it is not necessary to configure the same conductor. For example, as shown in FIG. 3, a chromium plating layer 32 having a thickness of, for example, 3 μm may be formed on a thin layer 31 having a thickness of, for example, 1 μm obtained by sputtering copper.

Further, in the above embodiment, the embodiment in which the interlayer connection body is formed in the blind via hole 9 simultaneously with the formation of the inner wiring circuit pattern has been described. It can also be formed on the inner wall of the hall. An embodiment of this through hole will be described with reference to FIG. FIG. 4 is a cross-sectional view showing a method of forming a through hole in the order of steps.

A first through-hole 42 is formed at a predetermined through-hole forming position on the insulator substrate 41 as shown in FIG. This forming method includes a method using laser light, a method using photoetching, and the like. On the front and back surfaces of the insulator substrate 41, a conductor, for example, a copper CVD layer 43, which is a first wiring layer, is formed as shown in FIG. This film is a metal CVD film formed in a vacuum. This CVD layer 43 is also formed on the inner wall surface of the through hole 42.

A second wiring layer is formed on the surface of the CVD film 43 on which the inner wiring layer is to be formed. In this film formation, a copper plating layer 44 is formed by an electroless plating method as shown in FIG. Next, the copper plating layer 44 and the copper CV
The first inner wiring layer is constituted by the laminated structure of the D layer 43. On the first inner wiring layer, a build-up layer, that is, an insulator layer 45 is formed, for example, as shown in FIG.

A second through-hole 46 is formed in the insulating layer 45 so as to be aligned with the first through-hole 42. This state is shown in FIG. Next, a film, for example, a copper CVD layer 47 is formed on the insulator layer 45 in a vacuum. This state is shown in FIG. A copper plating layer 48 is formed on the CVD layer 47. The laminated structure of the plating layer 48 and the CVD layer 47 constitutes a second inner wiring layer. Thus, the through holes 42, 46
Is formed to penetrate through. Further, in the case of forming a multilayer structure, it can be formed by repeating the steps from FIG.

In the above embodiment, an embodiment applied to a build-up type multilayer printed wiring board has been described. However, the present invention can be applied to any wiring layer of a printed wiring board. For example, the present invention may be applied to an inner wiring layer and an outer wiring layer of a multilayer multilayer wiring board. In this case, similarly to the above embodiment, an electric circuit with fine wiring can be formed with a high yield.

That is, a plurality of desired wiring boards having wiring layers formed on the front and back surfaces are prepared on an epoxy resin substrate by the process shown in FIG. 1, and a prepreg is interposed between the respective wiring boards and laminated. By applying pressure, a laminated multilayer printed wiring board can be obtained.

[0054]

As described above, according to the present invention,
It is possible to manufacture a finely processed wiring circuit with a high yield.

Further, it is possible to manufacture a build-up type multilayer printed wiring board of a wiring circuit having good adhesion.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining an embodiment in which the present invention is applied to a method for forming a first inner wiring layer on a printed wiring board in the order of steps.

FIG. 2 is a cross-sectional view for explaining an embodiment applied to a method of forming a second inner wiring layer on the first inner wiring layer in FIG. 1 in the order of steps.

FIG. 3 is a cross-sectional view for explaining another embodiment of the wiring layer shown in FIG. 1;

FIG. 4 is a cross-sectional view for explaining another embodiment of FIG. 2 in the order of steps.

[Explanation of symbols]

 1, 8: epoxy resin substrate, 2, 3, 10: copper evaporation layer, 4, 11: plating resist layer, 5, 12, 44, 48: copper plating layer, 6: inner wiring layer, 7: land, 9: Blind via hole, 13: Wiring circuit pattern, 41: Insulator substrate 42, 46 ... Through hole 43, 47 ... Copper CVD layer 45 ... Insulator layer

Continued on the front page (72) Inventor Nobuo Tanaka 5-14-25 Ryoke, Kawaguchi-shi, Saitama F-term in Kawaguchi Plant of Toshiba Chemical Corporation 4E351 AA03 AA04 AA07 BB01 BB32 BB33 BB35 CC02 CC03 CC06 DD04 DD05 DD06 DD10 DD12 DD17 DD19 GG11

Claims (6)

[Claims] A conductor layer formed on the insulator in a vacuum, and a conductor plating layer provided on the conductor layer, wherein a wiring is formed in a laminated structure of the conductor layer and the conductor plating layer. A printed wiring board comprising a layer. 2. A first wiring comprising an insulating substrate, a copper vapor deposition layer provided on the insulating substrate, and a wiring layer in which a copper plating layer is laminated on the copper vapor deposition layer; A first wiring and an insulating layer provided on the insulating substrate; and a second wiring formed of a wiring layer formed by stacking a copper vapor deposition layer and a copper plating layer provided on the insulating layer. A printed wiring board, comprising: 3. A step of forming a conductor layer on the insulator in a vacuum, a step of forming a wiring layer having a conductor plating layer laminated on the conductor layer, and selectively etching the wiring layer. Forming a wiring circuit pattern by using the above method. 4. A step of forming a blind via hole in the insulator, a step of forming a conductor layer in a vacuum on the insulator including the blind via hole formed in this step, and plating a conductor on the conductor layer. A method for manufacturing a printed wiring board, comprising: a step of forming a wiring layer in which layers are stacked; and a step of selectively etching the wiring layer to form a wiring circuit pattern. 5. A step of forming a conductor layer on the insulator in a vacuum, a step of forming a mask pattern of a wiring pattern on the conductor layer, and a step of forming a conductor plating layer on the conductor layer. A method for manufacturing a printed wiring board, comprising: a step of removing the mask pattern; and a step of removing the exposed conductor layer. 6. The method for manufacturing a printed wiring board according to claim 3, wherein the means for forming the conductive layer in a vacuum is vacuum deposition, sputtering, or CVD. Production method.